Abstract: A photodetector is formed in a CMOS circuit using a junction field-effect transistor (JFET). The JFET/CMOS photodetector can be used to create an active pixel sensor for a CMOS digital imager, performing both photodetection and electrical signal amplification, allowing higher fill factors than with conventional APS imagers. A standard CMOS fabrication process is augmented with a small number of steps to integrate the JFET within the pixel, allowing the use of conventional CMOS fabrication plants.

Abstract: A MOS transistor with a controlled threshold voltage includes a SOI which includes a substrate composed of a semi-conducting material, a single crystal layer composed of a semi-conducting material and an insulating layer interposed between the substrate and the single crystal layer. The single crystal layer is formed therein with a source region, a drain region and a surrounded region surrounded by the source region and the drain region. The surrounded region includes a depletion layer having a composition surface which is in contact with the insulating layer. The MOS transistor comprises an EIB-MOS transistor of which the substrate is adapted to be applied with a voltage of a first polarity for inducing charges of a second polarity over the composition surface of the surrounded region.

Abstract: An electro-optical device having six image signal lines that are third layer leads comprising the same layer as data lines. A lead which is branched from one image signal line and crosses the other image signal lines is a parallel connection of a first layer lead and a second layer lead. The first layer lead comprises the same layer as the scanning lines in a display region and the second layer lead comprises the same layer as a barrier film of a thin film transistor (TFT) in the display region. Although the first and second layer leads have high resistance alone, the parallel connection can reduce resistance. In other portions, the second layer lead is used alone to improve the design versatility. Thus, the design versatility of peripheral circuits such as a sampling circuit in an electro-optical device is improved and the lead resistance in the peripheral circuit is reduced.

Abstract: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

Abstract: An imager temperature sensor and a current correction apparatus are provided which use dark pixel measurements from an imager chip during operation together with a fabrication process constant as well as a chip dependent constant to calculate chip temperature. The chip temperature may be used to generate a current correction signal. The correction signal is used to tune a current on the imager chip to correct for temperature variations.

Abstract: A device for amplifying and converting current signals into voltage signals for processing The current signals are delivered by sensors, e.g. optical transducers, magnetical heads. The current signals are first amplified using a current to current amplifier, the amplified current signals are then transported using electrical conductors and eventually amplified using a current to voltage amplifier. The invention may find application in consumer electronic devices, cars, planes, industrial machines.

Abstract: A liquid crystal display device comprises a pair of substrates (11, 12) bonded to each other by a sealing material (13) in the form of a frame provided therebetween, liquid crystal (14) held between the pair of substrates; a reflective layer (111) formed on one (11) of the substrates, and an alignment film (116) formed over the reflective layer (111) at the liquid crystal side. The surface of said one (11) of the substrates has a roughened area (11b) which is roughened and a flat area (11a) which is flat and surrounds the roughened area (11b). The alignment film (116) is formed in the roughened area (11b), and the sealing material (13) is formed in the flat area (11a).

Abstract: An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics.

Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.

Abstract: A light emitting module 10 is provided with a semiconductor light emitting device 21, a semiconductor light receiving device 22, a mount member 20 on which the semiconductor light emitting device 21 and semiconductor light receiving device 22 are mounted, a lens 32, and a lens holding member 30 for holding the lens 32. Part of light emitted by the semiconductor light emitting device 21 is reflected by a reflecting film 32c provided on a first surface 32a of the lens 32 to enter the semiconductor light receiving device 22. Therefore, the semiconductor light receiving device 22 can receive forward light from the semiconductor light emitting device 21, without using a half mirror.

Abstract: A semiconductor display device which includes the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask, and thus impurity concentrations of the Lov regions and the Loff regions can be independently controlled.

Abstract: A semiconductor device including an overcoat layer of a transparent material disposed on a substrate, a projection formed on the overcoat layer, a convex intralayer lens of an inorganic material formed to include the projection as a core and a transparent film with a flat top surface formed on the convex intralayer lens.

Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.

Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n? channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

Abstract: In the manufacture of a semiconductor laser device, sequentially grown on a sapphire substrate in the following order are a buffer layer, a first undoped GaN layer, a first super lattice defect reducing layer, a second undoped GaN layer, a second super lattice defect reducing layer, a third undoped GaN layer, a third super lattice defect reducing layer and a fourth undoped GaN layer. A device structure is then formed thereon. The first to third super lattice defect reducing layers each include five pairs of InGaN and AlGaN films alternately placed on one another in this order.

Abstract: A non-lead type, stacked-type semiconductor device includes a sealing body of insulative resin, a tab, leads, each having one surface exposed on a mounting surface of the sealing body, a first semiconductor chip located in the sealing body having a first circuit-forming surface and a second surface supported on the tab through adhesive, electrode pads formed in the periphery of the first surface, conductive wires for electrically connecting the electrode pads and the leads, a second semiconductor chip having a first circuit-forming surface and a second surface opposite to the first surface, and stacked and mounted on the first surface of the first semiconductor chip toward the second surface thereof, electrode pads formed on the first surface of the second semiconductor chip, and conductive wires for electrically connecting the electrode pads of the second semiconductor chip and the leads.

Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirement for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.

Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.

Abstract: The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size requirements for pixel sensor cells while reducing leakage, image lag and barrier problems typically associated with conventional photodiodes.

Abstract: A new grid metal design for image sensors is disclosed which is comprised of a semiconductor image sensor chip having a pixel region covering most of the chip and a logic circuit region on the chip periphery. The pixel region contains an array of image pixels where for each image pixel the majority of its area is occupied by a light sensing element and the other image pixel circuit elements are arranged in the periphery of the image pixel without overlapping the image-sensing element. A number of metal levels are of the first type, at which functional metal patterns exist both for the chip peripheral logic circuits and for the pixel circuit elements. A number of metal levels are of the second type, at which functional metal patterns exist only for the chip peripheral logic circuits and dummy metal patterns cover the pixel region except for the light sensing elements.

Abstract: A surface mounted power transistor is provided with a heat sink by positioning a mounting plate of a heat sink between the power transistor and a solder pad on the circuit board. The mounting plate of the heat sink is provided with a plurality of openings through which the solder of the solder pad flows during the solder reflow process so that the mounting plate is securely adhered between the power transistor and the circuit board. The mounting plate of the heat sink is connected thermally to an extension member which extends generally perpendicular to the mounting plate, the extension member in turn being connected to a heat dissipation surface which may be one or several fins.

Abstract: In a solid-state imaging device in which a N-type photoelectric conversion region is formed in a P−-type well region, a light-blocking film and a transparent conductive film are formed on the N-type photoelectric conversion region with a second interlayer insulation film interposed therebetween. By applying a negative voltage to the light-blocking film and the transparent conductive film, a P++-type inversion region is formed in a topmost part of the N-type photoelectric conversion region.

Abstract: A method and apparatus for high density nanostructures is provided. The method and apparatus include Nano-compact optical disks, such as nano-compact disks (Nano-CDS). In one embodiment a 400 Gbit/in2 topographical bit density nano-CD with nearly three orders of magnitude higher than commercial CDS has been fabricated using nanoimprint lithography. The reading and wearing of such Nano-CDS have been studied using scanning proximal probe methods. Using a tapping mode, a Nano-CD was read 1000 times without any detectable degradation of the disk or the silicon probe tip. In accelerated wear tests with a contact mode, the damage threshold was found to be 19 &mgr;N. This indicates that in a tapping mode, both the Nano-CD and silicon probe tip should have a lifetime that is at least four orders of magnitude longer than that at the damage threshold.

Abstract: A semiconductor device that has a p-n junction with a photosensitive region partially having a diffusion region and a non-diffused region when the p-n junction is subjected to a reverse bias voltage. When an incident light (e.g. a laser) is directed at the surface of the photosensitive region, hole-electron pairs are generated in the partial diffusion region within the photosensitive region. As a result, the current through the photosensitive region changes in a substantially linear fashion with the intensity of the incident light. The semiconductor device can be configured in a circuit to provide substantially linear power amplification. The semiconductor device can be configured by itself or with a complimentary device to form push-pull operations.

Abstract: A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Abstract: A threshold voltage change and degradation of the drain saturation current over a period of time of a MOS transistor are prevented by providing a permeable insulating film that serves as an inter-layer etching stopper layer on the surface of a plug, and an inter-layer insulating film that can be made from a low dielectric constant organic insulating film.

Abstract: In a solid-state image pick-up device 10 in which a microlens layer 16 is provided on a surface of a semiconductor substrate 11 having photoelectric converting units 12H and 12L for storing an electric charge corresponding to an amount of incident light arranged vertically and horizontally, a microlens 16H to be provided on the microlens layer 16 is disposed on only the photoelectric converting unit 12H to be used as a pixel having a high sensitivity and the microlens layer 16 in a position facing the photoelectric converting unit 12L to be used as a residual pixel having a low sensitivity has a planar structure 16L or a perforated structure 16L.

Abstract: A semiconductor light receiving device is provided, which comprises a semiconductor substrate, a collector region, a base region, and an emitter region, an insulating film covering the surface of the collector region, the base region, and the emitter region, a first metal line on the insulating film at a position corresponding to the base region and being electrically connected to the emitter region, and a second metal line on the insulating film at a position corresponding to a junction portion of the base region and the collector region and being electrically connected to the emitter region. The first metal line has a sloped surface such that incident light falling on the first metal line is reflected and directed toward the surface of the base region.

Abstract: In a thin film transistor (TFT), a mask is formed on a gate electrode, and a porous anodic oxide is formed in both sides of the gate electrode using a relatively low voltage. A barrier anodic oxide is formed between the gate electrode and the porous anodic oxide and on the gate electrode using a relatively high voltage. A gate insulating film is etched using the barrier anodic oxide as a mask. The porous anodic oxide is selectively etched after etching barrier anodic oxide, to obtain a region of an active layer on which the gate insulating film is formed and the other region of the active layer on which the gate insulating film is not formed. An element including at least one of oxygen, nitrogen and carbon is introduced into the region of the active layer at high concentration in comparison with a concentration of the other region of the active layer. Further, N- or P-type impurity is introduced into the active layer.

Abstract: An exemplary system and method for providing an acoustic plate wave apparatus is disclosed as comprising inter alia: a monocrystalline silicon substrate (200); an amorphous oxide material (220); a monocrystalline perovskite oxide material (230); a monocrystalline piezoelectric material (240); and a flexural plate wave component (250, 270) having an input interdigitated transducer (270), an output interdigitated transducer (250) and an optional support layer (260). Deposition or removal of material on or from an absorptive thin film sensor surface (210), or changes in the mechanical properties of the thin film (210) in contact with various chemical species, or changes in the electrical characteristics of a solvent solution exposed to the thin film (210) generally operate to produce measurable perturbations in the vector quantities (e.g., velocity, etc.) and scalar quantities (e.g., attenuation, etc.) of the acoustic plate modes.

Abstract: In a semiconductor light-emitting element, a first DBR and a second DBR, with a specified spacing left between them, form a resonator, and a single quantum well active layer is positioned at the loop of a standing wave within this resonator. The single quantum well active layer is composed of a Ga0.5In0.5P well layer and a pair of (Al0.5Ga0.5)0.5In0.5P barrier layers, which sandwiches the Ga0.5In0.5P well layer therebetween. The impurity concentration of the (Al0.5Ga0.5)0.5In0.5P barrier layers is higher than that of the Ga0.5In0.5P well layer. For example, the impurity concentration of the Ga0.5In0.5P well layer is set to 2×1016 cm−3, while the impurity concentration of the (Al0.5Ga0.5)0.5In0.5P barrier layers is set to 2×1018 cm−3.

Abstract: An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semiconductor layer and CuX layer made by implantation of a Group VIB element.

Abstract: A block, which is an object to be scanned, of a semiconductor integrated circuit includes a scan flip-flop and a combinational circuit. A serial-parallel conversion unit receives serial scan output data output from the scan flip-flop of the block and converts the serial scan output data into parallel scan output data. A scan output storage stores the parallel scan output data output from the serial-parallel conversion unit, and outputs the parallel scan output data stored to outside of the semiconductor integrated circuit.

Abstract: A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding decreases in threshold voltage due to dopant penetration, allowing consistent threshold voltage values to be maintained for all PMOS transistors on a single wafer. The nitrogen concentration gradient can be introduced by regulating the flow of nitrous oxide during RTN processing to cause an accumulation of atomic oxygen to develop within the process chamber.

Abstract: Disclosed is an ISFET comprising a H+-sensing membrane consisting of RF-sputtering a-WO3. The a-WO3/SiO2-gate ISFET of the present invention is very sensitive in aqueous solution, and particularly in acidic aqueous solution. The sensitivity of the present ISFET ranges from 50 to 58 mV/pH. In addition, the disclosed ISFET has high linearity. Accordingly, the disclosed ISFET can be used to detect effluent.

Abstract: A waveguide photodiode includes an n-type cladding layer, an n-type light confining layer, an i-type light absorption layer, a p-type light confining layer, and a p-type cladding layer buried in an Fe—InP blocking layer on a semiconductor substrate. At least one of the p-type light confining layer and the p-type cladding layer contains a p-type impurity selected from Be, Mg, and C. An undoped layer is preferably located between the i-type light absorption layer and the p-type light confining layer.

Abstract: The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.

Abstract: A functional device free from cracking and having excellent functional characteristics, and a method of manufacturing the same are disclosed. A low-temperature softening layer (12) and a heat-resistant layer (13) are formed in this order on a substrate (11) made of an organic material such as polyethylene terephthalate, and a functional layer (14) made of polysilicon is formed thereon. The functional layer (14) is formed by crystallizing an amorphous silicon layer, which is a precursor layer, with laser beam irradiation. When a laser beam is applied, heat is transmitted to the substrate (11) and the substrate (11) tends to expand. However, a stress caused by a difference in a thermal expansion coefficient between the substrate (11) and the functional layer (14) is absorbed by the low-temperature softening layer (12), so that no cracks and peeling occurs in the functional layer (14). The low-temperature softening layer (12) is preferably made of a polymeric material containing an acrylic resin.

Abstract: A sensor formed in a substrate of a first conductivity type in a first concentration to express a first intrinsic potential includes CMOS circuitry to control the sensor, a first well of the first conductivity type in a second concentration (greater than the first concentration) formed in the substrate to express a second intrinsic potential, and a photodiode region of a second conductivity type formed in the first well. The first and second intrinsic potentials induce a field between the substrate and the first well that repels photo generated charge from drifting from the substrate into the first well. Alternatively, a sensor formed in a substrate of a first conductivity type includes CMOS circuitry to control the sensor, a first well of a second conductivity type formed in the substrate, a second well of the first conductivity type formed in the first well, and a photodiode region of the second conductivity type formed in the second well.

Abstract: This invention discloses the basic chip architecture and packing configuration required to build an all silicon opto-coupler in which a forward biased silicon PN junction diode is used as the LED. Construction of the LED and the detector are disclosed as well as the package chip configuration. Methods for isolating circuit structures from the LED are also disclosed so that CMOS and bipolar circuits can freely added to the transmitting chip as well as the receiving chip. Bi-directional data transmission and multi-channel operation is also shown.

Abstract: A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

Abstract: A monolithic photodetector including a photodiode, a precharge MOS transistor, a control MOS transistor, a read MOS transistor, and a transfer MOS transistor, the photodiode and the transfer transistor being formed in a same substrate of a first conductivity type, the photodiode including a first region of the second conductivity type formed under a second region of the first conductivity type more heavily doped than the first region, and above a third region of the first conductivity type more heavily doped than the substrate, the first region being the source of the second conductivity type of the transfer transistor, the second and third regions being connected to the substrate and being at a fixed voltage.

Abstract: In a semiconductor device having a built-in contact-type sensor, a height of a surrounding part of a sensor part from the exposed surface of the sensor part is reduced. The semiconductor device has a semiconductor element having a built-in sensor. The semiconductor element has a circuit forming surface and a back surface opposite to the circuit forming surface. The contact-type sensor and electrodes are formed on the circuit forming surface. Back electrodes are formed on the back surface. Conductive members extend through the semiconductor device from the electrodes to the back electrodes. A protective film covers the circuit forming surface in a state where the surface of the contact-type sensor is exposed. External connection terminals are electrically connected to the back electrodes.

Abstract: A method of manufacturing a semiconductor device with the use of a laser crystallization method is provided which can prevent grain boundaries from being formed in a channel forming region of a TFT and which can avoid substantial reduction in TFT mobility, reduction in on current, and increase in off current due to the grain boundaries, and a semiconductor device manufactured by using the manufacturing method is also provided. Stripe shape or rectangular shape unevenness is formed only in a driver circuit. Continuous wave laser light is irradiated to a semiconductor film formed on an insulating film along the stripe unevenness of the insulating film or along a major axis or minor axis of the rectangular unevenness. Although it is most preferable to use the continuous wave laser light at this point, pulse wave laser light may also be used.

Abstract: A structure for doping of III-V compounds is provided. The structure is a multi-layered structure in which layers of dopant are alternated with layers of initially undoped III-V compound. Dopant diffuses from the layers of dopant into the layers of III-V compound. The structure does not facilitate the introduction of impurities into the III-V compound during the diffusion of the dopant.

Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-including metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-including metal layer and the insulating interlayer.

Abstract: The invention relates to a bipolar transistor and a method for producing same. The aim of the invention is to provide a bipolar transistor and a method for producing same, which during the use of a single-process poly-silicon technology with differential epitaxis for the production of bases overcomes the disadvantages of conventional systems, so as notably further to improve the high-speed properties of a bipolar transistor, provide the most conductive connections possible between the metal contacts and the active (internal) transistor region as well as a minimized passive transistor surface, while at the same time avoiding greater process complexity and increased contact resistances. To this end a surface relief is produced in the active emitter region by a wet-chemical process. A single-process poly-silicon bipolar transistor having a base produced by epitaxis in accordance with the invention permits a reduction in external base resistance without causing a deterioration in emitter properties.

Abstract: A solid-state imaging device such as a CMOS image sensor includes photodiode portions that are designed for both improving sensitivity and reducing crosstalk of electrical charge to adjacent pixels. A p-type layer, which has an impurity concentration that is lower than that of a substrate p+-layer, is formed on the substrate p+-layer which is a p-type silicon semiconductor substrate of high impurity concentration. An n-type photoelectric conversion region is provided at a position on the upper side of the p-type layer. By means of this configuration, of the photoelectrons that are generated in the p-type layer, electrons that diffuse in the direction of the substrate are reliably captured in substrate p+-layer and annihilated by recombination.

Abstract: A nuclear spin control device comprises a first semiconducting layer with spin-up carriers, a second semiconducting layer with spin-down carriers; and a third semiconducting layer arranged between the first and the second semiconducting layers. The third semiconducting layer can be tunnelled selectively by the spin-up carriers and the spin-down carriers such that nuclear spin in the third semiconducting layer selectively interacts with the carriers so as to be oriented into a desired direction. The device may be adapted to control the shape of a wave function so as to cover nuclear spins in the third semiconducting layer and propagate information of one nuclear spin to another nuclear spin.