Abstract: In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an electromagnetic shield that shields the substrate from AC signals carried by a contact pad made from another conductive layer on a backside of the substrate. The conductive layers can also be used to form capacitor/rectifier networks. Manufacturing methods are also provided.

Abstract: A semiconductor device comprises a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type, a base layer of a second conductivity type provided in the first semiconductor layer, for defining a vertical MISFET including source regions and a gate electrode on a gate insulation film, a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer, a guard ring region of the second conductivity type provided around SBD-forming region, a first main electrode disposed above the first semiconductor layer and provided in common as both a source electrode of the MISFET and an anode of the SBD, a surface gate electrode disposed above the first semiconductor layer, and a second main electrode provided in common as a drain electrode of the MISFET and a cathode of the SBD.

Abstract: A microwave monolithic integrated circuit comprises a T-shaped gate electrode including a Schottky gate electrode formed on a first region of a compound semiconductor substrate, a pair of ohmic electrodes making an ohmic contact with a surface of the substrate in the first region at respective sides of the T-shaped gate electrode, a lower capacitor electrode pattern formed on a second region of the compound semiconductor substrate with a composition substantially identical with a low-resistance, top electrode constituting the T-shaped gate electrode on the Schottky gate electrode, a dielectric film formed on the lower electrode pattern, and an upper electrode pattern formed on the dielectric film.

Abstract: A vertical MIM capacitor (140) including a first conductive line (124) and second conductive line (136) sandwiched around a vertical portion of a capacitor dielectric (134). Additional conductive lines (136) may be positioned vertically proximate first conductive lines (124) separated by another vertical portion of capacitor dielectric (134) to form a double-sided capacitor (142), increasing the capacitance. A plurality of vertical MIMcaps (140, 142) may be coupled together in parallel to increase the capacitance.

Abstract: A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentration than in the inner zone is provided in the inner zone. The turnoff performance in such geometrically coupled power diodes, in contrast to the turnoff performance of pin power diodes (in the Read-diode version) with spaced charge coupling, is largely temperature-independent. Hybrid diodes with optimized conducting-state and turnoff performance can be made from such FCI diodes. FCI diodes are preferably used in conjunction with switching power semiconductor elements, as voltage limiters or free running diodes.

Abstract: The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires (6) go perpendicularly to the gate and drain bonding wires (7, 8). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.

Abstract: Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped silicon carbide charge coupling region of second conductivity type (e.g., an in-situ doped epitaxial P-type region) is also provided in the trench. This charge coupling region forms a P-N rectifying junction with the drift region that extends along a sidewall of the trench. The drift region and charge coupling region are both uniformly doped at equivalent and relatively high net majority carrier doping concentrations (e.g., 1×1017 cm−3) so that both the drift region and charge coupling region can be depleted substantially uniformly when blocking reverse voltages.

Abstract: A semiconductor device has first and second opposed major surfaces (10a and 10b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 130) with the first region (11) and separates the first region (11) from the first major surface (10a) while the third region (14) separates the first region (11) from the second major surface (10b). A plurality of semi-insulating or resistive paths (21) are dispersed within the first region (1′) such that each path extends through the first region from the second to the third region. In use of the device when a reverse biasing voltage is applied across the rectifying junction (13 or 130) an electrical potential distribution is generated along the resistive paths (21) which causes a depletion region in the first region (11) to extend through the first region (11) to the third region (14) to increase the reverse breakdown voltage of the device.

Abstract: The present invention relates to a structure for ground connection on a component including a vertical MOS power transistor and logic components, the substrate of a first type of conductivity of the component corresponding to the drain of the MOS transistor and the logic components being formed in at least one well of the second type of conductivity and on the upper surface side of the substrate. In the logic well, a region of the first type of conductivity is formed, on which is formed a metallization, to implement, on the one hand, an ohmic contact, and on the other hand, a rectifying contact.

Abstract: A vertical field effect transistor (1400) and diode (1450) formed on a single III-V substrate. The diode cathode and the transistor drain or collector may be formed in a common layer (1408).

Abstract: A method for producing a field effect transistor includes: a first step of forming an insulating film over a substrate; a second step of dry etching the insulating film to form a rectangular insulating pattern having side surfaces; a third step of forming a gate electrode film over the substrate having the rectangular insulating pattern; a fourth step of conducting substantially anisotropic etching of the gate electrode film to form side walls made of the gate electrode film adjacent to the side surfaces of the rectangular insulating pattern; and a fifth step of removing at least a portion of the insulating pattern to form a side wall gate.

Abstract: An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.

Abstract: A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined doping concentrations with the doping concentration of the channel regions being greater than the doping concentration of the drift region.

Abstract: A P.sup.- layer (51) is formed between a P base layer (43) and an N.sup.- layer (42) so as to be in contact with the P base layer (43), facing an insulating film (46) of a trench (45) with the N.sup.- layer (42) between. In the configuration, a depletion layer extends to the P.sup.- layer (51) to relieve an electric field at a tip end portion of the trench (45) and a channel length can be lessened. Therefore, it is possible to provide an insulated gate semiconductor device of high breakdown voltage and low On-resistance.

Abstract: An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural P.sup.+ -type area units are positioned under and facing the Schottky barrier electrode. An N.sup.+ -type area is disposed in the vicinity of the P.sup.+ -type units. The impurity concentration is such as to cause an avalanche breakdown in at least a portion of the surfaces.

Abstract: A static induction transistor includes a substrate and a drift layer with different doping levels. At least two mesas are formed on the drift layer and a heavily doped region is positioned on a top surface of each of the mesas. A gate contact extends along a bottom of a recess between the mesas and along a side of each of the mesas forming the recess. The gate contact also extends along a portion of the top surface of each of the mesas. In one embodiment of the invention, a notch is formed in the top surface of the mesas between the gate contact and the heavily doped region.

Abstract: A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed.

Abstract: A high speed soft recovery diode having a large breakdown voltage is disclosed. Anode P layers (3) are selectively formed in a top portion of an N.sup.- body (2). A P.sup.- layer (4a) is disposed in the top portion of the N.sup.- body (2) so as to be spacewise complementary to the anode P layers (3). In the N.sup.- body (2), P regions (5) are selectively formed below the P.sup.- layer (4a). On the N.sup.- body (2), an anode electrode (6) is disposed in contact with both the P.sup.- layer (4a) and the anode P layers (3). A cathode electrode (7) is disposed under the N.sup.- body (2) through a cathode layer (1). When the diode is reverse-biased, a depletion layer does not have a sharply curved configuration due to the P regions (5). Hence, concentration of electric field is avoided and a breakdown voltage would not deteriorate. During forward-bias state of the diode, injection of excessive holes from the anode P layers (3) into the N.sup.- body (2) is prevented, thereby reducing a recovery current.

Abstract: A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET).

Abstract: A junction field-effect transistor is disclosed that comprises a bulk single crystal silicon carbide substrate having respective first and second surfaces opposite one another, the substrate having a single polytype and having a concentration of suitable dopant atoms so as to make the substrate a first conductivity type. A first epitaxial layer of silicon carbide is formed on the first surface of the substrate, and having a concentration of suitable dopant atoms that give the first epitaxial layer the first conductivity type. A second epitaxial layer of silicon carbide is formed on the first epitaxial layer, the second epitaxial layer having a concentration of suitable dopant atoms to give the second epitaxial layer a second conductivity type opposite from the first conductivity type.

Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

Abstract: A semiconducting component with a Schottky junction with stacked electrodes has a lower electrode forming an emitter or source, a central electrode forming a base or grid and an upper electrode forming either a collector or a drain. Semiconductor material is between the upper electrode and the lower electrode. The central control electrode is in the form of several adjacent conducting fingers. An insulating material is in the region directly below the fingers between the control electrode and the lower electrode, thereby reducing parasitic capacitance between the control electrode and the lower electrode.