Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) is disclosed. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer, and source/drain regions with lightly doped drain (LDD) regions in the semiconductor substrate. The germanium layer supplies carriers into the epitaxial layer so that short channel effects are reduced.

Abstract: A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.

Abstract: A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening.

Abstract: There is provided a method of manufacturing a semiconductor device, including forming a structure including a first layer containing Si and a metal oxide layer in contact with the first layer, the metal oxide layer having a dielectric constant higher than that of silicon oxide, and heating the structure in an atmosphere containing He and/or Ne.

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1,0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1,0-?m thick and its surface dislocation density is less than 106/cm2.

Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.

Abstract: An exemplary organic semiconductor copolymer includes a polymeric repeat structure having a polythiophene structure and an electron accepting unit. The electron accepting unit has at least one electron-accepting heteroaromatic structure with at least one electron-withdrawing imine nitrogen in the heteroaromatic structure or a thiophene-arylene comprising a C2-30 heteroaromatic structure. Methods of synthesis and electronic devices incorporating the disclosed organic semiconductors, e.g., as a channel layer, are also disclosed.

Abstract: High-Voltage Lateral MOSFET and Lateral Double-diffused MOS (LDMOS) for HV power applications with multiple paths for conduction in the drain extension and methods of fabrication are described.

Abstract: A semiconductor device includes a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate and a constituent of the semiconductor layer including a nitride semiconductor different from a constituent of the substrate, a via hole provided in the substrate and configured to extend from a rear surface side of the substrate to the semiconductor layer, a ground electrode formed on an inner wall of the via hole, a contact layer provided in the semiconductor layer and configured to extend from a surface of the semiconductor layer to the ground electrode, a gate electrode and a drain electrode, each of which being formed on the semiconductor layer, and a source electrode formed on the semiconductor layer and connected to the ground electrode through the contact layer.

Abstract: A semiconductor device includes: a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate, a plurality of gate electrodes formed on the semiconductor layer, a plurality of source electrodes formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, a via hole configured to extend from a substrate side of the semiconductor layer to a rear surface of the source electrode, a ground electrode which is formed on an inner wall of the via hole and on the rear surface of the substrate and connects the plurality of source electrodes, and a first air bridge interconnection which is formed on a surface side of the source electrode and connects the plurality of source electrodes.

Abstract: A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.

Abstract: An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.

Abstract: A field-effect transistor includes source, drain, and gate electrodes; a crystalline or polycrystalline layer of inorganic semiconductor; and a dielectric layer. The layer of inorganic semiconductor has an active channel portion physically extending from the source electrode to the drain electrode. The inorganic semiconductor has a stack of 2-dimensional layers in which intra-layer bonding forces are covalent and/or ionic. Adjacent ones of the layers are bonded together by forces substantially weaker than covalent and ionic bonding forces. The dielectric layer is interposed between the gate electrode and the layer of inorganic semiconductor material. The gate electrode is configured to control a conductivity of an active channel part of the layer of inorganic semiconductor.

Abstract: A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.

Abstract: The invention provides a sheet for optical-semiconductor element encapsulation, which has a multilayer structure including at least two resin layers. The at least two resin layers include: (A) an outermost resin layer (layer A) that is to be brought into contact with one or more optical semiconductor elements; and (B) a resin layer (layer B) disposed on the layer A and having a lower refractive index than that of the layer A. Also disclosed is a process for producing an optical semiconductor device using the sheet.

Abstract: A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surrounding the pore. Through the use of selective deposition techniques, the adhesion-promoting material can be positioned where needed and the lower electrode may be defined in a fashion that may reduce shunting current, reduce device current requirements, and increase dynamic range in some embodiments.

Abstract: Floating conducting regions at floating potentials are placed on a substrate surface between adjacent conducting regions to which predetermined potentials are applied. This makes it possible to block the spread of a depletion layer to the substrate between the conducting impurity regions. Thus, the leakage of high-frequency signals can be suppressed. In particular, in a case where a floating conducting region is placed between a peripheral impurity region of a common input terminal pad and a resistor in a switch circuit device, it is possible to suppress the leakage of high-frequency signals from an input terminal to control terminals which become high frequency GND and to suppress an increase in insertion loss.

Abstract: A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surrounding the pore. Through the use of selective deposition techniques, the adhesion-promoting material can be positioned where needed and the lower electrode may be defined in a fashion that may reduce shunting current, reduce device current requirements, and increase dynamic range in some embodiments.

Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.

Abstract: Provided are a vertical carbon nanotube field effect transistor (CNTFET) and a method of manufacturing the same. The method includes: forming a first electrode on a substrate; forming a stack of multiple layers (“multi-layer stack”) on the first electrode, the multiple layers including first and second buried layers and a sacrificial layer interposed between the first and second buried layers; forming a vertical well into the multi-layer stack; growing a CNT within the well; forming a second electrode connected to the CNT on the multi-layer stack into which the well has been formed; forming a protective layer on the second electrode; removing the sacrificial layer and exposing the CNT between the first and second buried layers; forming a gate insulating layer on the exposed surface of the CNT; and forming a gate enclosing the CNT on the gate insulating layer.

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1.0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1.0 ?m thick and its surface dislocation density is less than 106/cm2.

Abstract: The invention involves an array to couple a live cell, in particular a nerve cell, with an electronic circuit to pick up directly or indirectly electrically active cell signals and/or to electronically stimulate the cell, where the coupling array comprises a transistor (T1) with a double gate, where one of the gates is designed as a control gate (CG) to select the transistor via external control signals, and the other gate (FG) is connected to an electrically conducting contact element (1) which may be brought into contact with the cell (2) to register changes in the electric properties of the cell.

Abstract: The principal surface of a p-type SiC substrate (1) is formed of a face intersecting (0001) Si-face at 10 to 16°. An n+ source region (2) and an n+ drain region (3) are formed in a surface layer portion at the principal surface of the p-type SiC substrate (1) so as to be separated from each other. A gate electrode (5) is formed on a gate oxide film (4) on the principal surface of the p-type SiC substrate (1).

Abstract: Disclosed herein is a composite-structured organic semiconductor polymer for an organic thin film transistor which contains quinoxaline rings in the backbone of the polymer. According to the organic semiconductor polymer, since quinoxaline rings having n-type semiconductor characteristics, such as high electron affinity, are incorporated into a polythiophene having p-type semiconductor characteristics, the organic semiconductor polymer simultaneously exhibits both p-type and n-type semiconductor characteristics. In addition, the polythienylquinoxaline derivative exhibits high solubility in organic solvents, co-planarity and stability in air. Furthermore, when the polythienylquinoxaline derivative is used as an active layer of an organic thin film transistor, the organic thin film transistor exhibits a high charge carrier mobility and a low off-state leakage current.

Abstract: The compound semiconductor device comprises an i-GaN buffer layer 12 formed on an SiC substrate 10; an n-AlGaN electron supplying layer 16 formed on the i-GaN buffer layer 12; an n-GaN cap layer 18 formed on the n-AlGaN electron supplying layer 16; a source electrode 20 and a drain electrode 22 formed on the n-GaN cap layer 18; a gate electrode 26 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; a first protection layer 24 formed on the n-GaN cap layer 18 between the source electrode 20 and the drain electrode 22; and a second protection layer 30 buried in an opening 28 formed in the first protection layer 24 between the gate electrode 26 and the drain electrode 22 down to the n-GaN cap layer 18 and formed of an insulation film different from the first protection layer.

Abstract: A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat ?-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a gate insulating structure comprised of a first oxide layer that includes a mixture of indium and gallium oxide compounds (30) positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer. Together the lower indium gallium oxide compound layer and the second insulating layer form a gate insulating structure. The gate insulating structure and underlying compound semiconductor layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The first oxide layer serves to passivate and protect the underlying compound semiconductor surface from the second insulating layer and atmospheric contamination.

Abstract: A method for making an IC on a surface of a planar substrate includes forming a continuous first layer on the surface of the substrate and pressing a surface of a stamp into the first layer to produce a pattern of non-intersecting smooth regions on the surface. A rough region of the surface of the first layer laterally borders and laterally surrounds each smooth region of the surface of the first layer. The pattern of smooth and rough regions on the surface of the first layer copies a pattern of smooth and rough areas on the surface of the stamp. The method also includes forming a continuous second layer on the patterned first layer. The first layer is one of a dielectric layer and an organic semiconductor layer, and the second layer is the other of a dielectric layer and an organic semiconductor layer.

Abstract: A plasma oscillation switching device of the present invention comprises semiconductor substrate 101; first barrier layer 103 that is composed of a III-V compound semiconductor and formed on the substrate; channel layer 104 that is composed of a III-V compound semiconductor and formed on the first barrier layer; second barrier layer 105 that is composed of a III-V compound semiconductor and formed on the channel layer; source electrode 107, gate electrode 109 and drain electrode 108 provided on the second barrier layer, wherein the first barrier layer includes n-type diffusion layer 103a, the second barrier layer includes p-type diffusion layer 105a, the band gap of the channel layer is smaller than the band gaps of the first and the second barrier layers, two-dimensional electron gas EG is accumulated at the conduction band at the boundary between the first barrier layer and the channel layer, two-dimensional hole gas HG is accumulated at the valence band at the boundary between the second barrier layer and

Abstract: Provided is a field effect transistor. The field effect transistor includes an insulating vanadium dioxide (VO2) thin film used as a channel material, a source electrode and a drain electrode disposed on the insulating VO2 thin film to be spaced apart from each other by a channel length, a dielectric layer disposed on the source electrode, the drain electrode, and the insulating VO2 thin film, and a gate electrode for applying a predetermined voltage to the dielectric layer.

Abstract: A method for forming a transistor includes forming a gate dielectric layer over a portion of a semiconductor substrate, the substrate being substantially free of silicon; defining a gate electrode over a portion of the gate dielectric layer; and introducing ions into the substrate proximate the gate electrode to define source and drain regions. A transistor includes a semiconductor substrate that is substantially free of silicon and a gate dielectric layer over a portion of the substrate. The transistor can also include a gate electrode over a portion of the gate dielectric layer and introduce ions proximate the gate electrode, defining source and drain regions.

Abstract: A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT. Another feature of the present invention is that gate electrode comprises a first conductive layer and a second conductive layer and portion of the gate wiring has a clad structure comprising the first conductive layer and the second conductive layer with a low resistance layer interposed therebetween.

Abstract: An electronic device containing a polythiophene wherein R is an alkyl alkoxy; x represents the number of R groups; R? is CF3, alkoxy, alkyl, or optionally alkylene; y and z represent the number of segments; and a and b represent the mole fractions of each moiety, respectively, wherein the sum of a+b is equal to about 1.

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Abstract: A semiconductor device has a first semiconductor layer composed of a group III-V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III-V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.

Abstract: A semiconductor device has a first semiconductor layer composed of a group III-V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III-V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.

Abstract: A water flow regulating device that connects to a faucet and allows a user to set water temperature and pressure that flows from the faucet, and then turn it off and on without having to readjust the water pressure or temperature. Control of the water flow is accomplished through a manual switch located on the faucet housing or by a variety of push switches that could be activated by the hip, elbow, knee, or foot for hands free operation.

Abstract: A power semiconductor device includes a substrate of first conductivity having a dopant concentration of a first level. The substrate is a group III-V compound material. A transitional layer of first conductivity is epitaxially grown over the substrate. The transitional layer has a dopant concentration of a second level and is a group III-V compound material. An epitaxial layer of first conductivity is grown over the transitional layer and has a dopant concentration of a third level. Electrical currents flow through the transitional and epitaxial layers when the device is operating.

Abstract: A base of an optoelectronic device is disclosed. The present invention comprises an opening and a reflective surface. The base of the optoelectronic device incorporates with a transparent conductive substrate and an optoelectronic element to construct the optoelectronic device, wherein the optoelectronic element is disposed on the transparent conductive substrate, and the opening is used to hold the optoelectronic element. Moreover, the transparent conductive substrate is placed on the top of the opening, and the reflective surface is located at the bottom in the opening.

Abstract: Novel substituted pentacenes and electronic devices made with those substituted pentacenes are disclosed.

Abstract: A ferroelectric memory cell formed on a monocrystalline silicon underlayer, either an epitaxial silicon contact plug to a transistor source or drain or silicon gate region for which the memory cell forms a non-volatile gate. A conductive barrier layer of doped strontium titanate, whether cationically substituted, such by lanthanum or niobium for strontium and titanium respectively, or anionically deficient, is epitaxially grown over the silicon, and a lower metal oxide electrode layer, a ferroelectric layer and an upper metal oxide electrode layer are epitaxially grown on the barrier layer. No platinum barrier is needed beneath the ferroelectric stack. The invention can be applied to many other functional oxide materials of the Ruddlesden-Popper and devices including micromachined electromechanical (MEM) devices and ferromagnetic tri-layer devices.

Abstract: The present invention provides a transistor device that does not experience the problems associated with the prior art transistor devices. The transistor device includes a dielectric region located in a trench in a semiconductor substrate and a source region and a drain region located in the trench. The source region and drain region are at least partially on the dielectric region. The transistor device further includes a channel region located in the trench between the source region and drain region and at least partially on the dielectric region.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.

Abstract: An electronic device containing a polythiophene of Formula (I) wherein R and R′ are side chains; A is a divalent linkage; x and y represent the number of unsubstituted thienylene units; z is 0 or 1, and wherein the sum of x and y is greater than about zero; m represents the number of segments; and n represents the degree of polymerization.

Abstract: An Si1−yGey layer (where 0<y<1), an Si layer containing C, a gate insulating film and a gate electrode are formed in this order on a semiconductor substrate. An Si/SiGe heterounction junction is formed between the Si and Si1−yGey layers. Since C is contained in the Si layer, movement, diffusion and segregation of Ge atoms in the Si1−yGey layer can be suppressed. As a result, the Si/Si1−yGey interface can have its structural disorder eased and can be kept definite and planar. Thus, the mobility of carriers moving along the interface in the channel can be increased. That is to say, the thermal budget of the semiconductor device during annealing can be improved. Also, by grading the concentration profile of C, the diffusion of C into the gate insulating film can be suppressed and decline in reliability can be prevented.

Abstract: A semiconductor device having a high breakdown and capable of operating with a large current is realized using GaN-based compound semiconductors which exhibit good electric characteristics. Particularly, a semiconductor material having a larger band gap than semiconductor materials forming other semiconductor layers, for example, AlGaN is used for a semiconductor layer immediately below a gate electrode to realize a power device of vertical structure which comprises GTO or IGBT.