Abstract: A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1-x-yN, wherein x+y=1, 0≦x≦1, and 0≦y≦1; and forming a source electrode and a drain electrode by self-alignment using the gate electrode as a mask. A field-effect semiconductor device fabricated by the method is also disclosed.

Abstract: A channel layer 4 is formed on an n−-type epitaxial layer 2 and first gate areas 3, and field enhanced area(s) 5 and second gate areas 6 are formed on the first gate areas 3. Furthermore, n+-type source areas 7 and a third gate area 8 are formed on the second gate areas 6. These steps result in a device structure having a first J-FET with the n+-type source areas 7 and the n+-type substrate 1 as a source and drain and the first gate areas 3 at the right and left in the figure as a gate; and the second J-FET with the n+-type source areas 7 and the n+-type substrate 1 as a source and drain and the second gate areas 6 and the third gate area 8 as a gate. The first J-FET is normally-on, while the second J-FET is normally-off.

Abstract: Inexpensive, unannealed glass is used as a substrate. The surface of a polycrystalline silicon film doped with boron (B) or phosphorus (P) is oxidized with ozone at a processing temperature of 500° C. or below to form a silicon oxide film of 4 to 20 nm thick on the surface of polycrystalline silicon. On account of this treatment, the level density at the interface between the gate-insulating layer and the channel layer can be made lower, and a thin-film transistor having less variations of characteristics can be formed on the unannealed glass substrate.

Abstract: A traveling wave FET in which increasing distances between electrodes and the design of semiconductor regions associated with the various electrodes act to increase maximum gain parameters of the device. The relationship of the electrode series resistance is also considered in the design as it affects these gain parameters.

Abstract: A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surrounding the pore. Through the use of selective deposition techniques, the adhesion-promoting material can be positioned where needed and the lower electrode may be defined in a fashion that may reduce shunting current, reduce device current requirements, and increase dynamic range in some embodiments.

Abstract: The present invention provides an active pixel including a semiconductor layer (5) having dopants of a first conductivity type, wherein said semiconductor layer (5) comprises a first region (1) and a second region (2) both having dopants of a second conductivity type, said first region (1) and said second region (2) being adapted for collecting charge carriers in said semiconductor layer (5) generated by electromagnetic radiation, said first region (1) having an area and a boundary of this area, said semiconductor layer (5) further comprising a third region (3) having dopants of the first conductivity type at a higher doping level than the semiconductor layer (5), the third region (3) forming a barrier for substantially impeding the diffusion of said charge carriers to said second region (2). Over a part of its boundary, the first region (1) is separated from the third region (3) by a zone of the semiconductor layer (5) for creation of a depletion zone (9).

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Abstract: Submicron-dimensioned, MOSFET devices are formed using multiple implants for forming an impurity concentration distribution profile exhibiting three impurity concentration peaks at a predetermined depths below the semiconductor surface substrate. The inventive method reduces “latch-up” and “punch-through” with controllable adjustment of the threshold voltage.

Abstract: A germanium-on-insulator (GOI) device formed on a GOI structure with a buried oxide (BOX) layer disposed therein and an active layer disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The GOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions.

Abstract: A first silicon layer (Si layer), a second silicon layer (Si1Cy layer) containing carbon and a third silicon layer not containing carbon are stacked in this order on a silicon substrate. Since the lattice constant of the Si1-yCy layer is smaller than that of the Si layer, the conduction band and the valence band of the second silicon layer receive a tensile strain to be split. Electrons having a smaller effective mass, which have been induced by an electric field applied to a gate electrode, are confined in the second silicon layer, and move in the channel direction. Thus, an n-MOSFET having extremely high mobility can be obtained. Furthermore, if the second silicon layer is made of Sil-x-yGexCy, a structure suitable for a high-performance CMOS device can be formed. A high-performance field effect transistor can be provided at lower costs by using a heterojunction structure mainly composed of silicon.

Abstract: The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT. Another feature of the present invention is that gate electrode comprises a first conductive layer and a second conductive layer and portion of the gate wiring has a clad structure comprising the first conductive layer and the second conductive layer with a low resistance layer interposed therebetween.

Abstract: We have found that a single crystal, single domain oxide layer of thickness less than 5 nm can be grown on a (100) oriented GaAs-based semiconductor substrate. Similar epitaxial oxide can be grown on GaN and GaN-based semiconductors. The oxide typically is a rare earth oxide of the Mn2 0 3 structure (e.g., Gd2O3). The oxide/semiconductor interface can be of high quality, with low interface state density, and the oxide layer can have low leakage current and high breakdown voltage. The low thickness and high dielectric constant of the oxide layer result in a MOS structure of high capacitance per unit area. Such a structure advantageously forms a GaAs-based MOS-FET.

Abstract: A silicon carbide vertical MOSFET is provided which includes: a first conductivity type silicon carbide substrate; a first conductivity type drift layer comprising silicon carbide which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base region formed in a selected region of a surface layer of the first conductivity type drift layer; a first conductivity type source region formed in a selected region of the second conductivity type base region; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer; a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base region; and a drain electrode formed on a rear surface of the silicon carbide substrate.

Abstract: The specification describes a thin film transistor device in which the semiconductor layer is a fluorene oligomer having a molecular weight of less than 2000, and comprising from 1 to 10 fluorene ring units. These oligomers can be deposited by simple evaporation to give desirable semiconductor properties, e.g. high mobility.

Abstract: A silicon-on-insulator (SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hetero junction along a lower portion of the source/body junction.

Abstract: Disclosed is a compound semiconductor field effect transistor. The compound semiconductor field effect transistor has a charge absorption layer and a semiconductor laminated structure. The charge absorption layer includes a compound semiconductor layer of a first conductive type formed in a part of a compound semiconductor substrate having a semi-insulating layer. The semiconductor laminated structure includes at least an active layer including a compound semiconductor layer of a second conductive type epitaxially grown so as to cover the charge absorption layer and a region of the semi-insulating surface where the charge absorption layer is not formed. A source electrode is formed on the semiconductor laminated structure, being electrically connected to the charge absorption layer.

Abstract: A semiconductor device includes a capacitor having a pair of electrodes opposite to each other through a dielectric layer, and an element other than the capacitor, both of which are formed on a semiconductor substrate. An ohmic electrode of the element and one of the electrodes of the capacitor are formed of the same metallic material.

Abstract: A semiconductor-on-insulator (SOI) chip. The SOI chip includes a substrate; a buried oxide (BOX) layer disposed on the substrate; an active layer disposed on the BOX layer, the active layer having a first area made from silicon and a second area made from silicon-germanium; a first device fabricated in the first area of the active layer and having a silicon channel and a first threshold voltage; and a second device fabricated in the second area of the active layer and having a silicon-germanium channel and a second threshold voltage differing from the first threshold voltage. Also discussed are alternative forms of the SOI chip and methods of making the SOI chip.

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: A Field effect transistor semiconductor switch in which the channel of same is made from materials having an electrical conductivity which can undergo an insulator-metal transistor (i.e., Mott transition) upon application of an electric field. The channel contains the Mott material in which the charge carriers, either holes or electrons, are strongly correlated. The Mott transition determines the metal-insulator switching and is demonstrated to be controlled by an external gate electrode.

Abstract: An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.

Abstract: A structure and a fabrication method of a flat panel display comprising address lines with mending layers. A first address line and a first mending layer are formed on a substrate. The first mending layer and the first address line are electrically insulated with each other, and the first mending layer is partitioned into different segments by the first address line. A first insulating layer is formed over the substrate to cover at least the first mending layer and the first address line. A second address line is formed on the first insulating layer over the first mending layer and crossing the first address line. A second insulating layer is formed over the substrate to cover at least the second address line. A second mending layer is formed on the second insulating layer over the second address line and crossing the first address line.

Abstract: A thin film transistor (TFT) device structure based on an organic-inorganic hybrid semiconductor material, that exhibits a high field effect mobility, high current modulation at lower operating voltages than the current state of the art organic-inorganic hybrid TFT devices. The structure comprises a suitable substrate disposed with the following sequence of features: a set of conducting gate electrodes covered with a high dielectric constant insulator, a layer of the organic-inorganic hybrid semiconductor, sets of electrically conducting source and drain electrodes corresponding to each of the gate lines, and an optional passivation layer that can overcoat and protect the device structure. Use of high dielectric constant gate insulators exploits the gate voltage dependence of the organic-inorganic hybrid semiconductor to achieve high field effect mobility levels at very low operating voltages.

Abstract: A thin film transistor (TFT) device structure based on an organic semiconductor material, that exhibits a high field effect mobility, high current modulation and a low sub-threshold slope at lower operating voltages than the current state of the art organic TFT devices. The structure comprises a suitable substrate disposed with he following sequence of features: a set of conducting gate electrodes covered with a high dielectric constant insulator, a layer of the organic semiconductor, sets of electrically conducting source and drain electrodes corresponding to each of the gate lines, and an optional passivation layer that can overcoat and protect the device structure. Use of high dielectric constant gate insulators exploits the unexpected gate voltage dependence of the organic semiconductor to achieve high field effect mobility levels at very low operating voltages.

Abstract: A structure and method of forming an integrated circuit (e.g., field effect transistor) having a buried Mott-insulated oxide channel includes depositing source and drain electrodes over a substrate forming a Mott transition channel layer over the substrate and electrodes, forming an insulator layer over the Mott transition channel layer, forming source and drain contacts through the insulator layer (such that the source and drain contacts are electrically connected to the Mott transition channel layer) and forming a gate electrode over the insulator layer between the source and drain contacts.

Abstract: There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2eV, respectively.

Abstract: To provide a semiconductor device having a new structure capable of simultaneously realizing high operational function and high reliability, in an activation region 102 sandwiched by a source region 101 and a drain region 103 constituted by a crystalline semiconductor, SixGe1−x regions 105 are formed by locally adding germanium and a depletion layer widening from the drain side toward the source side is effectively restrained by utilizing a difference in band structures of the SixGe1−x regions 105 and Si regions 106 where germanium is not added.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5 and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.

Abstract: In a crystallization process of an amorphous semiconductor film, a first crystalline semiconductor film having crystalline regions, and dotted with amorphous regions within the crystalline regions, is obtained by performing heat treatment processing after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. The amorphous regions are kept within a predetermined range by regulating the heat treatment conditions at this point. Laser annealing is performed on the first crystalline semiconductor film, to form a second crystalline semiconductor film. Electrical characteristics for a TFT manufactured based on the second crystalline semiconductor film can be obtained having less dispersion.

Abstract: A method of manufacturing a thin film transistor. A gate electrode is formed on a substrate. Then a first gate insulation layer is formed on the gate electrode and on the substrate. The first gate insulation layer is then cleaned to remove contaminates. After cleaning, a second gate insulation layer is then formed on the first gate insulation layer. Beneficially, the first and second gate insulation layers are of the same material. An active layer having an ohmic contact layer is then formed on the second insulation layer. Spaced apart source and drain electrodes are then formed on the ohmic contact.

Abstract: A method and structure of forming an integrated circuit chip having a transistor includes forming a conductive oxide layer, forming a Mott transition oxide layer over the conductive oxide layer and forming an insulative oxide layer over the Mott transition oxide layer.

Abstract: The SiC semiconductor structure contains at least three semiconductor regions. The surface area of the third semiconductor region encompasses that of the second semiconductor region as a second partial area, which in turn encloses the surface of the first semiconductor region as a first partial area. The contour of the edge of the second partial area is determined by the contour of the edge of the first partial area to the effect that the second partial area can be represented essentially as a specially enlarged mapping of the first partial area, the deviation of the contour of the edge of the second partial area from the exact contour that results in the course of the mapping being at most ±10 nm.

Abstract: An insulator layer for single crystal gallium arsenide substrates in which the insulator layer is compliantly matched with the substrate and the insulator layer is free of defects causing surface roughness and crystalline defect problems which, otherwise, could impair device performance. To accomplish this, the insulator layer is formed on a gallium arsenide substrate as an integral composite or variegated structure including (a) a uniform homogenous film of Group IIa metal atoms attached directly onto a gallium arsenide substrate surface in the form of a monolayer, and (b) a single crystal epitaxial film of a Group IIa metal fluoride deposited on the monolayer.

Abstract: An FET structure in accordance with the invention employs an organic-inorganic hybrid material as the semiconducting channel between source and drain electrodes of the device. The organic-inorganic material combines the advantages of an inorganic, crystalline solid with those of an organic material. The inorganic component forms an extended, inorganic one-, two-, or three-dimensional network to provide the high carrier mobilities characteristic of inorganic, crystalline solids. The organic component facilitates the self-assembly of these materials and enables the materials to be deposited by simple, low temperature processing conditions such as spin-coating, dip-coating, or thermal evaporation. The organic component is also used to tailor the electronic properties of the inorganic framework by defining the dimensionality of the inorganic component and the electronic coupling between inorganic units.

Abstract: A device includes first and second contacts formed on a channel material, a film of doped first insulator material interposed between the first and second contacts, and a second insulator material interfaced with the doped first insulator material with an area of said channel material therebetween. The second insulator material is doped so as to have carriers of opposite charge to those in the channel material.

Abstract: An electro-conductive ultraviolet light transmitting Ga.sub.2 O.sub.3 material (10) with a metallic oxide phase is deposited on a GaAs substrate or supporting structure (12). The Ga.sub.2 O.sub.3 material or thin layer comprises a minor component of metallic IrO.sub.2. The Ga.sub.2 O.sub.3 thin layer may be positioned using thermal evaporation (106) of Ga.sub.2 O.sub.3 or of a Ga.sub.2 O.sub.3 containing a compound from an Iridium crucible (108). Alternatively, the Ir may be co-evaporated (110) by electron beam evaporation. The electro-conductive ultraviolet light transmitting material Ga.sub.2 O.sub.3 with a metallic oxide phase is suitable for use on solar cells and in laser lithography.

Abstract: An improved FET for use as a voltage-controlled resistor includes a p-type control gate and a high-resistance connection to receive a control signal. The bootstrap frequency for the device is much lower than the signal frequency so that the signal frequency is decoupled from the control voltage to reduce distortion.

Abstract: A semiconductor device comprises at least one semiconductor layer of SiC and a layer of a refractory metal nitride separated by an insulating layer located next to the SiC layer of SiO.sub.2. The insulating layer comprises two sub layers, namely a first sub layer of SiO.sub.2 next to the SiC layer and a second sub layer of Si.sub.3 N.sub.4 located between the first sub layer and the metal nitride layer.

Abstract: A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n.sup.+ type silicon carbide semiconductor substrate 1, an n.sup.- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n.sup.+ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n.sup.+ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n.sup.- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n.sup.+ type source region 6, the p type silicon carbide semiconductor layer 3, and the n.sup.- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

Abstract: Disclosed are articles that comprise an oxide layer on a GaAs-based semiconductor body, with metal layers on the oxide and the body facilitating application of an electric field across the oxide layer. The interface between the oxide and the semiconductor body is of device quality. Contrary to teachings of the prior art, the oxide is not essentially pure Ga.sub.2 O.sub.3, but instead has composition Ga.sub.x A.sub.y O.sub.z, where A is an electropositive stabilizer element adapted for stabilizing Ga in the 3+ oxidation state. Furthermore, x.gtoreq.0, z is selected to satisfy the requirement that both Ga and A is substantially fully oxidized and y/(x+y) is greater than 0.1. Stabilizer element A typically is selected from Sc, Y, the rare earth elements and the alkaline earth elements. Articles according to the invention exemplarily comprise a planar enchancement mode MOS-FET with inversion channel. A method of making articles as described above is also disclosed.

Abstract: An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.

Abstract: A semiconductor device (20) is formed on a compound semiconductor substrate (21). The semiconductor device (20) is oriented on the surface (40) of the compound semiconductor substrate (21) such that the physical forces that result from the thermal heating or cooling of the compound semiconductor substrate (21) are essentially equal. This orientation reduces the variability of the drain to source current of the semiconductor device (20) as the semiconductor device (20) is operated at different temperatures.

Abstract: A semiconductor device is fabricated by the step of forming a gate insulation film of a GaS film on a compound semiconductor layer; the step of forming an inter-layer insulation film on the gate insulation film; the step of etching the inter-layer insulation film selectively with respect to the gate insulation film by the use of an etchant containing hydrogen fluoride and ammonium fluoride, the step of exposing a prescribed region of the gate insulation film; and the step of forming a gate electrode on the exposed gate insulation film.

Abstract: An undoped GaAs layer and a GaAs active layer are formed on a GaAs semiconductor substrate in that order, and a surface of the GaAs active layer is inactivated. Thereafter, a wafer composed of the GaAs semiconductor substrate, the undoped GaAs layer and the GaAs active layer is annealed at temperatures ranging from 570 to 580.degree. C. in a molecular beam epitaxy apparatus. Thereafter, the wafer is maintained at temperatures ranging from 350 to 500.degree. C., and an insulating layer made of amorphous GaAs is formed on the GaAs active layer while using tertiary-butyl-gallium-sulfide-cubane "((t-Bu)GaS).sub.4 " as a source of the insulating layer. Thereafter, the insulating layer is patterned according to a photo-lithography method to form a gate insulating layer on the GaAs active layer.

Abstract: A method of manufacturing an organic electronic device having a substrate and a pair of electrodes facing each other, including the steps of forming a polytetrafluoroethylene oriented film on a substrate, and contacting an oligothiophene compound with the polytetrafluoroethylene oriented film to form an organic oriented film on the polytetrafluoroethylene oriented film between the pair of electrodes wherein the long axis of oligothiophene molecules is oriented to the orientation of the polytetrafluoroethylene oriented film and crystallized.

Abstract: It has been found that a Ga-oxide-containing layer is substantially not etched in HF solution if the layer is a Ga-Gd-oxide with Gd:Ga atomic ratio of more than about 1:7.5, preferably more than 1:4 or even 1:2. This facilitates removal of a protective dielectric (typically SiO.sub.2) layer after an ohmic contact anneal, with the Ga-Gd-oxide gate oxide layer serving as etch stop and not being adversely affected by contact with the HF etchant. Gd-Ge-oxide also exhibits a composition-dependent etch rate in HCl:H.sub.2 O.

Abstract: The present invention discloses a method of forming an oxide layer on a layer of germanium including the steps of depositing a layer of aluminum arsenide on the layer of germanium, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide by the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a Ge field effect transistor by forming an oxide layer on Ge and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the germanium field effect transistor.

Abstract: The present invention is a diamond electrode with high efficiency, a small overvoltage, and a long lifetime, which is reusable, and which can measure the temperature of the electrode. The diamond electrode is at least partially composed of a semiconducting diamond film, whose surface is chemically modified. Another embodiment of the present invention carbon is used as a bare electrode material, diamond crystals are fixed to the bare electrode material, the surface of the undoped diamond crystals are covered with semiconducting diamond film, or semiconducting diamond crystals are fixed to said bare electrode material, and the surfaces of diamond films or crystals are chemically modified. Furthermore, wires may be connected to the diamond electrode to measure the electrical resistance, and hence the temperature.

Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and the minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent material (substrate) is the GaAs single crystal can be made uniform.