Abstract: A semiconductor device includes a capacitor which has: a lower electrode formed along an opening provided above a semiconductor substrate to have a concave cross section; a capacitor insulating film formed on the inner and top surfaces of the lower electrode; and an upper electrode formed on the capacitor insulating film. The upper electrode includes: a first conductive film formed on the inner surface of the capacitor insulating film and filling the opening; and a second conductive film formed to extend from the top surface of the first conductive film to the top surface of the capacitor insulating film.

Abstract: In a fin-type field effect transistor (FinFET) structure, a gate strap is positioned on the top of a gate conductor and runs along the gate conductor. The top of the gate strap is positioned a greater height above the top surface of the substrate than the top of the fin cap. The gate strap is conformal and, therefore, the top of the portion of the gate strap that crosses the fin cap has a greater height above the top surface of the substrate than top portions of other regions of the gate strap. Further, the material of the gate strap can have a different work function than a material of the gate conductor.

Abstract: A photoelectric conversion device comprises: a clipping unit including a MOS transistor which has a source connected to a signal line and a drain being connected to a power supply, and the clipping unit clipping an electric potential of the signal line to an electric potential corresponding to an electric potential of the source; a holding capacitance which has a first electrode and a second electrode, the first electrode being connected to a gate of the MOS transistor, and the holding capacitance holding at least a voltage transferred to the signal line while the charge-voltage converter has been reset; and a shift unit which shifts an electric potential of the second electrode in a direction such that the electric potential of the second electrode comes close to a level to be transferred to the signal line while the charge-voltage converter has been reset.

Abstract: Methods include making a FinFET device structure having multiple FinFET devices (e.g. ntype and/or ptype) with different metal conductors and/or different high-k insulators in the gates formed on a SOI substrate. One such method includes removing a second semiconductor layer from a second metal layer in a region above a second cap layer, from adjoining regions and from regions adjacent to a second fin.

Abstract: A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine the electric fields between the limits of the shields.

Abstract: Dynamic random access memory (DRAM) devices include first node pads and second node pads alternately arranged in a first direction on a substrate to form a first pad column. A width of the second node pads in a second direction, perpendicular to the first direction, is greater than a width of the first node pads in the second direction. Storage electrodes are electrically connected to the first node pads and the second node pads. Bit line pads may be arranged in the first direction on the substrate to form a second pad column. The second pad column is adjacent the first pad column and displaced therefrom in the second direction.

Abstract: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.

Abstract: A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

Abstract: A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.

Abstract: Disclosed are a vertical-type capacitor and a formation method thereof. The capacitor includes a first electrode wall and a second electrode wall perpendicular to a semiconductor substrate, and at least one dielectric layer on the substrate to insulate the first electrode wall from the second electrode wall. The first electrode wall includes a plurality of first conductive layers and a plurality of first contacts, the plurality of first conductive layers being interconnected with each other by each of the plurality of first contacts. The second electrode wall includes a plurality of second conductive layers and a plurality of second contacts, the plurality of second conductive layers being interconnected with each other by each of the plurality of second contacts.

Abstract: An external electrode structure for a monolithic ceramic capacitor provided with a function as a resistance element is capable of preventing a reduction of the external electrode due to baking in a reducing atmosphere, so that Ni or a Ni alloy can be used in an internal electrode and a good electrical connection between the internal electrode and the external electrode is achieved. The external electrodes disposed on an outer surface of a capacitor main body include an electrically conductive layer and a metal plating layer disposed thereon, and the electrically conductive layer includes a compound oxide, e.g., an In—Sn compound oxide, which reacts with Ni or the Ni alloy, and a glass component.

Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.

Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: An integrated circuit arrangement includes an undulating capacitor in a conductive structure layer. The surface area of the capacitor is enlarged in comparison with an even capacitor. The capacitor is interlinked with dielectric regions at its top side and/or its underside, so that it can be produced by methods which may not have to be altered in comparison with conventional CMP methods.

Abstract: A metal-insulator-metal capacitor includes a first electrode in a first wiring level, a second electrode above the first wiring level and extending into a first portion of the first electrode that surrounds the second electrode, and a dielectric film separating the first electrode from the second electrode.

Abstract: The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.

Abstract: A capacitor may include a first electrode, a second electrode, a low dielectric layer, and/or a high dielectric layer. The first electrode may include at least one first electrode branch. The second electrode may face the first electrode and include at least one second electrode branch. The low dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may be formed between the first electrode branch and the second electrode branch. The high dielectric layer may have a higher dielectric constant than the low dielectric layer.

Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.

Abstract: A method of fabricating an integrated circuit capacitor includes forming a first metal layer on a conductive plug in an interlayer insulating layer on a substrate. At least a portion of the first metal layer is silicided to form a metal silicide layer and a remaining first metal layer on the conductive plug. The remaining first metal layer is removed using a dry etching process. A lower electrode including a second metal layer is then formed on the metal silicide layer. Because the remaining first metal layer is removed, etching and/or other damage to the conductive plug and/or the interlayer insulating layer during a subsequent wet ethching process may be reduced and/or prevented.

Abstract: A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Abstract: A first electrode layer having protrusions and depressions on its surface are formed on a lower insulating layer on a semiconductor substrate, and a sacrificial layer is formed on the first electrode layer with a material that is reflowable when heated. After reflowing the sacrificial layer by heat treatment, the reflowed sacrificial layer and first electrode layer are etched so that the protrusions of the first electrode layer are curved, and a dielectric layer and a second electrode layer are sequentially formed on the first electrode layer. When manufactured using the above method, a thin film capacitor may have higher capacitance without increasing the area of the electrode.

Abstract: A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum area. The capacitor structure provided can also be applied to a high-frequency high-speed module or system to enhance noise inhibition capability of a capacitive substrate.

Abstract: System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Abstract: In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).

Abstract: A semiconductor memory device includes a memory cell and a dummy cell. The amount of leakage current per unit area in a capacitor in the dummy cell is larger than that in a capacitor in the memory cell.

Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

Abstract: An interdigitized capacitor comprising first and second electrodes. The first electrode comprises two combs symmetrical to a first mirror plane. The fingers of the combs extend toward the first mirror plane. The second electrode comprises two combs and a linear plate. The combs are symmetrical to a second mirror plane and the fingers thereof extend toward the second mirror plane. The linear plate is located at the second mirror plane and connected to one finger of the combs of the second electrode. The first and second mirror planes are orthogonal. The fingers of the combs of the first and second electrodes are interdigitized.

Abstract: A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through the lower interlayer dielectric layer to also be in contact with the semiconductor substrate. A metal silicide layer is disposed on the second landing pad. The metal silicide layer is disposed lower than a top surface of the first landing pad. An intermediate interlayer dielectric layer is disposed on the lower interlayer dielectric layer. A conductive line is disposed on the intermediate interlayer dielectric layer. A contact plug is disposed between the conductive line and the metal silicide layer. A designed contact area between the metal silicide layer and the contact plug is protected against inadvertent etching.

Abstract: A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: Capacitors are disclosed having reduced parasitic capacitance. In one embodiment, the capacitor includes a first set of electrodes, each electrode of the first set extending through at least one of a plurality of back-end-of-line (BEOL) layers above a substrate; a second set of electrodes, each electrode of the second set extending through at least one of the BEOL layers, and wherein each electrode of the second set extends to a greater depth of the plurality of BEOL layers than each electrode of the first set.

Abstract: A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure comprising a via for coupling the drain runner with the drain region, and a second coupling structure comprising a via for coupling the source runner with the source region.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: A capacitor for a dynamic semiconductor memory cell, a memory and method of making a memory is disclosed. In one embodiment, a storage electrode of the capacitor has a pad-shaped lower section and a cup-shaped upper section, which is placed on top of the lower section. A lower section of a backside electrode encloses the pad-shaped section of the storage electrode. An upper section of the backside electrode is enclosed by the cup-shaped upper section of the storage electrode. A first capacitor dielectric separates the lower sections of the backside and the storage electrodes. A second capacitor dielectric separates the upper sections of the backside and the storage electrodes. The electrode area of the capacitor is enlarged while the requirements for the deposition of the capacitor dielectric are relaxed. Aspect ratios for deposition and etching processes are reduced.

Abstract: A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Abstract: Provided is a capacitor of a semiconductor device and a method of fabricating the same. In one embodiment, the capacitor includes a lower electrode formed on a semiconductor substrate; a dielectric layer formed on the lower electrode; and an upper electrode that is formed on the dielectric layer. The upper electrode includes a first conductive layer, a second conductive layer, and a third conductive layer stacked sequentially. The first conductive layer comprises a metal layer, a conductive metal oxide layer, a conductive metal nitride layer, or a conductive metal oxynitride layer. The second conductive layer comprises a doped polysilicon germanium layer. The third conductive layer comprises a material having a lower resistance than that of the second conductive layer.

Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).

Abstract: The memory cell is arranged in a ridge of semiconductor material forming a fin with sidewalls and a channel region between source and drain regions. Memory layer sequences provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes. This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.