Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

Abstract: An array of programmable non-volatile devices are is adapted such that their logic state is controllably altered over time by quiescent changes, slow controlled changes, scheduled changes, or some combination thereof imposed at a physical level. This allows for improved security and privacy for data to be permanently deleted. In some applications a data refresh and/or automatic backup can be implemented as well.

Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure. The first terminal comprises a tunneling layer formed on the substrate, a first conductive structure formed on the tunneling layer, and a dielectric structure formed on a top surface and on a first curved side surface of the first conductive structure. The semiconductor structure includes a second terminal coupled to the substrate. The second terminal comprises a second conductive structure formed on an isolation structure. The second conductive structure has a second curved side surface, and the dielectric structure is disposed between the first curved side surface and the second curved side surface.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and distal regions proximate the control gate regions. The control gate regions have front surfaces, top surfaces and bottom surfaces. The top and bottoms surfaces extend back from the front surfaces. High-k dielectric material is along the control gate regions. The high-k dielectric material has first regions along the top and bottom surfaces, and has second regions along the front surfaces. The first regions are thicker than the second regions. Charge-blocking material is adjacent to the second regions of the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. Gate-dielectric material is adjacent to the charge-storage material. Channel material is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies.

Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Abstract: A semiconductor device constituting a non-volatile memory includes a semiconductor portion of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, an insulating film, and a conductive layer. The first well includes a trench extending from the surface of the semiconductor portion to an inside of the first well. The insulating film extends on a surface inside the trench. A conductive portion formed continuous with the conductive layer is disposed on the insulating film inside the trench.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.

Abstract: A resistive memory device including a first electrode and a second electrode facing each other and a variable resistance layer disposed between the first electrode and the second electrode, wherein the variable resistance layer includes cadmium-free quantum dots (Cd-free quantum dots) and at least a portion of the Cd-free quantum dots include a Cd-free quantum dot including a halide anion on a surface of the Cd-free quantum dot, a method of manufacturing the same and an electronic device.

Abstract: Embodiments of memory devices and fabrication methods thereof are disclosed. In an example, a memory device includes a substrate, a memory stack, and a channel structure. The memory stack includes interleaved conductor layers and dielectric layers over the substrate. The channel structure extends through the memory stack into the substrate and includes a functional layer that includes a tunneling layer of which a nitrogen weight percent is not greater than about 28%.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric layer; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric layer, and the second gate dielectric layer extends over the first gate.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate having a diffusion region including an impurity; and a contact provided on the diffusion region. The contact includes a metal film, a barrier metal film covering the metal film, and a conductive film provided between the barrier metal film and the diffusion region and including a conductive material having a higher heat of formation than a heat of formation of the barrier metal film.

Abstract: A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all of the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.

Abstract: Methods of fabricating semiconductor devices comprise forming first active patterns vertically spaced apart on a first active fin of a substrate and second active patterns vertically spaced apart on a second active fin of the substrate that has a first region on which the first active fin is formed and a second region on which the second active fin is formed, forming a first electrode layer on the first and second active fins and the first and second active patterns, forming a first mask pattern overlapping the first electrode layer on the first region, forming a second mask pattern overlapping the first electrode layer on the second region, and using the second mask pattern as an etching mask to etch the first mask pattern and the first electrode layer on the first region to form a first electrode pattern on the second region.

Abstract: A three dimensional memory includes flat electrodes, each defining a plane; a vertical electrode, extending essentially along an axis perpendicular to the plane defined by each flat electrode; floating electrodes, each situated between a flat electrode and the vertical electrode; first layers of an insulating material, each flat electrode being separated from the preceding and/or following flat electrode by a first layer of an insulating material; first layers of a first active material, each layer of an active material separating a flat electrode from the floating electrode that is associated therewith; a second layer of a second active material separating the vertical electrode from the floating electrodes. The first active material forms a selector or a memory point and the second active material forms a memory point or a selector. Each flat electrode includes first, second and third sub-layers made of, respectively, first, second and third conductive materials.

Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: Provided is an RF switch device (100) in which body contact regions (190) are formed at respective positions adjacent to or partially overlapping opposite ends of a gate region (110) so that holes in a body of the device can escape or flow in either or both of two directions, rather than in only a single direction.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a first well region and a second well region in the semiconductor substrate; and forming a first gate structure on a surface of the second well region and a portion of a surface of the first well region and a second gate structure on a portion of the first well region. A first opening is formed between the first gate structure and the second gate structure. The method also include forming a sidewall spacer layer covering sidewall and bottom surfaces of the first opening in the first opening; forming a dielectric layer on the semiconductor substrate to cover the first gate structure, the second gate structure and the sidewall spacer layer; and forming a floating plug in the dielectric layer and on the sidewall spacer layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes providing a substrate including a channel region for conducting current; shaping the substrate to form a protruding plane, a bottom plane and a side plane connected between the protruding plane and the bottom plane for the channel region; forming an oxide layer covering the channel region; forming a ferroelectric material strip, extending in a first direction, on a protruding plane of the oxide layer; and forming a gate strip, extending in a second direction orthogonal with the first direction, on the ferroelectric material strip and a side plane and a bottom plane of the oxide layer.

Abstract: A semiconductor storage device includes a stacked body including conductive layers stacked in a first direction; columnar bodies of a first group extending in the first direction in the stacked body, wherein memory cell transistors are respectively formed at intersections of the conductive layers and the columnar bodies of the first group; columnar bodies of a second group that are arranged in a second direction, and respectively include an insulating material; and an insulating film extending in the first direction and the second direction in the stacked body, and divides the stacked body to include a first portion adjacent to the columnar bodies of the first group, a second portion adjacent to the columnar bodies of the second group, a third portion between the first portion and the second portion, and a first protruding part protruding from one side surface in the third direction in the third portion.

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line. The memory component can also include a vertically oriented conductive channel extending through the plurality of conductive layers. In addition, the flash memory component can include a plurality of memory cells coupling the plurality of conductive layers to the conductive channel. Each word line can be associated with one of the plurality of memory cells. Associated devices, systems, and methods are also disclosed.

Abstract: A semiconductor layout structure includes a substrate, a plurality of gate structures, and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, in which the active regions are separated from each other by an isolation structure. The transistors are respectively disposed in the active regions. The gate structures extend across the active regions along a second direction that is perpendicular to the first direction, in which each of the active regions includes a pair of source/drain portions at opposite sides of each of the gate structures. The conductive structures are embedded in a first portion of the isolation structure disposed between the adjacent active regions in the first direction, wherein the conductive structures extend along the second direction and are separated from the source/drain portions by the isolation structure.

Abstract: The present invention provides a 1.5T SONOS memory structure and a manufacturing method, comprises a P-well and a storage well on its side, gates of a select transistor and a storage transistor; the height of the select transistor gate is less than the height of the storage transistor gate, an stack layer is between the gats of the select transistor and the storage transistor which height is same as the storage transistor gate; the top of the select transistor gate has a first sidewall; the sidewall of the select transistor gate has a second sidewall. The present invention strengthens the isolation between the gates of the select transistor and the storage transistor, reduces the risk of current leakage, enables the metal silicide to also grow on the gate of the select transistor, reduces the resistance of the select transistor and improves the performance of the device.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: An embodiment includes a system comprising: a switching device that includes a fin; and a source contact on a source, a gate contact on a channel, and a drain contact on a drain; wherein the gate contact includes: (a)(i) a first layer that includes oxygen, the first layer directly contacting the fin, (a)(ii) a second layer that includes a dielectric material, (c) a third layer that includes at least one of aluminum, titanium, ruthenium, zirconium, hafnium, tantalum, niobium, vanadium, thorium, barium, magnesium, cerium, and lanthanum, and (a)(iii) a fourth layer that includes a metal, wherein (b)(i) the source contact, the gate contact, and the drain contact are all on the fin, and (b)(ii) the second layer is between the first and fourth layers. Other embodiments are described herein.

Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.

Abstract: A memory device includes a semiconductor fin, a floating gate, a control gate, a source region, an erase gate, and a select gate. The floating gate is above and conformal to the semiconductor fin. The control gate is above the floating gate. The source region is in the semiconductor fin. The erase gate is above the source region and adjacent the control gate. The select gate is above the semiconductor fin. The control gate is between the erase gate and the select gate.

Abstract: Embodiments of the disclosure provide memory devices and methods related to memory accessing.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.

Abstract: A nonvolatile memory device according to an embodiment of the present disclosure includes a substrate having a channel layer, a first tunneling layer disposed on the channel layer, a second tunneling layer disposed on the first tunneling layer, a third tunneling layer disposed on the second tunneling layer, a charge trap layer disposed on the third tunneling layer, a charge barrier layer disposed on the charge trap layer, and a gate electrode layer disposed on the charge barrier layer. The first tunneling layer includes a first insulative material. The second tunneling layer includes a second insulative material. The third tunneling layer includes a second insulative material. The resistance switching material is a material whose electric resistance varies reversibly between a high resistance state and a low resistance state depending on a magnitude of an applied electric field.

Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

Abstract: The present invention provides architectures of high-density NOR flash memory consisting of arrays of memory cells (i.e., field effect transistors) with uniquely designed sidewall charge-storage structures to solve the leakage problem typically associated with overerase in traditional NOR flash memory. This feature is particularly useful for applications such as embedded flash memory.

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Abstract: The present disclosure provides embodiments of a semiconductor structure having bi-layer self-aligned contact. The semiconductor structure includes a gate stack disposed on a semiconductor substrate and having a first height, a spacer disposed on a sidewall of the gate stack and having a second height greater than the first height, and a first etch stop layer disposed on a sidewall of the gate spacer and having a third height greater than the second height. The semiconductor structure further includes a first dielectric layer disposed over the gate stack and contacting the gate spacer and the first etch stop layer and a second dielectric layer disposed on the first dielectric layer and contacting the first etch stop layer.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: A method of forming an apparatus comprises forming filled trenches within a semiconductive structure having a well region comprising one or more dopants, the filled trenches extending into the well region and each individually comprising a conductive gate structure and a dielectric liner intervening between the conductive gate structure and the semiconductive structure. A fluorine-doped region is formed at junctions between the well region and additional regions of the semiconductive structure overlying the well region. The additional regions of the semiconductive structure are doped with one or more additional dopants having a different conductivity type than that of the one or more dopants of the well region after forming the fluorine-doped region. The semiconductive structure is annealed after doping the additional regions thereof. Apparatuses, memory devices, and electronic systems also described.

Abstract: Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.

Abstract: An integrated circuit includes two different types of embedded memories, with cells that have different retention characteristics, and situated in different areas of the substrate. In some applications the cells are both non-volatile memories sharing a common gate layer but with different oxide layers, different thicknesses, etc. The first type of cell is a conventional flash cell which can be part of a logic/memory region, while the second type of cell uses capacitive coupling and can be located in a high voltage region. Because of their common features, the need for additional masks, manufacturing steps, etc. can be mitigated.

Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor device includes a composite gate structure formed over a semiconductor substrate. The composite gate structure includes a gate dielectric layer, a metal layer, and a semiconductor layer. The metal layer is disposed on the gate dielectric layer. The semiconductor layer is disposed on the gate dielectric layer. The metal layer surrounds the semiconductor layer.

Abstract: A semiconductor device includes a first substrate including a cell region and surrounded by an extension region, a common source plate on the first substrate, a supporter on the common source plate, a first stack structure on the supporter and including an alternately stacked first insulating film and first gate electrode, a channel hole penetrating the first stack structure, the supporter, and the common source plate on the cell region, and an electrode isolation trench spaced apart from the channel hole in a first direction on the cell region, extending in a second direction, and penetrating the first stack structure, the supporter, and the common source plate, wherein a first thickness of the supporter in a first region adjacent to the electrode isolation trench is greater than a second thickness of the supporter in a second region formed between the electrode isolation trench and the channel hole.

Abstract: A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array; a first insulating layer; and a passivation film. The memory cell array includes first interconnect layers and a first memory pillar. The first interconnect layers extend in a first direction substantially parallel to a semiconductor substrate. The first memory pillar passes through the first interconnect layers and extends in a second direction substantially perpendicular to the semiconductor substrate. The first insulating layer is provided above the memory cell array. The passivation film is provided on the first insulating layer, and includes a protrusion at least above the memory cell array and between the passivation film and the first insulating layer.