Abstract: A semiconductor device includes a memory cell formed on a semiconductor substrate. The memory cell includes a first source region and a first drain region that are formed in the semiconductor substrate and a first selection gate, and a first floating gate disposed in series between the first source region and the first drain region. A first floating gate transistor including the first drain region and the first floating gate has a threshold set lower than a threshold of a first selection gate transistor including the first source region and the first selection gate.

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.

Abstract: An integrated circuit includes a substrate having a first region and a second region, a first isolation structure disposed in the substrate and separating the first region from the second region, a first device disposed in the first region, a second device disposed in the second region, and a semiconductor dummy structure disposed on the first isolation structure. The first isolation structure has first top surface and a second top surface lower than the first top surface. The semiconductor dummy structure covers a portion of the first top surface, a portion of the second top surface and a boundary between the first top surface and the second top surface.

Abstract: According to one embodiment, a semiconductor device includes a transistor having a diffusion layer extending along a surface of a substrate and a gate electrode arranged above the diffusion layer; and contacts having elongated bottom surfaces connected to the diffusion layer on both sides of the gate electrode, in which the contacts are arranged so that the bottom surfaces of the contacts are not aligned in a straight line with an extension direction of the diffusion layer.

Abstract: A three-dimensional (3D) memory device is provided. The 3D memory device includes a substrate, an alternating conductive/dielectric stack, an epitaxial layer, and a vertical structure. The alternating conductive/dielectric stack is disposed on the substrate. The alternating conductive/dielectric stack includes a plurality of dielectric layers and a plurality of conductive layers alternately stacked in a vertical direction perpendicular to a surface of the substrate. The epitaxial layer is disposed between the substrate and the alternating conductive/dielectric stack in the vertical direction. The vertical structure penetrates the alternating conductive/dielectric stack in the vertical direction for being partly disposed in the epitaxial layer. The epitaxial layer includes a protruding part disposed between the vertical structure and a bottom dielectric layer of the alternating conductive/dielectric stack in a horizontal direction orthogonal to the vertical direction.

Abstract: Disclosed herein are techniques for directional spacer removal, as well as related integrated circuit (IC) structures and devices. For example, in some embodiments, an IC structure may include: a first semiconductor fin having a first fin end cap; a second semiconductor fin having a second fin end cap, wherein the second fin end cap faces the first fin end cap; a first gate over the first semiconductor fin, wherein the first gate has a first gate end cap; a second gate over the second semiconductor fin, wherein the second gate has a second gate end cap facing the first gate end cap; and a gate edge isolation material adjacent to the first fin end cap, the second fin end cap, the first gate end cap, and the second gate end cap.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: An erasable programmable non-volatile memory includes a memory array and a sensing circuit. The memory array includes a general memory cell and a reference memory cell, which are connected with a word line. The sensing circuit includes a current comparator. The read current in the program state of the general memory cell is higher than the read current in the program state of the reference memory cell. The erase efficiency of the general memory cell is higher than the erase efficiency of the reference memory cell. When a read action is performed, the general memory cell generates a read current to the current comparator, and the reference memory cell generates a reference current to the current comparator. According to the reference current and the read current, the current comparator generates an output data signal to indicate a storage state of the general memory cell.

Abstract: An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high ? dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a memory device. A decision to perform a refresh operation is made based on the temperature and number of program-erase (P-E) cycles. In one approach, the refresh operation is not performed if the number of P-E cycles is below a threshold number and/or the temperature is below a threshold temperature. When the temperature and number of P-E cycles indicate that a refresh operation should be performed, a timer counts an elapsed time until the elapsed time reaches an allowed discharge time. The allowed discharge time can be based on the temperature, number of P-E cycles, and other factors which affect an expected number of fail bits. The allowed discharge time can also change as the temperature changes during the counting of the elapsed time.

Abstract: A 3D semiconductor device, the device including: a first level including a single crystal layer, a first metal layer, a second metal layer above the first metal layer, and a third metal layer above the second metal layer, where the second metal layer is significantly thicker than either the third metal layer or the first metal layer, where the third metal layer is precisely aligned to the first metal layer with less than 20 nm misalignment; a second level including a first array of first memory cells, each of the first memory cells include first transistors; a third level including a second array of second memory cells, each of the second memory cells include second transistors, where the second level is above the third level, where the second transistors are self-aligned to the first transistors, being processed following the same lithography step; and periphery circuits connected by the second metal to control the memory cells, where the periphery circuits are either underneath or atop the memory cells.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode having a two-sided staircase shape above the substrate, a blocking layer on the gate electrode, a plurality of discrete charge trapping layers each extending laterally on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of discrete channel layers each extending laterally on the tunneling layer. The plurality of charge trapping layers are disposed corresponding to stairs of the two-sided staircase shape of the gate electrode, respectively. The plurality of channel layers are disposed corresponding to the stairs of the two-sided staircase shape, respectively.

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

Abstract: The object of the present invention is to provide a nonvolatile storage element capable of suppressing retention degradation. A nonvolatile storage element is provided with a semiconductor substrate and a floating gate provided above the semiconductor substrate, in which the floating gate has an area of 30 ?m2 or more.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.

Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.

Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.

Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.

Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.

Abstract: Techniques for voltage bitline high (VBLH) regulation for a computer memory are described herein. An aspect includes generating, by a resistor ladder and a diode compensation footer, a VBLH reference signal based on a high voltage (VPP) in a computer memory module. Another aspect includes regulating a VBLH signal based on the VBLH reference signal. Another aspect includes regulating a wordline driver voltage of the computer memory module based on the VBLH signal.

Abstract: A semiconductor device according to an embodiment includes first conductors, a second conductor, a first semiconductor, a multi-layered body, and a third conductor. The second conductor is provided above the first conductors. The multi-layered body is provided between the first semiconductor and the first conductors, and between the first semiconductor and the second conductor. The third conductor is provided between the multi-layered body and the second conductor. The first semiconductor includes a first portion facing an uppermost first conductor and a second portion facing the second conductor. The first semiconductor is continuous at least from the first portion to the second portion.

Abstract: A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.

Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.

Abstract: An apparatus includes an interface circuit and a monitor circuit communicatively coupled to the interface circuit. The monitor circuit is configured to identify a command issued to a memory communicatively coupled to the monitor circuit through the interface circuit, determine whether the command is authorized, and, based on a determination that the command is not authorized, cancel the command.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, first and second source/drains, a gate electrode, and a gate contact. The semiconductor fin is disposed on the substrate. The first and second source/drains is disposed on the semiconductor fin. The gate electrode is across the semiconductor fin and exposes the first and second source/drains. The gate contact is disposed on the gate electrode and has an elliptical profile with a major axis extending along a lengthwise direction of the gate electrode when viewed from above the gate contact.

Abstract: A method for manufacturing a semiconductor device includes forming a sacrificial member on a foundation layer, the sacrificial member extending in a first direction along a front surface of the foundation layer; forming a line and space pattern including a plurality of structures on the foundation layer and the sacrificial member, the structures extending along the front surface of the foundation layer in a second direction crossing the first direction; and forming communication passages between the foundation layer and the structures by selectively removing the sacrificial member via spaces between the structures, the spaces being in communication with each other through the communication passages.

Abstract: A semiconductor device including a main board; a first board provided on the main board; first and second semiconductor elements provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; third and fourth semiconductor elements provided on the second board; a second positive terminal provided on the second board; a second negative terminal provided on the second board; a second output terminal provided on the second board; a first terminal plate connecting the first positive terminal and the second positive terminal, a second terminal plate connecting the first negative terminal and the second negative terminal, and a third terminal plate connecting the first output terminal and the second output terminal.

Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.

Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. A vertical structure is formed penetrating the alternating dielectric stack in a vertical direction. A bottom dielectric layer of the alternating dielectric stack is removed. An epitaxial layer is formed between the substrate and the alternating dielectric stack after removing the bottom dielectric layer. An insulating layer is formed on the epitaxial layer. The insulating layer is located between the epitaxial layer and the alternating dielectric stack. The influence of the step of forming the vertical structure on the epitaxial layer may be avoided, and defects at the interface between the epitaxial layer and the bottom dielectric layer may be avoided accordingly.

Abstract: A method for fabricating a semiconductor device including three-dimensional and planar memory device co-integration includes forming trenches within a horizontal electrode stack to expose portions of a conductive layer, forming vertical electrodes including conductive material within the trenches, forming a planar memory device stack across the device, and patterning the planar memory device stack to form a planar memory device.

Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.

Abstract: A flash memory module includes a flash memory and a controller. The controller acquires information indicating reliability of monitoring target data of the flash memory, specifies a first cell, which is a cell having a threshold voltage level lower than a threshold voltage level of a corresponding cell in expected value data obtained by correcting an error bit of the monitoring target data, among cells in which error bits have occurred of the monitoring target data when it is determined that the reliability indicated by the acquired information is lower than a predetermined condition, and transmits rewrite correction target cell data, which is data corresponding to data of the first cell in the expected value data, to the flash memory. The flash memory injects an electron into the first cell based on a threshold voltage indicated by the rewrite correction target cell data.

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a device isolation film on the substrate. An active region of the substrate is defined by the device isolation film on the substrate and has a first width in a horizontal direction. A gate electrode is on the active region and has a second width equal to or less than the first width of the active region in the horizontal direction. The integrated circuit device includes an insulating spacer over the device isolation film and the active region.

Abstract: Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Abstract: A three-dimensional (3D) memory structure and a manufacturing method thereof are provided. The method includes the following steps. A 3D memory unit is formed on a first region of a substrate. A first insulation layer is formed on the first region and a second region of the substrate. A first planarization process is performed to the first insulation layer. The top surface of the first insulation layer on the first region and the top surface of the first insulation layer on the second region are coplanar after the first planarization process. A peripheral circuit is formed on the second region after the first planarization process. The influence of the process for forming the 3D memory unit on the peripheral circuit may be avoided. The manufacturing yield, the electrical performance, and the reliability of the 3D memory structure may be enhanced accordingly.

Abstract: In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a plurality of electrode films arranged along a first direction with an air gap interposed, the first direction crossing a surface of the substrate, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and each of the electrode films, and a high dielectric constant film provided along an outer surface of the air gap, a relative dielectric constant of the high dielectric constant film being higher than a relative dielectric constant of silicon oxide.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

Abstract: A first alternating stack of first insulating layers and first sacrificial material layers is formed with a first stepped surfaces located in a staircase region. A second alternating stack of second insulating layers and second sacrificial material layers with second stepped surfaces is formed over the first alternating stack. Areas of the second stepped surfaces overlap areas of the first stepped surfaces to reduce the size of the staircase region. The sacrificial material layers are subsequently replaced with electrically conductive layers. Laterally-insulated staircase region via structures contacting a respective one of the electrically conductive layers may be provided by forming stepped via cavities such that an annular surface of a respective sacrificial material layer is physically exposed at an annular step of the stepped via cavities. Laterally-insulated staircase region via structures may be formed in the stepped via cavities tot provide electrical connections to the electrically conductive layers.

Abstract: The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.

Abstract: A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.