Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process.

Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

Abstract: An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.

Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.

Abstract: An end of a stacked-structure of conductive and insulating layers above a substrate has a staircase structure. The staircase includes a step pair. The risers of steps are opposed to each other. The step pairs are provided at different levels in the form in the staircase. First contact-plugs are provided on treads of respective steps of the first step part. A second contact-plug is provided in either an intermediate region between the first and the second steps of the step pair or the second step to extend in the stacked structure in a direction in which the conductive and insulating layers are stacked. A CMOS circuit is provided below the stacked structure and is connected to the second contact-plug. The second contact-plug is provided in either the intermediate region on which the first contact-plug is not formed or the second step on which the first contact-plug is not formed.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.

Abstract: A nonvolatile memory device includes a memory cell array, a word line drive block that is connected to a first group of memory cells through a first group of word lines and to a second group of memory cells through a second group of word lines, a bit line bias and sense block that is connected to the first and second groups of memory cells through bit lines, a variable current supply block that generates a word line current to be supplied to a selected word line, and a control logic block that receives an address and a command and controls the variable current supply block to adjust an amount of the word line current based on the address. The control logic block further varies the amount of the word line current depending on a distance between the selected word line and the substrate.

Abstract: A method for fabricating the three dimensional (3D), non-volatile memory (NVM) device includes: forming a stacked structure including a plurality of interlayer insulating layers and a plurality of first material layers which are alternately stacked; forming at least one channel hole penetrating through the stack structure; forming a second material layer along the at least one channel hole; trimming a surface of the second material layer; oxidizing a whole of the trimmed second material layer to form at least a portion of a charge blocking layer; and forming a charge storage layer and a tunnel insulating layer over the charge blocking layer.

Abstract: A vertical memory device includes: a substrate including a memory cell region and a contact region; a plurality of gate electrodes that extend from the memory cell region to the contact region and include pad portions which are end portions stacked in a step shape in the contact region; a plurality of contact plugs coupled to the pad portions of the gate electrodes; and a plurality of supporters formed below the pad portions of the gate electrodes.

Abstract: A semiconductor memory device comprises: stacked bodies adjacent to each other in a second direction, each comprising conductive layers stacked in a first direction; semiconductor portions arranged in a third direction between the stacked bodies, and comprising semiconductor layers facing the conductive layers, and a first insulating layer; and a second insulating layer provided between the semiconductor portions. The smallest distance from a geometrical center of gravity of the second insulating layer to the stacked body on a predetermined first cross-section being represented by D1; a distance from surfaces of the stacked bodies facing the semiconductor portion on a predetermined second cross-section being represented by D2, the relationship 2D1>D2 is satisfied.

Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

Abstract: A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

Abstract: Embodiments of three-dimensional (3D) memory devices having source contact structure in a memory stack are disclosed. The 3D memory device has a memory stack that includes a plurality of interleaved conductor layers and insulating layers extending over a substrate, a plurality of channel structures each extending vertically through the memory stack into the substrate, and a source contact structure extending vertically through the memory stack and extending laterally to separate the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts each electrically coupled to a common source of the plurality of channel structures.

Abstract: A semiconductor memory device includes: a first conductive layer and a first insulating layer extending in a first direction, these layers being arranged in a second direction intersecting the first direction; a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first and second directions; a second semiconductor layer opposed to the first conductive layer, extending in the third direction; a first contact electrode connected to the first semiconductor layer; and a second contact electrode connected to the second semiconductor layer. In a first cross section extending in the first and second directions, an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer, and an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.

Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.

Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.

Abstract: An image sensor includes one or more photodiodes disposed in a semiconductor material to receive image light and generate image charge, and a floating diffusion to receive the image charge from the one or more photodiodes. One or more transfer transistors is coupled to transfer image charge in the one or more photodiodes to the floating diffusion, and a source follower transistor is coupled to amplify the image charge in the floating diffusion. The source follower includes a gate electrode (coupled to the floating diffusion), source and drain electrodes, and an active region disposed in the semiconductor material between the source and drain electrodes. A dielectric material is disposed between the gate electrode and the active region and has a first thickness and a second thickness. The second thickness is greater than the first thickness, and the second thickness is disposed closer to the drain electrode than the first thickness.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.

Abstract: An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Abstract: A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.

Abstract: A semiconductor device includes a gate pattern disposed over a lower structure, and including a gate electrode region and a gate pad region extending from the gate electrode region; and a vertical channel semiconductor layer having a side surface facing the gate electrode region of the gate pattern. The gate pad region includes a first pad region having a thickness greater than a thickness of the gate electrode region. The first pad region includes an upper surface, a lower surface opposing the upper surface, and an outer side surface. The outer side surface has a lower outer side surface and an upper outer side surface, divided from each other by a boundary portion. The lower outer side surface extends from the lower surface, and a connection portion of the lower outer side surface and the lower surface has a rounded shape.

Abstract: A semiconductor memory device includes first conductive layers stacked and second conductive layers stacked in a first direction. The second conductive layers spaced from the first conductive layers in a second direction intersecting the first direction. A first memory pillar is between the first conductive layers and the second conductive layers in the second direction. The first memory pillar extends in the first direction and has a first length in the second direction. A second memory pillar is between the first conductive layers and the second conductive layers in the second direction. The second memory pillar is adjacent to the first memory pillar. The second memory pillar extends in the first direction and has a second length greater than the first length in the second direction.

Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.

Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: A two-terminal memory device and methods for its use are provided. In the device, a bottom electrode is electrically continuous with a first operating terminal, and a control gate electrode is electrically continuous with a second operating terminal. A stack of insulator layers comprising a hopping conduction layer and a tunnel layer is contactingly interposed between the bottom electrode and the control gate electrode. The tunnel layer is thinner than the hopping conduction layer, and it has a wider bandgap than the hopping conduction layer. The hopping conduction layer consists of a material that supports electron hopping transport.

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

Abstract: A vertical memory device includes gate electrodes on a substrate and a channel. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes, and includes a first portion, a second portion and a third portion. The second portion is formed on and connected to the first portion, and has a sidewall slanted with respect to the upper surface of the substrate so as to have a width gradually decreasing from a bottom toward a top thereof. The third portion is formed on and connected to the second portion.

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures located within a respective one of the memory openings. A multi-pillared dielectric isolation structure extends through upper sections of a neighboring pair of memory openings. The multi-pillared dielectric isolation structure includes a plurality of dielectric pillar portions located within a respective one of the memory openings, and at least one horizontally-extending portion adjoining each of the plurality of dielectric pillar portions and located between a vertically neighboring pair of insulating layers within the alternating stack. The at least one horizontally-extending portion laterally separates laterally neighboring strips of at least one electrically conductive layer within the alternating stack.

Abstract: In a method for producing a capacitor, a dielectric structure is generated in a trench of a semiconductor substrate. The dielectric structure includes a plurality of adjacent dielectric layers having opposing material tensions.

Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: In one embodiment, a semiconductor device includes electrode layers and insulating layers alternately provided on a substrate and stacked in a first direction perpendicular to a surface of the substrate, and semiconductor layers provided in the electrode layers and insulating layers, extending in the first direction, and adjacent to each other in a second direction parallel to the surface of the substrate. The device further includes first and second charge trapping layers provided between the semiconductor layers and electrode layers sandwiching the semiconductor layers in a third direction parallel to the surface of the substrate. The device further includes insulators provided between the semiconductor layers being adjacent to each other in the second direction, and including a first insulator having a first width, and a second insulator having a second width longer than the first width and having nitrogen concentration different from that in the first insulator.

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.

Abstract: A semiconductor memory device includes a substrate defined with a cell array region and a connection region which extends in a first direction from the cell array region; an electrode structure including a bottom electrode structure which includes plurality of bottom electrodes stacked on the substrate to be separated from one another and a top electrode structure which includes plurality of top electrodes stacked on the bottom electrode structure to be separated from one another and has a stepped structure which includes plurality of stepping surfaces, in the connection region; and plurality of recess holes formed to a first depth from stepping surfaces of the stepped structure, and having bottom surfaces which expose the bottom electrode structure, wherein the first depth is substantially same as a height of the top electrode structure, and distances of the bottom surfaces of the recess holes from the substrate are different from one another.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.

Abstract: A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.

Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: A memory device comprises a stack of conductive strips separated by insulating layers on a substrate, and a vertical channel structure disposed in a hole through the stack of conductive strips to the substrate. A vertical channel structure is disposed in a hole through the stack of conductive strips to the substrate. Charge storage structures are disposed at cross points of the conductive strips and the vertical channel structure, the charge storage structures including multiple layers of materials. The insulating layers have sidewalls recessed from the vertical channel structure. A charge storage layer of the multiple layers of materials of the charge storage structures lines sidewalls of the insulating layers. Dielectric material is disposed between the vertical channel structure and the charge storage layer on sidewalls of the insulating layers.

Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.

Abstract: A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.

Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.

Abstract: A semiconductor device includes a semiconductor body and an insulated gate contact on a surface of the semiconductor body over an active channel in the semiconductor device. The insulated gate contact includes a channel mobility enhancement layer on the surface of the semiconductor body, a diffusion barrier layer over the channel mobility enhancement layer, and a dielectric layer over the diffusion barrier layer. By using the channel mobility enhancement layer in the insulated gate contact, the mobility of the semiconductor device is improved. Further, by using the diffusion barrier layer, the integrity of the gate oxide is retained, resulting in a robust semiconductor device with a low on-state resistance.

Abstract: A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.