Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

Abstract: A three-dimensional AND type flash memory and a manufacturing method thereof includes steps below is provided. A stack structure includes a first insulating layer and a first sacrificial layer is formed. A first pillar structure through the stack structure includes a second insulating layer and a second sacrificial layer surrounded by thereof is formed. A second pillar structure through the stack structure includes a channel layer and an insulating pillar surrounded by thereof is formed. The second sacrificial layer is located on both sides of the channel layer. The first sacrificial layer is removed. A lateral opening exposing a portion of the second insulating layer and the channel layer is formed. A gate insulating layer surrounding the exposed second insulating layer and channel layer is formed in the lateral opening. A gate layer is filled in the lateral opening. A conductive layer is used to replace the second sacrificial layer.

Abstract: A semiconductor device includes a capacitor structure. The capacitor structure comprises conductive vias extending through openings in a stack of alternating dielectric materials and first conductive materials, each conductive via comprising a second conductive material extending through the openings and another dielectric material on sidewalls of the openings, first conductive lines in electrical communication with a first group of the conductive vias, and second conductive lines in electrical communication with a second group of the conductive vias. Related semiconductor device, electronic systems, and methods are disclosed.

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces.

Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer.

Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

Abstract: Embodiments are described herein that form silicon germanium nano-wires while reducing or eliminating erosion of nitride layers (e.g., masks and spacers) caused during selective etching of silicon with respect to silicon germanium during formation of silicon germanium nano-wires. oxide layers are used to protect nitride layers during formation of silicon germanium (SiGe) nano-wires. In particular, multilayer spacers including oxide/nitride/oxide layers are formed to protect the nitride layers during selective silicon etch processes that are used to form silicon germanium nano-wires, for example, for field effect transistors (FETs). The multilayer spacers allow for target levels of erosion to be achieved for the nitride layers.

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.

Abstract: A semiconductor memory device according to the embodiments includes a first laminated body, a second laminated body, an intermediate insulation layer, and a columnar body. The intermediate insulation layer is positioned between the first laminated body and the second laminated body. A plurality of conductive layers of the second laminated body include a first conductive layer which is positioned closest to the intermediate insulation layer among the plurality of conductive layers of the second laminated body. The first conductive layer has a main body part having a first end surface facing the columnar body, and a protrusion part which protrudes from the main body part to the first laminated body, and has a second end surface facing the columnar body. The first end surface and the second end surface are continuous with each other.

Abstract: A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. First, an initial channel hole can be formed in a structure. The structure can include a staircase structure. The structure can include a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset can be formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel can then be formed based on the channel hole. Further, a plurality of gate electrodes can be formed based on the plurality of second layers.

Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.

Abstract: A reinforced vertical-NAND structure is provided. The reinforced vertical-NAND structure includes a first set of interleaved oxide and nitride layers formed into first and second vertical structures. The first vertical structure rises from a first section of a substrate and the second vertical structure rises from a second section of the substrate. The reinforced vertical-NAND structure also includes a reinforcing layer and a second set of interleaved oxide and nitride layers formed into third and fourth vertical structures. The reinforcing layer includes sheets, which are distinct and laid across respective tops of the first and second vertical structures, and bridges connecting the sheets. The third vertical structure rises from the sheet corresponding to the first vertical structure and the fourth vertical structure rises from the sheet corresponding to the second vertical structure.

Abstract: Embodiments of a three-dimensional (3D) memory device are disclosed. The 3D memory device has an architecture with an increased number of bit lines. In an example, the 3D memory device includes a substrate, a plurality of memory strings each extending vertically above the substrate in a memory region, and a plurality of bit lines over the plurality of memory strings. At least one of the plurality of bit lines is electrically connected to a single one of the plurality of memory strings.

Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

Abstract: According to one embodiment, first and second conductive layers are stacked in a first direction. The second conductive layers are spaced from the first conductive layers. Insulation regions are provided between the first and second conductive layers. A pillar is arranged between the first and second conductive layers and between the insulation regions. The pillar includes a charge storage film, a first insulation film, and a semiconductor layer, which are provided sequentially from the first conductive layers. A second insulation film is provided between the charge storage film and the first conductive layers. A portion of the charge storage film is provided between one of the insulation regions and the first conductive layers at an end of a portion where the first conductive layers and the pillar face each other.

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include delivering a nitrogen-containing precursor or an oxygen-containing precursor to a substrate contained in a semiconductor processing chamber. The methods may include forming reactive ligands on an exposed surface of the substrate with the nitrogen-containing precursor or the oxygen-containing precursor. The methods may also include forming a high-k dielectric material overlying the substrate.

Abstract: A vertical memory device includes a substrate having a trench structure, gate electrodes on the substrate, the gate electrodes being spaced apart from each other in a first direction substantially vertical to an upper surface of the substrate, a channel including a vertical portion extending through the gate electrodes in the first direction, and a horizontal portion extending in the trench structure in a second direction substantially parallel to the upper surface of the substrate, the horizontal portion being connected the vertical portion, and an epitaxial layer on a first portion of the substrate and connected to the horizontal portion of the channel, the first portion of the substrate being adjacent to ends of the gate electrode in the second direction.

Abstract: An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices include a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.

Abstract: Provided herein may be a method of manufacturing a semiconductor device including the step of replacing sacrificial layers of a stack with line patterns through slits that pass through the stack and have different depths.

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer provided on a lower insulating layer. The horizontal semiconductor layer includes a cell array region and a connection region. An electrode structure is provided including electrodes. The electrodes are stacked on the horizontal semiconductor layer. The electrodes have a staircase structure on the connection region. A plurality of first vertical structures are provided on the cell array region to penetrate the electrode structure. A plurality of second vertical structures are provided on the connection region to penetrate the electrode structure and the horizontal semiconductor layer. Bottom surfaces of the second vertical structures are positioned at a level lower than a bottom surface of the horizontal semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pillar extending in a first direction and a first conductive pattern surrounding the channel pillar. The semiconductor device also has second conductive patterns surrounding the channel pillar above the first conductive pattern, wherein the second conductive patterns are stacked in the first direction and spaced apart from each other. The semiconductor device further has an etch stop pattern disposed above the first conductive pattern and below the second conductive patterns.

Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.

Abstract: A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.

Abstract: A three-dimensional semiconductor device includes an electrode structure on a substrate that includes a first region and a second region, the electrode structure including a ground selection electrode, cell electrodes, and a string selection electrode which are sequentially stacked on the substrate wherein the ground selection electrode, the cell electrodes, and the string selection electrode respectively include a ground selection pad, cell pads, and a string selection pad which define a stepped structure in the second region of the substrate, a plurality of dummy pillars penetrating each of the cell pads and a portion of the electrode structure under each of the cell pads, and a cell contact plug electrically connected to each of the cell pads, wherein each of the dummy pillars penetrates a boundary between adjacent cell pads, and wherein the adjacent cell pads share the dummy pillars.

Abstract: Apparatus and associated methods relate to a logic circuit having a number of unit circuits performing buffering and data storage functionalities in parallel. In an illustrative example, a logic circuit may include N unit circuits for data storage and N?1 unit circuits for buffering. During a conversion cycle, only an ith unit circuit of the N unit circuits and an (i?1)th unit circuit of the N?1 unit circuits may be enabled. Output status of the ith unit circuit of the N unit circuits may be monitored to disable the ith unit circuit, and also enable an (i?1)th unit circuit of the N unit circuits and an (i?2)th unit circuit of the N?1 unit circuits. By performing buffering and data storage in parallel, propagation delays in the SAR logic circuit may advantageously be reduced, and thus, conversion time of a successive-approximation-register (SAR) analog-to-digital converter (ADC) may be advantageously reduced.

Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate, and an alternating stack of insulating layers and spacer material layers and memory stack structures are formed over the in-process source-level layers. A backside trench is formed through the alternating stack, and a source cavity is formed by removing the source-level sacrificial layer employing an etchant provided through the backside trench. A source contact layer including a doped semiconductor material is formed on vertical semiconductor channels of the memory stack structures within the source cavity. The source contact layer includes an unfilled cavity, which is subsequently filled with a silicon nitride liner, a silicon oxide fill material and a semiconductor cap. A semiconductor oxide structure can be formed by filling voids in the silicon oxide fill material by oxidizing the semiconductor cap into a thermal semiconductor oxide material portion.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a semiconductor material layer. Memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack. The sacrificial material layers are replaced with electrically conductive layers. An insulating spacer is formed on sidewalls of the backside trench. A first doped semiconductor material is deposited within the backside trench. Vertical cavities are formed by vertically recessing the first doped semiconductor material at discrete locations that are laterally spaced apart. A second doped semiconductor material is deposited in the vertical cavities. The second doped semiconductor material disrupts a laterally-extending cavity in the first doped semiconductor material, thereby providing a structurally reinforced network of the first and second doped semiconductor materials for a backside contact via structure that is formed in the backside trench.

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Abstract: A 3D memory device includes a multi-layers stacking structure having an O-shaped opening; a memory structure layer having a first string portion and a second string portion disposed on two opposite sides of a sidewall of the O-shaped opening and a connection portion disposed on a bottom of the O-shaped opening and connecting the first and the second string portion; a dielectric pillar disposed in the O-shaped opening and over the connection portion; an isolation body extending along a direction and embedded among the first string portion, the second string portion and the connection portion to isolate the first string portion from the second string portion; a first contact disposed in a first recess defined by the first string portion, the dielectric pillar and the isolation body; and a second contact disposed in a second recess defined by the second string portion, the dielectric pillar and the isolation body.

Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.

Abstract: Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive member, a first semiconductor member, and a first stacked member provided between the first conductive member and the first semiconductor member. The first stacked member includes a first insulating film, a second insulating film provided between the first insulating film and the first semiconductor member, first and second layers. The first layer includes aluminum and nitrogen and is provided between the first and second insulating films. A first thickness of the first layer along a first direction is 3 nm or less. The first direction is from the first semiconductor member toward the first conductive member. The second layer contacts the first layer, includes silicon and nitrogen, and is provided at one of a position between the first layer and the second insulating film or a position between the first layer and the first insulating film.

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

Abstract: A semiconductor device includes a lower stack structure on a substrate, an upper stack structure on the lower stack structure, and a channel structure in a channel hole formed through the upper stack structure and the lower stack structure. The channel hole includes a lower channel hole in the lower stack structure, an upper channel hole in the upper stack structure, and a partial extension portion adjacent to an interface between the lower stack structure and the upper stack structure. The partial extension portion is in fluid communication with the lower channel hole and the upper channel hole. A lateral width of the partial extension portion may be greater than a lateral width of the upper channel hole adjacent to the partial extension portion and greater than a lateral width of the upper channel hole adjacent to the partial extension portion.

Abstract: Storage node configurations are described. A storage node (e.g., a floating gate or a charge trap layer of a three-dimensional (3D) NAND flash device) include a channel-facing surface with a radius of curvature. For example, a channel-facing surface of the storage node may be concave. A control gate-facing surface of the storage node may instead, or additionally, also include a radius of curvature. The radius of curvature of the channel-facing and/or control gate-facing surfaces of the storage node is less than or equal to the radius of the channel layer.

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.

Abstract: Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor memory device includes a plurality of electrode structures provided on a substrate and extending in parallel to each other in one direction and each including electrodes and insulating layers alternately stacked on the substrate, a plurality of vertical structures penetrating the plurality of electrode structures, and an electrode separation structure disposed between two of the plurality of electrode structures adjacent to each other. Each of the electrodes includes an outer portion adjacent to the electrode separation structure, and an inner portion adjacent to the plurality of vertical structures. A thickness of the outer portion is smaller than a thickness of the inner portion.

Abstract: A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first signal line, a first conductive layer, a first storage layer and a first insulation layer. The first signal line extends in a first direction crossing the substrate. The first conductive layer extends in a second direction crossing the first direction and being parallel to the substrate, and has a first surface and a second surface that is away from the first signal line in a third direction crossing the first and second directions. The first storage layer is provided between the first signal line and the first conductive layer. The first insulation layer is provided between the second surface and the first storage layer.

Abstract: A vertical memory device includes conductive lines on a substrate, first and second semiconductor patterns, first and second pads, first and second electrodes, a third electrode, and a first division pattern. The conductive lines are stacked in a vertical direction and extend in a first direction. The first and second semiconductor patterns extend through the conductive lines in the vertical direction. The first and second pads are formed on the first and second semiconductor patterns. The first and second electrodes are electrically connected to the first and second pads. The third electrode is electrically connected to a first conductive line of the conductive lines. The first division pattern extends in a second direction, and extends through and divides the first conductive line. In a plan view, the first and second semiconductor patterns and the first conductive line are disposed at one side of the first division pattern.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.