Particular Electrode Material Patents (Class 257/32)
  • Publication number: 20040206952
    Abstract: An article including a substrate, a layer of an inert oxide material upon the surface of the substrate, a layer of an amorphous oxide or oxynitride material upon the inert oxide material layer, a layer of an oriented cubic oxide material having a rock-salt-like structure upon the amorphous oxide material layer, and a layer of a SrRuO3 buffer material upon the oriented cubic oxide material layer is provided together with additional layers such as a HTS top-layer of YBCO directly upon the layer of a SrRuO3 buffer material layer. With a HTS top-layer of YBCO upon at least one layer of the SrRuO3 buffer material in such an article, Jc's of up to 1.3×106 A/cm2 have been demonstrated with projected Ic's of over 200 Amperes across a sample 1 cm wide.
    Type: Application
    Filed: May 6, 2004
    Publication date: October 21, 2004
    Inventors: Quanxi Jia, Stephen R. Foltyn, Paul N. Arendt, James R. Groves
  • Patent number: 6790675
    Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: September 14, 2004
    Assignees: International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Yoshihiro Ishimaru, Masahiro Horibe, Osami Horibe, Yoshinobu Tarutani, Keiichi Tanabe
  • Patent number: 6777808
    Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Quentin P. Herr, Lynn A. Abelson, George L. Kerber
  • Patent number: 6750473
    Abstract: A transistor having a channel width, W, and a channel length, L, defined by non-rectangular electrodes. The transistor is a thin film field effect transistor having an insulated gate electrode. One of a source and drain electrodes is connected to a display electrode and one is connected to a data line. The source and drain electrodes can be interdigitated to provide a desired W/L ratio. The gate is connected to a select line. An overlap region between a display electrode and a select line for another pixel defines a capacitor. The transistor is fabricated to be situated behind the display electrode so as to maximize an aperture ratio. The design enables the use of conventional printing methods, such as screen printing, ink jet printing, printing through a stencil, flexo-gravure printing and offset printing.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 15, 2004
    Assignee: E-Ink Corporation
    Inventors: Karl R. Amundson, Gregg Duthaler, Paul S. Drzaic
  • Patent number: 6649929
    Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: November 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, Chang C. Tsuei
  • Publication number: 20030209706
    Abstract: A mesa-shaped superconducting-superlattice structure is formed and adhered with epoxy onto a dielectric substrate where plural superconducting layers and plural insulating layers are naturally and alternately stacked. A &lgr;/4 micro strip line (which means the length of the strip line is one-fourth of the wavelength of a microwave to be introduced) is electrically connected via a metallic film onto the mesa structural portion of the superconducting-superlattice structure, and a metallic electrode is electrically connected to the additional mesa structural portion of the superconducting-superlattice structure via a metallic film.
    Type: Application
    Filed: March 21, 2003
    Publication date: November 13, 2003
    Applicant: UTSUNOMIYA UNIVERSITY
    Inventors: Akinobu Irie, Ginichiro Oya
  • Publication number: 20030094606
    Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.
    Type: Application
    Filed: May 16, 2002
    Publication date: May 22, 2003
    Inventors: Dennis M. Newns, Chang C. Tsuei
  • Patent number: 6545291
    Abstract: A transistor having a channel width, W, and a channel length, L, defined by non-rectangular electrodes. The transistor is a thin film field effect transistor having an insulated gate electrode. One of a source and drain electrodes is connected to a display electrode and one is connected to a data line. The source and drain electrodes can be interdigitated to provide a desired W/L ratio. The gate is connected to a select line. An overlap region between a display electrode and a select line for another pixel defines a capacitor. The transistor is fabricated to be situated behind the display electrode so as to maximize an aperture ratio. The design enables the use of conventional printing methods, such as screen printing, ink jet printing, printing through a stencil, flexo-gravure printing and offset printing.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: April 8, 2003
    Assignee: E Ink Corporation
    Inventors: Karl R. Amundson, Gregg Duthaler, Paul S. Drzaic
  • Publication number: 20030038285
    Abstract: A solid state dc-SQUID includes a superconducting loop containing a plurality of Josephson junctions, wherein an intrinsic phase shift is accumulated through the loop. In an embodiment of the invention, the current-phase response of the dc-SQUID sits in a linear regime where directional sensitivity to flux through the loop occurs. Changes in the flux passing through the superconducting loop stimulates current which can be quantified, thus providing a means of measuring the magnetic field. Given the linear and directional response regime of the embodied device, an inherent current to phase sensitivity is achieved that would otherwise be unobtainable in common dc-SQUID devices without extrinsic intervention.
    Type: Application
    Filed: July 9, 2002
    Publication date: February 27, 2003
    Inventors: Mohammad H.S. Amin, Timothy Duty, Alexander Omelyanchouk, Geordie Rose, Alexandre Zagoskin, Jeremy P. Hilton
  • Patent number: 6495854
    Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: December 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, Chang C. Tsuei
  • Patent number: 6429494
    Abstract: A semiconductor read-only memory (ROM) has trenches and vertical transistors. The trenches are filled with insulator material during the manufacturing process. Holes, which are as wide as the trenches are etched into the insulator at regions where word lines and decoder lines are to be provided over the trenches in a later manufacturing step. In a subsequent masking process for changing the conductivity characteristic of channel regions of transistors, channel regions selected according to programming requirements, are doped. The insulator remaining in the trenches prevents that regions under the insulator material are affected by the masking method.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: August 6, 2002
    Assignee: Infineon Technologies AG
    Inventor: Ulrich Zimmermann
  • Patent number: 6426539
    Abstract: Bolometric detector with intermediate electrical insulation and manufacturing process for this detector. According to the invention, at least two electrodes are formed facing the same face of a layer of bolometric material (5) and starting from the same layer of conducting material (8). Areas (8A, 8B) belonging to the two electrodes are electrically isolated from each other and electrically isolated from the layer of bolometric material, while other areas (7A, 7B) belonging to the two electrodes are separated from each other and are in electrical contact with this layer. The invention is particularly applicable to infrared imagery.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: July 30, 2002
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Michel Vilain, Jean-Jacques Yon
  • Publication number: 20020096429
    Abstract: A Josephson junction includes first and second electrodes, each of which is formed of superconductive material. The first electrode has a first electrode face. A barrier of the junction extends from the first electrode to the second electrode. The barrier has a first barrier face opposing and adjoining the first electrode face. The barrier is formed of non-superconductive barrier material and superconductive barrier material. A concentration of the superconductive barrier material is greater than zero at the first barrier face, whereby the first barrier face is formed at least partially of the superconductive barrier material.
    Type: Application
    Filed: November 5, 2001
    Publication date: July 25, 2002
    Inventors: Ju Gao, Jinglan Sun
  • Publication number: 20020074626
    Abstract: There is provided a superconducting device including a substrate, a first superconductor layer supported by the substrate and containing Ln, AE, M and O, and a second superconductor layer containing a material represented by a formula of (Yb1−yLn′y)AE′2M′3Oz, the first and second superconductor layers forming a junction, and atomic planes each including M and O in the first superconductor layer and atomic planes each including M′ and O in the second superconductor layer being discontinuous to each other in a position of the junction, wherein each of Ln and Ln′ represents at least one metal of Y and lanthanoids, each of AE and AE′ represents at least one of alkaline earth metals, each of M and M′ represents a metal which contains 80 atomic % or more of Cu, y represents a value between 0 and 0.9, and z represents a value between 6.0 and 8.0.
    Type: Application
    Filed: October 30, 2001
    Publication date: June 20, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshihiko Nagano, Jiro Yoshida
  • Patent number: 6365912
    Abstract: A superconductive tunnel junction device in which quasiparticles in a superconductive region (S1), relax into a normal metal trap (N1) releasing their potential energy in electron-electron interactions to increase the number of excited charge carriers in the trap. The excited charge carriers tunnel through an insulating tunnel junction barrier (I2) into a second superconductive region (S2). The quasiparticles in the first superconductive region are formed either by absorption or energetic particles/radiation or by injection by charge carriers tunneling in from a base region which can be of normal metal (N0) or superconductor (or both) of semiconductor. The current from the trap to the second superconductor is higher than that out of the base region thus providing current amplification. The device can thus form a three terminal transistor-like device. It can be used as or in particle/radiation detectors, as an analogue signal amplifier, microrefrigerator or digital switch.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: April 2, 2002
    Assignee: Isis Innovation Limited
    Inventors: Norman Ewart Booth, Joel Nathan Ullom, Michael Nahum
  • Patent number: 6353234
    Abstract: The invention concerns a layered arrangement comprising at least one layer based on a high-temperature superconductive material with at least one unit cell having a CuO2 plane, the layer being connected to a non-supeconductive layer. A modified interface layer is provided between the two layers. Alternatively, at least one of the contacting layers can be modified in the interface region. Modification can be brought about by doping with metallic ions or implantation.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: March 5, 2002
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Mikhail Faley, Ulrich Poppe, Chunlin Jia
  • Patent number: 6348699
    Abstract: A superconductive device is disclosed, which has specific characteristics of a generator and/or detector of sub-millimeter wave length radiation, comprising a two-dimensional lateral array of mesas (column-shaped elements) each containing vertically stacked Josephson junctions on top of one another. This device is capable of covering the entire frequency range between the microwave and far infrared spectral regions, in plurality of applications, where radiation emission and detection is involved. According to its various embodiments, thin columns (stacks) of Josephson junctions are monolithically built between superconducting electrical top and bottom contact layers. Mutually isolated segments cut out of the contact layers allow for optimization of circuit parameters such as impedance matching to load and maximizing the output power. External electronic control allows modulation of the radiation field and other operation modes of the device.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: February 19, 2002
    Assignee: Oxxel Oxide Electronics Technology GmbH
    Inventor: Alfred Zehe
  • Publication number: 20010035524
    Abstract: A superconductive device is disclosed, which has specific characteristics of a generator and/or detector of sub-millimeter wavelength radiation, comprising a two-dimensional lateral array of mesas (column-shaped elements) each containing vertically stacked Josephson junctions on top of one another. This device is capable of covering the entire frequency range between the microwave and far infrared spectral regions, in a plurality of applications, where radiation emission and detection is involved. According to its various embodiments, thin columns (stacks) of Josephson junctions are monolithically built between superconducting electrical top and bottom contact layers. Mutually isolated segments cut out of the contact layers allow for optimization of circuit parameters such as impedance matching to load and maximizing the output power. External electronic control allows modulation of the radiation field and other operation modes of the device.
    Type: Application
    Filed: June 20, 2001
    Publication date: November 1, 2001
    Applicant: OXXEL OXIDE ELECTRONICS TECHNOLOGY GMBH
    Inventor: Alfred Zehe
  • Patent number: 6274412
    Abstract: A process sequence is disclosed for fabricating arrays of Thin Film Transistors by printing metallic conductors for the gate and data lines and possibly the Indium Tin Oxide Pixel electrode as well. The process eliminates conventional step-and-repeat photolithographic patterning, and provides high conductivity metallization for large arrays. These arrays may be used in displays, detectors and scanners.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: August 14, 2001
    Assignee: Parelec, Inc.
    Inventors: Paul H. Kydd, Sigurd Wagner, Helena Gleskova
  • Patent number: 6121630
    Abstract: A high-temperature superconducting thin film of compound oxide selected from the group consisting of:Y.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Ho.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Lu.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,Sm.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Nd.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Gd.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,Eu.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Er.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Dy,Ba.sub.2 Cu.sub.3 O.sub.7-x,Tm.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x, Yb.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x La.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-x,(La, Sr).sub.2 CuO.sub.4-x,which is deposited on a substrate of sapphire, with the outer surface of the high-temperature superconducting thin film being covered with a protective crystalline film of SrTiO.sub.3.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: September 19, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideo Itozaki, Saburo Tanaka, Nobuhiko Fujita, Shuji Yazu, Tetsuji Jodai
  • Patent number: 6088604
    Abstract: A superconductor-normal conductor junction device comprises first and second regions (1, 3) of normal material forming first and second junctions with a superconducting material (2), the Fermi level of the first region of normal material being so arranged relative to a given energy level in the superconducting material that charge carriers in the first normal material undergo Andreev reflection at the first junction, resulting in pairs of the charge carriers entering said given energy level in the superconducting material, and the Fermi level of the second region of normal material being so arranged relative to said given level in the superconducting material that said charge carriers conduct from the superconducting material through the second region.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: David Arfon Williams, Adrian Michael Marsh, Haroon Ahmed, Bruce William Alphenaar
  • Patent number: 6084246
    Abstract: Compounds of the general formula A.sub.4 MeSb.sub.3 O.sub.12 wherein A is either barium (Ba) or strontium (Sr) and Me is an alkali metal ion selected from the group consisting of lithium (Li), sodium (Na) and potassium (K) have been prepared and included in high critical temperature thin film superconductors, ferroelectrics, pyroelectrics, piezoelectrics, and hybrid device structures.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: July 4, 2000
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Arthur Tauber, Steven C. Tidrow, William D. Wilber, Robert D. Finnegan
  • Patent number: 6023072
    Abstract: A Josephson junction having a laminar structure which includes a substrate, a first superconductive layer deposited on the substrate, a non-superconductive layer deposited on the first superconductive layer, and a second superconductive layer deposited on the non-superconductive layer. The laminar structure has three segments, including: a first planar segment, a second planar segment, and a ramp segment connecting the two planar segments at an ascent angle thereto. The layers are of substantially uniform thickness in the three segments, with the substrate being thinner in the second planar segment than in the first planar segment and having a constantly-decreasing thickness in the ramp segment. The superconductive layers and the non-superconductive layer are deposited in-situ and are epitaxial with a c-axis in a direction substantially normal to the first and second planar segments.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: February 8, 2000
    Assignee: TRW Inc.
    Inventor: Arnold H. Silver
  • Patent number: 5982034
    Abstract: Thin films of isotropically conductive material are formed from Sr.sub.1-x Ca.sub.x RuO.sub.3. This material is easily deposited as a thin film by methods such as 90.degree. off-axis sputtering and laser ablation. The materials are epitaxially deposited on a wide variety of substrates and allow overlying epitaxial growth of an equally large number of significant oxides such as superconducting oxides, dielectric, and ferroelectric materials.
    Type: Grant
    Filed: November 19, 1993
    Date of Patent: November 9, 1999
    Assignee: Lucent Technologies Inc.
    Inventors: Robert Joseph Cava, Chang-Beom Eom
  • Patent number: 5965900
    Abstract: The invention relates to a detector cell comprising tunnel-effect superconductive devices organized in a two-dimensional array and placed on a common substrate, each superconductive device comprising a tunnel-effect superconductive junction and being electrically connected to a bottom connection area and to a top connection area. The superconductive devices are separated from one another by trenches extending down to and including the bottom connection area and defining individual bottom connection areas disposed between each of said junctions and the substrate. At least one individual bottom connection area is electrically connected to at least one bottom connection area of an adjacent superconductive device by a localized bridge region.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: October 12, 1999
    Assignee: Agence Spatiale Europeenne
    Inventors: Anthony Peacock, Robert Venn
  • Patent number: 5962866
    Abstract: A superconductor device has a substrate with an inclined surface that divides the substrate surface into a lower planar substrate surface and an upper planar substrate surface. A lower layer of an anisotropic superconductor material is epitaxially deposited on the lower planar substrate surface so that an a-axis of the anisotropic superconductor material of the lower layer is exposed at a top edge of the lower layer. An upper layer of an anisotropic superconductor material is epitaxially deposited on the upper planar substrate surface so that an a-axis of the anisotropic superconductor material of the upper layer is exposed at a top edge of the upper layer. A layer of a non-superconductor material overlies the inclined surface and the layers of anisotropic superconductor material.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: October 5, 1999
    Assignee: Biomagnetic Technologies, Inc.
    Inventors: Mark S. DiIorio, Shozo Yoshizumi, Kai-Yueh Yang
  • Patent number: 5939730
    Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: August 17, 1999
    Assignee: TRW Inc.
    Inventors: Dale J. Durand, Kei F. Lau
  • Patent number: 5917199
    Abstract: A TFT structure includes a variably doped contact layer system in order to reduce leakage current characteristics and increase mobility of the TFT. Such TFTs may be utilized in, for example, X-ray imagers or liquid crystal displays. In certain embodiments, the contact layer system is lightly doped adjacent a semiconductor or channel layer, and is more heavily doped adjacent the source/drain electrodes. The variation in doping density of the contact layer system may be performed in a step-like manner, gradually, continuously, or in any other suitable manner. In certain embodiments, the contact layer system may include a single layer which is deposited over an intrinsic semiconductor layer, with the amount of dopant gas being used during the deposition process being adjusted through the deposition of the single layer so as to cause the doping density to vary (increase or decrease) throughout the thickness of the system/layer.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: June 29, 1999
    Assignee: OIS Optical Imaging Systems, Inc.
    Inventors: Young Hee Byun, Yiwei Lu
  • Patent number: 5897367
    Abstract: A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: April 27, 1999
    Assignee: TRW Inc.
    Inventors: George L. Kerber, Lynn A. Abelson, Raffi N. Elmadjian, Eric G. Ladizinsky
  • Patent number: 5831279
    Abstract: A device with weak links (Josephson junctions) in a superconducting film has two single crystals connected through an interconnecting arrangement that may have one or more sublayers. At least two grain boundaries or at least one barrier are/is formed in the substrate.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: November 3, 1998
    Assignee: Telefonktiebolaget LM Ericsson
    Inventors: Erland Wikborg, Evgeni Stepantsov, Zdravko Ivanov, Tord Claeson
  • Patent number: 5821557
    Abstract: A Josephson junction includes a substrate, a first superconducting layer, a second superconducting layer transversely overlaid on the first layer with an insulating layer interposed therebetween, the insulating layer is an oxide or a nitride of the superconducting material, and the insulating layer including a low oxygen- or nitrogen-concentrated area in contact with each of the first and second layers. A process for fabricating the Josephson junction includes the steps of preparing a substrate, forming a first superconducting layer, forming a second superconducting layer transversely on the first layer with an insulating layer interposed therebetween wherein the insulating layer is an oxide or nitride of the superconducting material, and injecting ion beams into the insulating layer so as to form low oxygen- or nitrogen-concentrated area linking the first and second layers.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: October 13, 1998
    Assignee: Shimadzu Corporation
    Inventors: Shinji Nagamachi, Masahiro Ueda, Kei Shinada, Mitsuyoshi Yoshii
  • Patent number: 5801393
    Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: September 1, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun-Yong Sung, Jeong-Dae Suh
  • Patent number: 5757243
    Abstract: An effective high frequency oscillator is made of a plurality of Josephson devices. A high frequency converter as a high frequency circuit is made of the high frequency oscillator, nonlinear superconductor devices, and transmission line. Josephson devices are connected in parallel to make a superconductor module. Then superconductive modules are connected in series for high frequency via a phase locking circuit such as a thin film type capacitor to make the high frequency oscillator. Consequently, the high frequency oscillator is used as a local oscillator for a frequency converter. The high frequency system comprises a high frequency package housing a high frequency circuit, a cooling unit including a low temperature stage in thermal contact with the high frequency package, and a shielding case for housing the high frequency circuit and the low temperature stage. The high frequency system of the present invention provides a small-sized and power-saving high frequency circuit having operational stability.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: May 26, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Mizuno, Akira Enokihara, Hidetaka Higashino, Kentaro Setsune
  • Patent number: 5710437
    Abstract: A radiation detecting device including a superconducting tunnel junction having a three-layer structure formed by depositing a lower electrode, a tunnel barrier layer, and an upper electrode in sequence. The upper electrode, the tunnel barrier layer and lower electrode have substantially aligned side walls around substantially their entire perimeters such that a cross-section of the three-layer structure along a path perpendicular to a direction of the deposition is substantially constant in shape and size along the direction of the deposition and such that no portion of the lower electrode or the upper electrode extends beyond the tunnel barrier layer. At least one of the upper electrode and the lower electrode is made of superconducting material.
    Type: Grant
    Filed: March 2, 1994
    Date of Patent: January 20, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Masahiko Kurakado, Toru Takahashi, Atsuki Matsumura
  • Patent number: 5624885
    Abstract: A Josephson junction device includes a substrate, an oxide thin film formed on a portion of the principal surface of the substrate, which is constituted of a single crystal of which lattices shift at angle of 45.degree. to that of the principal surface of the substrate. One of the two portions of the oxide superconductor thin film is formed on the oxide thin film and the other portion of the superconductor thin film is formed on the principal surface of the substrate directly so that the lattices of the two portions of the oxide superconductor thin film are respectively linear up to those of the oxide thin film and the principal surface of the substrate and the grain boundary. The grain boundary which constitutes a weak link of the Josephson junction is formed just on the step portion formed of the oxide thin film.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: April 29, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Saburo Tanaka, Takashi Matsuura, Hideo Itozaki
  • Patent number: 5510628
    Abstract: Patterned surfaces for the selective adhesion and outgrowth of cells are useful in cell culture devices, prosthetic implants, and cell-based microsensors. Such surfaces may be prepared by a deep ultraviolet photolithographic technique.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: April 23, 1996
    Assignee: Geo-Centers, Inc.
    Inventors: Jacque H. Georger, Jr., David A. Stenger, Thomas L. Fare
  • Patent number: 5498881
    Abstract: A superconducting device has a substrate and a superconducting film formed on the substrate. A surface of the substrate has a first surface portion of which a curvature is constant or changes continuously, a second surface portion of which a curvature is constant or changes continuously, and a third surface portion at which the first and second surface portions meet and at which the curvatures of the first and second surface portions become discontinuous. The superconducting film formed on the surface of said substrate has a grain boundary serving as a junction only in a portion corresponding to the third surface portion of the substrate.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: March 12, 1996
    Assignees: International Superconductivity Technology Ctr., Sharp Kabushiki Kaisha
    Inventors: Manabu Fujimoto, Keiichi Yamaguchi, Youichi Enomoto, Tsutomu Mitsuzuka, Katsumi Suzuki
  • Patent number: 5477061
    Abstract: A Josephson device comprises a first electrode layer of a superconducting material and containing Nb therein as a constituent element, an overlayer of a nitride of a refractory metal element provided on the first electrode layer, a barrier layer of an insulating compound that contains the metal element as a constituent element and acting as a barrier of a Josephson junction, the barrier layer being provided on the overlayer, and a second electrode layer of a superconducting material and containing Nb therein as a constituent element, the second electrode layer being provided on the barrier layer.
    Type: Grant
    Filed: September 20, 1991
    Date of Patent: December 19, 1995
    Assignee: Fujitsu Limited
    Inventor: Shinichi Morohashi
  • Patent number: 5472934
    Abstract: An anisotropic superconductor junction device consisting of a lower superconducting layer and an upper superconducting layer separated by a barrier layer, in which the upper and lower superconducting layers and the barrier layer each have a (103) crystal orientation in which the c axis is arranged in the same direction at an angle of 45 degrees relative to the plane of the junction.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: December 5, 1995
    Assignees: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Hiroshi Akoh, Hiroshi Sato
  • Patent number: 5468723
    Abstract: A superconducting device has a structure of superconductor--normal--conductor (semiconductor)--superconductor. The superconducting regions and the normal-conductor region can be made of the same elements but having different relative proportions of the elements. The device can be fabricated by introducing at least one element into an unmasked region of the superconductor to form a normal conductor region or into unmasked regions of the normal conductor to form superconductor regions.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: November 21, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe
  • Patent number: 5422497
    Abstract: A superconducting device includes a first thin film of oxide superconductor material formed on a substrate, a second thin film of insulator material stacked on the first thin film of oxide superconductor material, and a third thin film of oxide superconductor material formed on the second thin film of insulator material. The second thin film of insulator material is formed of an amorphous oxide including the same constituent elements as those of the oxide superconductor material of the first thin film. The second thin film of insulator material is formed by heat-treating the first thin film of oxide superconductor material in a gaseous atmosphere bringing a surface of the oxide superconductor material into an amorphous condition, after the first thin film of oxide superconductor material has been formed on the substrate.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: June 6, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuchika Saitoh, Sou Tanaka, Michitomo Iiyama
  • Patent number: 5378683
    Abstract: The disclosure relates to a Josephson junction formed by a non-superconducting barrier between two superconducting films of the (R) BaCuO (R=rare earth) group. In order to take advantage of the greater coherence length of superconductors along the CuO planes, i.e. perpendicularly to the long axis "c" of the crystal unit cell, the superconducting film is oriented so that the axis "c" is parallel to the plane of the junction. The device can be applied to Josephson junctions and to SQUIDs.
    Type: Grant
    Filed: April 21, 1992
    Date of Patent: January 3, 1995
    Assignee: Thomson-CSF
    Inventors: Regis Cabanel, Guy Garry, Alain Schuhl, Bruno Ghyselen
  • Patent number: 5362709
    Abstract: A superconducting tunnel junction is disclosed herein. The superconducting tunnel junction is characterized in that a pair of oxide superconducting layers thereof and a tunnel barrier layer located between the oxide superconducting layers have the same or almost the same crystal structure and the same or almost the same lattice constant in a direction of a, b, or c axis. The layers have good crystallization.
    Type: Grant
    Filed: October 22, 1991
    Date of Patent: November 8, 1994
    Assignee: Semiconductor Energy Laboratory, Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 5358925
    Abstract: An HTSC material epitaxially deposited on a YSZ buffer layer on a surface of a monocrystalline silicon substrate has a zero resistance transition temperature of at least 85.degree. K., a transition width (10-90%) of no more than 1.0.degree. K., a resistivity at 300.degree. K. of no more than 300 micro-ohms-centimeter and a resistivity ratio (at 300.degree. K./100.degree. K.) of 3.0.+-. 0.2. The surface of the silicon substrate is cleaned using a spin-etch process to produce an atomically clean surface terminated with an atomic layer of an element such as hydrogen with does not react with silicon. The substrate can be moved to a deposition chamber without contamination. The hydrogen is evaporated in the chamber, and then YSZ is epitaxially deposited preferably by laser ablation. Thereafter, the HTSC material, such as YBCO, is epitaxially deposited preferably by laser ablation. The structure is then cooled in an atmosphere of oxygen.
    Type: Grant
    Filed: August 10, 1992
    Date of Patent: October 25, 1994
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: George A. Neville Connell, David B. Fenner, James B. Boyce, David K. Fork
  • Patent number: 5334580
    Abstract: A superconducting device has a structure of superconductor - normal-conductor (semiconductor) - superconductor. The superconductors constituting the superconducting device are made of a superconducting oxide material of K.sub.2 NiF.sub.4 type crystal-line structure or perovskite type crystalline structure which contains at least one element selected from the group consisting of Ba, Sr, Ca, Mg and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu and Tb; Cu; and O.
    Type: Grant
    Filed: January 14, 1993
    Date of Patent: August 2, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe
  • Patent number: 5321276
    Abstract: A superconducting tunnel junction radiation sensing device includes first and second superconductor electrodes and a tunnel barrier layer interposed therebetween. The tunnel barrier layer is made up of a thin-wall portion and a thick-wall portion each formed of a semiconductor or an insulator, and each having opposite surfaces respectively contacting the first and second superconductor electrodes, and each extending adjacent each other in a same horizontal plane between the first and second electrodes. The thick-wall portion has a vertical thickness which is at least twice that of the thin-wall portion. Furthermore, the thickness of the thin-wall portion is such that a tunnel effect is enabled therethrough form the first electrode to the second electrode, and the thickness of the thick-wall portion is such that a tunnel effect is substantially prohibited therethrough from the first electrode to the second electrode.
    Type: Grant
    Filed: October 1, 1991
    Date of Patent: June 14, 1994
    Assignee: Nippon Steel Corporation
    Inventors: Masahiko Kurakado, Atsuki Matsumura, Takeshi Kaminaga, Tooru Takahashi
  • Patent number: 5306705
    Abstract: A non-linear superconducting junction device comprising a layer of high transient temperature superconducting material which is superconducting at an operating temperature, a layer of metal in contact with the layer of high temperature superconducting material and which remains non-superconducting at the operating temperature, and a metal material which is superconducting at the operating temperature and which forms distributed Sharvin point contacts with the metal layer.
    Type: Grant
    Filed: May 6, 1993
    Date of Patent: April 26, 1994
    Assignee: Board of Trustees of the Leland Stanford Junior University
    Inventors: Matthew J. Holcomb, William A. Little
  • Patent number: 5291035
    Abstract: A microelectronic component comprising a crossover is provided comprising a substrate, a first high T.sub.c superconductor thin film, a second insulating thin film comprising SrTiO.sub.3 ; and a third high T.sub.c superconducting film which has strips which crossover one or more areas of the first superconductor film. An in situ method for depositing all three films on a substrate is provided which does not require annealing steps and which can be opened to the atmosphere between depositions.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: March 1, 1994
    Assignee: The Regents of the University of California
    Inventors: Frederick C. Wellstood, John J. Kingston, John Clarke
  • Patent number: 5266815
    Abstract: Technology for using a wiring of a superconductive material in semiconductor integrated circuit device. An isolation layer and/or a barrier layer are provided for preventing diffusion of harmful composition of the superconductive material for the semiconductor device. Control of a circuit can be made utilizing the characteristics of a superconductive material. Also, the characteristics of a superconductive material may be controlled. A method of forming a layer of superconductive material, well compatible with the widely used process of manufacturing integrated circuit devices, is also disclosed.
    Type: Grant
    Filed: April 6, 1992
    Date of Patent: November 30, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Toshikazu Nishino, Shoji Shukuri, Yasuo Wada, Yutaka Misawa, Takahiko Kato
  • Patent number: 5247189
    Abstract: A tunnel junction type superconducting device includes a pair of superconductor electrodes formed of compound oxide superconductor material, and a metal layer of a high electric conductivity formed between the pair of superconductor electrodes so as to maintain the pair of superconductor electrodes separate from each other. The pair of superconductor electrodes is separated from each other by a distance within a range of 3 nm to 70 nm by action of the metal layer.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: September 21, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Saburo Tanaka, Hideo Itozaki, Shuji Yazu