Abstract: An electronic device can include a drain region of a transistor, wherein the drain region has a first conductivity type. The electronic device can also include a channel region of the transistor, wherein the channel region has a second conductivity type opposite the first conductivity type. The electronic device can further include a first doped region having the first conductivity type, wherein the first doped region extends from the drain region towards the channel region. The electronic device can still further include a second doped region having the first conductivity type, wherein the second doped region is disposed between the first doped region and the channel region.

Abstract: A vertically arranged laterally diffused metal-oxide-semiconductor (LDMOS) device comprises a trench extending into a semiconductor body toward a semiconductor substrate. The trench includes sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material. A lightly doped drain region adjoins the trench and extends laterally around the sidewalls from the diffusion agent layer into the semiconductor body. In one embodiment, a method for fabricating a vertically arranged LDMOS device comprises forming a trench extending into a semiconductor body toward a semiconductor substrate, the trench including sidewalls, a bottom portion connecting the sidewalls, a dielectric material lining the trench and a diffusion agent layer lining the dielectric material.

Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.

Abstract: A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.

Abstract: A high performance, power integrated circuit composed of two charge balanced, extended drain NMOS transistors (CBDEMOS) formed on an n-substrate. A CBDENMOS transistor with an n-type substrate source. A charge balanced channel diode (CBCD) with an n-type substrate. A process for forming a high performance, power integrated circuit composed of two CBDENMOS transistors formed on an n-substrate. A process for forming a power integrated circuit composed of one CBDENMOS transistor and one CBCD on an n-type substrate.

Abstract: A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated.

Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a modified breakdown shallow trench isolation (STI) region to effectively reduce a drain to source resistance when compared to a conventional semiconductor device, thereby increasing the breakdown voltage of the semiconductor device when compared to the conventional semiconductor device. The modified breakdown STI region allows more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device. The semiconductor device may include a modified well region to further reduce the drain to source resistance of the semiconductor device.

Abstract: The invention relates to a method for the production of both MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors, whose gates are laterally defined by spacers in a p-substrate or a p-well in an n-substrate. The aim of the invention is to provide a method for the production of MOS transistors with extremely low leakage currents that allows for parallel logic/switching transistors.

Abstract: According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

Abstract: In a semiconductor substrate of a first conductivity type, first to third drain offset regions of a second conductivity type are formed in that order in a bottom up manner. A body region of the first conductivity type is formed partly in the second drain offset region and partly in the third drain offset region. The second drain offset region has a lower impurity concentration than the first and third drain offset regions. A curvature portion of the body region is located in the second drain offset region.

Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.

Abstract: A thin film transistor includes a gate electrode and a semiconductor layer. The semiconductor layer includes a channel region, a source region, a drain region, a low-concentration impurity region provided between the channel region and the source or drain region and a high-concentration impurity region. The high-concentration impurity region overlaps with the gate electrode.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: A transistor including a source region, drain region, channel region, drift region, isolation region, a first gate structure over the channel region, and a second gate structure over the isolation region is provided. The drift region includes a first portion located under the isolation region and a second portion located laterally adjacent to the isolation region. The first gate structure is separated by a first separation space from the second gate structure. The first separation space is located over a portion of the second portion of the drift region and a portion of the isolation region.

Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

Abstract: A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.

Abstract: In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

Abstract: CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.

Abstract: A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate.

Abstract: A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other.

Abstract: System and method for metal-oxide-semiconductor field effect transistor. In a specific embodiment, the invention provides a field effect transistor (FET), which includes a substrate material, the substrate material being characterized by a first conductivity type, the substrate material including a first portion, a second portion, and a third portion, the third portion being positioned between the first portion and the second portion. The FET also includes a source portion positioned within the first portion, the source portion being characterized by a second conductivity type, the second conductivity type being opposite of the first conductivity type. A first drain portion is positioned within second portion and characterized by the second conductivity type and a first doping concentration.

Abstract: A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Abstract: A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position.

Abstract: A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Abstract: Semiconductor devices and methods for fabricating the same are disclosed. The semiconductor device includes gate electrodes having sidewall spacers on a semiconductor substrate, double diffusion drain regions in the semiconductor substrate adjacent to the sidewall spacers, double diffusion junction regions aligned with the gate electrodes, and source/drain regions in the double diffusion junction regions.

Abstract: An anti punch-through leakage current MOS transistor and a manufacturing method thereof are provided. A high voltage deep first type well region and a first type light doping region are formed in a second type substrate. A mask with a dopant implanting opening is formed on the second type substrate. An anti punch-through leakage current structure is formed by implanting the first type dopant through the dopant implanting opening. A doping concentration of the first type dopant of the high voltage deep first type well region is less than that of the anti punch-through leakage current structure and greater than that of the high voltage deep first type well region. A second type body is formed by implanting a second type dopant through the dopant implanting opening. A gate structure is formed on the second type substrate.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: A semiconductor device includes: a semiconductor substrate; a silicon pillar provided perpendicularly to a main surface of the semiconductor substrate; a gate dielectric film that covers a portion of a side surface of the silicon pillar; an insulator pillar that covers remaining portions of the side surface of the silicon pillar; a gate electrode that covers the silicon pillar via the gate dielectric film and the insulator pillar; an interlayer dielectric film provided above the silicon pillar, the gate dielectric film, the insulator pillar, and the gate electrode; and a gate contact plug embedded in a contact hole provided in the interlayer dielectric film, and in contact with the gate electrode and the insulator pillar. A film thickness of the insulator pillar in a lateral direction is thicker than a film thickness of the gate dielectric film in a lateral direction.

Abstract: A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

Abstract: A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with the graded junction space. By using a p-well blocking layer to separate the p-well(s) and the n-well, breakdown voltage characteristic is improved without the cost of an additional mask or process change.

Abstract: According to an embodiment, a semiconductor device includes a gate electrode formed on a semiconductor substrate via an insulating layer; a source region including an extension region, a drain region including an extension region, a first diffusion restraining layer configured to prevent a diffusion of the conductive impurity in the source region and including an impurity other than the conductive impurity, and a second diffusion restraining layer configured to prevent a diffusion of the impurity in the drain region and including the impurity other than the conductive impurity.

Abstract: A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated.

Abstract: A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 500, 510, or 530; or 220, 220W, or 540) is provided with a hypoabrupt vertical dopant profile below one (104; or 264 or 564) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108; or 268 or 568). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone.

Abstract: A high-voltage metal-oxide-semiconductor (HVMOS) device having increased breakdown voltage and methods for forming the same are provided. The HVMOS device includes a semiconductor substrate; a gate dielectric on a surface of the semiconductor substrate; a gate electrode on the gate dielectric; a source/drain region adjacent and horizontally spaced apart from the gate electrode; and a recess in the semiconductor substrate and filled with a dielectric material. The recess is between the gate electrode and the source/drain region, and is horizontally spaced apart from the gate electrode.

Abstract: A method of manufacturing a semiconductor device, has forming a gate insulating film over a surface of a substrate, eliminating a portion of the gate insulating film in a region, forming a gate electrode over the gate insulating film and a drain electrode on the region, implanting first impurities into the substrate using the gate electrode and the drain electrode as a mask, forming an insulating film to fill the space between the gate electrode and the drain electrode, and implanting second impurities into the substrate to form a source region using the gate electrode, the drain electrode and the insulating film as a mask.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: An partially depleted Dieler LDMOSFET transistor (100) is provided which includes a substrate (150), a drift region (110) surrounding a drain region (128), a first well region (107) surrounding source region (127), a well buffer region (106) separating the drift region and first well region to at least partly define a first channel region, a gate electrode (118) formed over the first channel region having a source-side gate edge aligned with the first well region (107), an LDD extension region (120) extending from the source region to the channel region, and a dielectric RESURF drain extension structure (161) formed at the drain of the gate electrode (118) using the plurality of STI stripes (114).

Abstract: A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy implantation are blocked by the conductive gate. The method further includes performing a high energy implantation using a third dopant type and being applied to the entire device area. The dopants of the high energy implantation penetrate the conductive gate and is introduced into the entire device active area including underneath the conductive gate. After annealing, a double-diffused lightly doped drain (DLDD) region is formed from the high and low energy implantations and is used as a drift region of the lateral DMOS transistor. The DLDD region overlaps with the body region at a channel region and interacts with the dopants of the body region to adjust a threshold voltage of the lateral DMOS transistor.

Abstract: A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

Abstract: A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.

Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.