Substrate Is Single Crystal Insulator (e.g., Sapphire Or Spinel) Patents (Class 257/352)
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Publication number: 20120205744Abstract: Embodiments of the invention provide SOI body-contacted transistors that can be used for high frequency analog and digital circuits. In accordance with certain embodiments of the invention, the SOI transistor gate can have an “I” shape, similar to the shape of the gate of a floating body SOI transistor. However, a body region is provided that extends perpendicular to the width direction of the gate and is contacted at an end of the extended body region. To form such a body contact structure, a source/drain implant block mask and silicide block mask are used during the formation of the source/drain regions. The source/drain implant block mask and silicide block mask can be formed on the same region, but the silicide block mask can allow for the body contact portion at the end of the extended body region to be silicided during the siliciding of the source/drain regions.Type: ApplicationFiled: February 10, 2012Publication date: August 16, 2012Inventors: Kenneth K. O, Chieh-Lin Wu
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Patent number: 8241997Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.Type: GrantFiled: July 10, 2008Date of Patent: August 14, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8227866Abstract: A semiconductor substrate having an SOI layer is provided. Between an SOI layer and a glass substrate, a bonding layer is provided which is formed of one layer or a plurality of layers of phosphosilicate glass, borosilicate glass, and/or borophosphosilicate glass, using organosilane as one material by a thermal CVD method at a temperature of 500° C. to 800° C.Type: GrantFiled: June 24, 2011Date of Patent: July 24, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tetsuya Kakehata
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Patent number: 8217488Abstract: A method for enhancing light extraction efficiency of GaN light emitting diodes is disclosed. By cutting off a portion from each end of bottom of a sapphire substrate or forming depressions on the bottom of the substrate and forming a reflector, light beams emitted to side walls of the substrate can be guided to the light emitting diodes.Type: GrantFiled: July 19, 2010Date of Patent: July 10, 2012Assignee: Walsin Lihwa CorporationInventors: Shiue-Lung Chen, Jeng-Guo Feng, Jang-Ho Chen, Ching-Hwa Chang Jean
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Patent number: 8217498Abstract: Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.Type: GrantFiled: October 18, 2007Date of Patent: July 10, 2012Assignee: Corning IncorporatedInventors: Rajaram Bhat, Kishor Purushottam Gadkaree, Jerome Napierala, Linda Ruth Pinckney, Chung-En Zah
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Publication number: 20120132994Abstract: Embodiments of the present invention relate generally to semiconductor devices and, more particularly, to a structure for high-voltage (HV) semiconductor-on-insulator (SOI) devices and methods for their formation. In one embodiment, the invention provides a semiconductor-on-insulator (SOI) device comprising: a substrate; an insulator layer atop the substrate; a polysilicon layer atop the insulator layer; a device layer atop the polysilicon layer, the device layer comprising: a P-well; an N-well; and an undoped silicon region between the P-well and the N-well; and a trench isolation adjacent one of the P-well and the N-well and extending through the device layer and the polysilicon layer to the insulator layer.Type: ApplicationFiled: November 29, 2010Publication date: May 31, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William F. Clark, JR., Yun Shi
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Patent number: 8138010Abstract: A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features.Type: GrantFiled: March 24, 2011Date of Patent: March 20, 2012Assignee: SanDisk 3D LLCInventors: Roy E. Scheuerlein, Steven Radigan
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Patent number: 8134207Abstract: In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 ?m or more.Type: GrantFiled: February 8, 2008Date of Patent: March 13, 2012Assignee: Hitachi, Ltd.Inventor: Atsuo Watanabe
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Patent number: 8106449Abstract: To achieve a stable reading operation in a memory cell having a gain-cell structure, a write transistor is configured, which has a source and a drain that are formed on the insulating layer, a channel formed on the insulating layer and between the source and the drain and made of a semiconductor, and a gate formed on an upper portion of the insulating layer and between the source and the drain and electrically insulated from the channel by a gate insulating film and controlling the potential of the channel. The channel electrically connects the source and the drain on the side surfaces of the source and the drain.Type: GrantFiled: July 27, 2006Date of Patent: January 31, 2012Assignee: Renesas Electronics CorporationInventors: Toshiaki Sano, Tomoyuki Ishii, Norifumi Kameshiro, Toshiyuki Mine
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Patent number: 8053840Abstract: The invention relates to thin film transistors comprising novel dielectric layers and novel electrodes comprising metal compositions that can be provided by a dry thermal transfer process.Type: GrantFiled: March 13, 2009Date of Patent: November 8, 2011Assignee: E. I. du Pont de Nemours and CompanyInventors: Richard Kevin Bailey, Graciela Beatriz Blanchet, John W. Catron, Jr., Reid John Chesterfield, Marc B. Goldfinger, Gary Delmar Jaycox, Lynda Kaye Johnson, Irina Malajovich, Hong Meng, Jeffrey Scott Meth, Kenneth George Sharp, Rinaldo Soria Schiffino, Feng Gao, Gerald Donald Andrews
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Publication number: 20110227637Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.Type: ApplicationFiled: February 15, 2011Publication date: September 22, 2011Inventors: Michael A. Stuber, Christopher N. Brindle, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Mark L. Burgener, Alexander Dribinsky, Tae Youn Kim
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Patent number: 8013327Abstract: A thin-film transistor includes an insulating substrate, a source electrode, and a drain electrode, disposed over the top of the insulating substrate, a semiconductor layer electrically continuous with the source electrode, and the drain electrode, respectively, a gate dielectric film formed over the top of at least the semiconductor layer; and a gate electrode disposed over the top of the gate dielectric film so as to overlap the semiconductor layer. Further, a first bank insulator is formed so as to overlie the source electrode, a second bank insulator is formed so as to overlie the drain electrode, and the semiconductor layer, the gate dielectric film, and the gate electrode are embedded in a region between the first bank insulator, and the second bank insulator.Type: GrantFiled: April 24, 2009Date of Patent: September 6, 2011Assignee: Hitachi, Ltd.Inventors: Masahiro Kawasaki, Masaaki Fujimori, Takeo Shiba, Shuji Imazeki, Tadashi Arai
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Patent number: 7989324Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.Type: GrantFiled: July 8, 2009Date of Patent: August 2, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Kimiaki Shimokawa
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Publication number: 20110180811Abstract: It is an object to provide a wireless chip which can increase a mechanical strength, and a wireless chip with a high durability. A wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, and a conductive layer connecting the chip and the antenna. Further, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a sensor device, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the sensor device. Moreover, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a battery, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the battery.Type: ApplicationFiled: April 7, 2011Publication date: July 28, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yukie SUZUKI, Yasuyuki ARAI, Shunpei YAMAZAKI
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Publication number: 20110169550Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener
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Patent number: 7960736Abstract: The present invention relates to a semiconductor-on-insulator structure including a semiconductor component comprised of substantially single-crystal semiconductor material layer and a single-crystal semiconductor material with an enhanced oxygen content layer; an oxide glass material layer; and a glass-ceramic layer.Type: GrantFiled: September 26, 2008Date of Patent: June 14, 2011Assignee: Corning IncorporatedInventors: Kishor P. Gadkaree, Linda R. Pinckney
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Patent number: 7943933Abstract: Disclosed herein is a TFT substrate which exhibits good characteristic properties despite the omission of the barrier metal layer to be normally interposed between the source-drain electrodes and the semiconductor layer in the TFT. The TFT substrate permits sure and direct connection with the semiconductor layer of the TFT. The thin film transistor substrate has a substrate, a semiconductor layer and source-drain electrodes. The source-drain electrodes are composed of oxygen-containing layers and thin films of pure copper or a copper alloy. The oxygen-containing layer contains oxygen such that part or all of oxygen combines with silicon in the semiconductor layer. And, the thin films of pure copper or a copper alloy connect with the semiconductor layer of the thin film transistor through the oxygen-containing layers.Type: GrantFiled: May 23, 2008Date of Patent: May 17, 2011Assignee: Kobe Steel, Ltd.Inventors: Aya Hino, Hiroshi Gotou
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Patent number: 7935958Abstract: The present invention provides a semiconductor device which has a storage element having a simple structure in which an organic compound layer is sandwiched between a pair of conductive layers and a manufacturing method of such a semiconductor device. With this characteristic, a semiconductor device having a storage circuit which is nonvolatile, additionally recordable, and easily manufactured and a manufacturing method of such a semiconductor device are provided. A semiconductor device according to the present invention has a plurality of field-effect transistors provided over an insulating layer and a plurality of storage elements provided over the plurality of field-effect transistors. Each of the plurality of field-effect transistors uses a single-crystal semiconductor layer as a channel portion and each of the plurality of storage elements is an element in which a first conductive layer, an organic compound layer, and a second conductive layer are stacked in order.Type: GrantFiled: October 18, 2005Date of Patent: May 3, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroko Abe, Yuji Iwaki, Mikio Yukawa, Shunpei Yamazaki, Yasuyuki Arai, Yasuko Watanabe, Yoshitaka Moriya
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Patent number: 7919815Abstract: Wafer suitable for semiconductor deposition application can be fabricated to have low bow, warp, total thickness variation, taper, and total indicated reading properties. The wafers can be fabricated by cutting a boule to produce rough-cut wafers, lapping the rough-cut wafers, etching the lapped wafers to remove a defect, deformation zone and relieve residual stress, and chemically mechanically polishing the etched wafers to desired finish properties. Etching can be performed by immersion in a heated etching solution comprising sulfuric acid or a mixture of sulfuric and phosphoric acids. A low pH slurry utilized in chemical mechanical polishing of the spinel wafer can comprise ?-Al2O3 and an organic phosphate.Type: GrantFiled: March 1, 2006Date of Patent: April 5, 2011Assignee: Saint-Gobain Ceramics & Plastics, Inc.Inventors: Brahmanandam Tanikella, Elizabeth Thomas, Frank L. Csillag, Palaniappan Chinnakaruppan, Jadwiga Jaroniec, Eric Virey, Robert A. Rizzuto
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Patent number: 7906409Abstract: A device manufacturing method includes a buffer layer forming step of forming a buffer layer on an underlying substrate, a mask pattern forming step of forming, on the buffer layer, a mask pattern which partially covers the buffer layer, a growth step of growing a group III nitride crystal from regions exposed by the mask pattern on the surface of the buffer layer, thereby forming a structure in which a plurality of crystal members are arranged with gaps therebetween so as to partially cover the buffer layer and the mask pattern, a channel forming step of forming a channel, to supply a second etchant for the buffer layer to the buffer layer, by selectively etching the mask pattern using a first etchant for the mask pattern, and a separation step of separating the plurality of crystal members from the underlying substrate and separating the plurality of crystal members from each other by supplying the second etchant to the buffer layer through the gaps and the channel and selectively etching the buffer layer.Type: GrantFiled: March 17, 2009Date of Patent: March 15, 2011Assignee: Canon Kabushiki KaishaInventors: Takafumi Yao, Meoung-Whan Cho
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Patent number: 7880231Abstract: A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.Type: GrantFiled: September 16, 2009Date of Patent: February 1, 2011Assignee: Intel CorporationInventor: Peter L. D. Chang
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Patent number: 7880303Abstract: An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.Type: GrantFiled: February 13, 2007Date of Patent: February 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chih-Hsiang Yao, Wen-Kai Wan, Jye-Yen Cheng
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Patent number: 7863713Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.Type: GrantFiled: December 20, 2006Date of Patent: January 4, 2011Assignees: Tohoku University, Foundation for Advancement of International ScienceInventors: Tadahiro Ohmi, Akinobu Teramoto, Kazufumi Watanabe
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Publication number: 20100270618Abstract: The present invention provides a production method of a semiconductor device, capable of improving surface flatness of a semiconductor chip formed on a semiconductor substrate and thereby suppressing a variation in electrical characteristics of the semiconductor chip transferred onto a substrate with an insulating surface, and further capable of improving production yield.Type: ApplicationFiled: October 14, 2008Publication date: October 28, 2010Inventors: Michiko Takei, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Steven Roy Droes
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Patent number: 7816736Abstract: There is provided a method of removing trap levels and defects, which are caused by stress, from a single crystal silicon thin film formed by an SOI technique. First, a single crystal silicon film is formed by using a typical bonding SOI technique such as Smart-Cut or ELTRAN. Next, the single crystal silicon thin film is patterned to form an island-like silicon layer, and then, a thermal oxidation treatment is carried out in an oxidizing atmosphere containing a halogen element, so that an island-like silicon layer in which the trap levels and the defects are removed is obtained.Type: GrantFiled: October 30, 2007Date of Patent: October 19, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 7800202Abstract: In order to obtain substantially the same operating speed of a p-type MOS transistor and an n-type MOS transistor forming a CMOS circuit, the n-type MOS transistor has a three-dimensional structure having a channel region on both the (100) plane and the (110) plane and the p-type MOS transistor has a planar structure having a channel region only on the (110) plane. Further, both the transistors are substantially equal to each other in the areas of the channel regions and gate insulating films. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other.Type: GrantFiled: November 30, 2006Date of Patent: September 21, 2010Assignees: Tohoku University, Foundation for Advancement of International ScienceInventors: Tadahiro Ohmi, Akinobu Teramoto
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Patent number: 7799599Abstract: Semiconductor-on-diamond devices and methods for making such devices are provided. In one aspect, for example, a method for making a semiconductor-on-diamond substrate is provided, including depositing a conformal amorphous diamond layer on a single crystal Si base layer, thereby forming in situ a single crystal SiC layer therebetween, removing the amorphous diamond layer to expose the SiC layer, and epitaxially depositing a single crystal diamond layer on the SiC layer.Type: GrantFiled: May 31, 2007Date of Patent: September 21, 2010Inventor: Chien-Min Sung
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Patent number: 7745880Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.Type: GrantFiled: October 19, 2005Date of Patent: June 29, 2010Assignee: Oki Semiconductor Co., Ltd.Inventors: Toshiyuki Nakamura, Satoshi Machida, Sachiko Yabe, Takashi Taguchi
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Patent number: 7732867Abstract: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is formed. The single crystal Si substrate 10 is bonded to the quartz substrate 20 having a carbon concentration of 100 ppm or higher, and an external shock is applied near the ion-implanted damage layer 11 to delaminate the Si crystal film along the hydrogen ion implanted boundary 12 of the single crystal Si substrate 10 out of the bonded substrate. Then, the surface of the resultant silicon thin film 13 is polished to remove a damaged portion, so that an SOQ substrate can be fabricated. There can be provided an SOQ substrate highly adaptable to a semiconductor device manufacturing process.Type: GrantFiled: November 2, 2007Date of Patent: June 8, 2010Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
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Patent number: 7714387Abstract: A semiconductor device with a TFT includes a substrate, an island-shaped semiconductor film serving as an active layer of the TFT on or over the substrate, a pair of source/drain regions formed in the semiconductor film, and a channel region formed between the pair of source/drain regions in the semiconductor film. The pair of source/drain regions is thinner than the remainder of the semiconductor film other than the source/drain regions. The thickness difference between the pair of source/drain regions and the remainder of the semiconductor film is in a range from 10 angstrom (?) to 100 angstrom. The total process steps are reduced and the operation characteristic and reliability of the device are improved.Type: GrantFiled: July 6, 2006Date of Patent: May 11, 2010Assignee: NEC LCD Technologies, Ltd.Inventors: Kunihiro Shiota, Hiroshi Okumura
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Patent number: 7691688Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.Type: GrantFiled: June 23, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Meikei Ieong, Alexander Reznicek, Devendra K. Sadana, Leathen Shi, Min Yang
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Patent number: 7663189Abstract: A semiconductor device is created in a doped silicon layer at most one-tenth of a micrometer thick formed on and having an interface with a sapphire substrate. An oppositely doped source region is formed in the silicon layer. A gate electrode is formed above part of the silicon layer. A diffusion layer doped with the same type of impurity as the source region but at a lower concentration is formed in the silicon layer, extending into a first area beneath the gate electrode, functioning as a drain region or as a lightly-doped extension of a more heavily doped drain region. The depth of this diffusion layer is less than the thickness of the silicon layer. This comparatively shallow diffusion depth reduces current leakage by inhibiting the formation of a back channel.Type: GrantFiled: November 29, 2005Date of Patent: February 16, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Koichi Fukuda
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Patent number: 7638805Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.Type: GrantFiled: October 29, 2007Date of Patent: December 29, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani
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Patent number: 7633131Abstract: A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming the semiconductor devices in the top surface of a single-crystal silicon wafer, thinning the silicon wafer to a desired thickness, and then dicing the thinned wafer to form silicon layers of a desired size. The MEMS device can be used to implement a pressure sensor, microphone, temperature sensor, and a joystick.Type: GrantFiled: February 1, 2007Date of Patent: December 15, 2009Assignee: National Semiconductor CorporationInventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
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Patent number: 7622772Abstract: An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate. The insulative substrate can include aluminum oxycarbide. The insulative substrate can exhibit a CTE sufficiently close to a CTE of the semiconductive material layer such that a strain of less than 1% would exist between a 1000 Angstroms thickness of the semiconductive material layer and the insulative substrate. The semiconductive material layer can include monocrystalline silicon. The electronic apparatus can be a silicon-on-insulator integrated circuit. An electronic apparatus fabrication method includes forming an insulative substrate containing an aluminum-based glass and forming a layer containing a semiconductive material over the substrate.Type: GrantFiled: March 29, 2005Date of Patent: November 24, 2009Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 7619282Abstract: There is disclosed a hybrid circuit in which a circuit formed of TFTs in integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.Type: GrantFiled: February 28, 2006Date of Patent: November 17, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto
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Patent number: 7608892Abstract: To reduce the adverse affect that characteristics of end portions of a channel forming region of a semiconductor film have on characteristics of a transistor. A gate electrode is formed over a channel forming region of a semiconductor film over a substrate, with a gate insulating film interposed therebetween. The semiconductor film is disposed in a region inside end portions of the gate insulating film. A side surface of the channel forming region is not in contact with at least the gate insulating film, so there is a space enclosed by the substrate, the side surface of the channel forming region, and the gate insulating film. Further, the side surface of the channel forming region is not necessarily in contact with the gate electrode. There may be a space enclosed by the substrate, the side surface of the channel forming region, the gate insulating film, and the gate electrode.Type: GrantFiled: April 12, 2007Date of Patent: October 27, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Masayuki Sakakura
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Patent number: 7608893Abstract: A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.Type: GrantFiled: February 26, 2008Date of Patent: October 27, 2009Assignee: Freescale Semiconductor, Inc.Inventor: Marius Orlowski
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Patent number: 7598520Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 ?.Type: GrantFiled: June 1, 2007Date of Patent: October 6, 2009Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
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Patent number: 7592671Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.Type: GrantFiled: January 6, 2007Date of Patent: September 22, 2009Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Ghavam Shahidi
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Publication number: 20090218590Abstract: A method of making a thin gallium-nitride (GaN)-based semiconductor structure is provided. According to one embodiment of the invention, the method includes the steps of providing a substrate; sequentially forming one or more semiconductor layers on the substrate; etching a pattern in the one or more semiconductor layers; depositing a dielectrics layer; forming a photoresist on a portion of the dielectrics layer, wherein the portion of the dielectrics layer is deposited on the one or more semiconductor layers; depositing a primer; removing the photoresist layer, wherein the primer on the photoresist is also removed; depositing a superhard material, wherein the superhard material forms in the pattern; and removing the substrate. Accordingly, the superhard material may be selectively deposited in only areas where the superhard material is desired. Vertical GaN-based light emitting devices may then be formed by cutting the semiconductor structure.Type: ApplicationFiled: March 31, 2009Publication date: September 3, 2009Applicant: Hong Kong Applied Science and Technology Research InstituteInventors: Yong Cai, HungShen Chu, Shengmei Zheng, Ka Wah Chan
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Thin film transistor including low resistance conductive thin films and manufacturing method thereof
Patent number: 7576394Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.Type: GrantFiled: February 1, 2007Date of Patent: August 18, 2009Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida -
Patent number: 7573063Abstract: A thin film transistor having an improved gate dielectric layer is disclosed. The gate dielectric layer comprises a poly(4-vinylphenol-co-acrylonitrile) based polymer. The resulting gate dielectric layer has a high dielectric constant and can be crosslinked. Higher gate dielectric layer thicknesses can be used to prevent current leakage while still having a large capacitance for low operating voltages. Methods for producing such gate dielectric layers and/or thin film transistors comprising the same are also disclosed.Type: GrantFiled: May 15, 2008Date of Patent: August 11, 2009Assignee: Xerox CorporationInventors: Ping Liu, Yiliang Wu, Yuning Li, Beng S. Ong
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Patent number: 7564100Abstract: The present invention provides an SOS wafer comprising a non-transparent polysilicon layer provided on a back surface of a sapphire substrate, a silicon nitride layer which protects the polysilicon layer, and a stress relaxing film which cancels stress produced in the silicon nitride layer, wherein the silicon nitride layer and the stress relaxing film are provided on the back surface side.Type: GrantFiled: March 17, 2006Date of Patent: July 21, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Kimiaki Shimokawa
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Patent number: 7544981Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.Type: GrantFiled: March 9, 2007Date of Patent: June 9, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yukio Tanaka, Shou Nagao
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Patent number: 7544552Abstract: A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.Type: GrantFiled: March 23, 2006Date of Patent: June 9, 2009Assignees: Honda Motor Co., Ltd., Shindengen Electric Manufacturing Co., Ltd.Inventors: Ken-ichi Nonaka, Hideki Hashimoto, Seiichi Yokoyama, Kensuke Iwanaga, Yoshimitsu Saito, Hiroaki Iwakuro, Masaaki Shimizu, Yusuke Fukuda, Koichi Nishikawa, Yusuke Maeyama
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Patent number: 7528447Abstract: A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.Type: GrantFiled: April 5, 2006Date of Patent: May 5, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Toshiyuki Enda, Hiroyoshi Tanimoto, Naoki Kusunoki, Nobutoshi Aoki, Fumitaka Arai, Riichiro Shirota
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Patent number: 7528448Abstract: The invention relates to thin film transistors comprising novel dielectric layers and novel electrodes comprising metal compositions that can be provided by a dry thermal transfer process.Type: GrantFiled: July 17, 2006Date of Patent: May 5, 2009Assignee: E.I. du Pont de Nemours and CompanyInventors: Richard Kevin Bailey, Graciela Beatriz Blanchet, John W. Catron, Jr., Reid John Chesterfield, Howard David Glicksman, Marc B. Goldfinger, Gary Delmar Jaycox, Lynda Kaye Johnson, Roupen Leon Keusseyan, Irina Malajovich, Hong Meng, Jeffrey Scott Meth, Geoffrey Nunes, Gerard O'Neil, Kenneth George Sharp, Feng Gao
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Patent number: 7525157Abstract: A semiconductor device includes: an insulating layer selectively formed on the semiconductor base material; a first semiconductor layer made of single-crystal and formed on the semiconductor base material that is exposed below the insulating layer, the first semiconductor layer having an opening that exposes the semiconductor base material; an opening plane exposing a side face of the first semiconductor layer and provided below the support film, the second semiconductor layer and the first semiconductor layer by using the mask pattern as a mask; a portion defining a hollow part between the second semiconductor layer and the semiconductor base material; a first insulating film formed in the hollow part; and a second insulating film formed above the semiconductor base material on which the first insulating film is formed.Type: GrantFiled: March 1, 2007Date of Patent: April 28, 2009Assignee: Seiko Epson CorporationInventor: Tatsushi Kato
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Patent number: 7524710Abstract: A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.Type: GrantFiled: June 6, 2008Date of Patent: April 28, 2009Assignee: Peregrine Semiconductor CorporationInventors: Anthony M. Miscione, George Imthurn, Eugene F. Lyons, Michael A. Stuber