Abstract: An integrated circuit for intermediate impedance matching and stabilization of high power devices is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of impedance matching and stability circuits to be placed on the same substrate as the active device. Additionally, by using the manifolds of the active to form plates of a capacitor, an impedance matching network of series inductance and shunt capacitor can be compactly fabricated for increasing the output impedance to intermediate levels. The manifolds of the active device are also used to form capacitors to provide stability to high power active devices.

Abstract: A method for making an integrated circuit includes forming spaced-apart trenches on a surface of a single crystal silicon substrate, lining the trenches with a silicon oxide layer, forming a first polysilicon layer over the silicon oxide layer, forming a second polysilicon layer over the first polysilicon layer, and removing a thickness of the single crystal silicon substrate to expose tubs of single crystal silicon in the second polysilicon layer.

Abstract: A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polysilicon. An electrical device can be formed to overlie the body contact. Thus, no additional circuitry or conductive path is required to electrically connect a body contact and a device region. Also, the body contact provides a predictable electrical characteristics without sacrificing the benefits attained from using the SOI substrate and conservation surface space on the semiconductor die.

Abstract: An insulated gate field effect transistor is disclosed. The transistor includes a semi-insulating silicon carbide substrate, an epitaxial layer of silicon carbide layer adjacent the semi-insulating substrate for providing a drift region having a first conductivity type, and source and drain regions in the epitaxial layer having the same conductivity type as the drift region. A channel region is in the epitaxial layer, has portions between the source and the drain regions, and has the opposite conductivity type from the source and drain regions. The transistor includes contacts to the epitaxial layer for the source, drain and channel regions, an insulating layer over the channel region of the epitaxial layer, and a gate contact adjacent the insulating layer and the channel region.

Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.

Abstract: A composite semiconductor including silicon and compound semiconductor, and having a metal semiconductor field effect transistor (MESFET) integrated at least partially with the silicon and at least partially with the GaAs having a silicon back gate is provided. The back gate for the MESFET may be formed by doping a region of the monocrystalline silicon substrate before forming the transistor. In a structure according the invention, integrated circuits may be provided to match the threshold voltages of one MESFET to another, improve the transconductance of a MESFET, and improve the switching speed of a MESFET.

Abstract: A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

Abstract: A semiconductor device is provided having angled dopant implantation and vertical trenches in the silicon on insulator substrate adjacent to the sides of a semiconductor gate. A second dopant implantation is in the exposed the source/drain junctions. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract: A method and structure for conductively coupling electrical structures to a semiconductor device located under a silicon on insulator (SOI) layer. The SOI layer is formed on a bulk semiconductor substrate. A trench structure through the SOI layer is formed, wherein an end of the trench structure interfaces with the bulk semiconductor substrate. A semiconductor device is formed in the bulk semiconductor substrate, wherein the semiconductor device includes P+ and N+ diffusions. Conductive plugs are formed through the trench structure such that the conductive plugs are self-aligned with, and in conductive contact with, the diffusions. The semiconductor device in the bulk semiconductor substrate may include an electrostatic discharge device (ESD). The bulk semiconductor substrate, which has a high thermal conductivity, serves as an effective medium for dissipating heat generated by the ESD.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: A method of forming a polysilicon thin film transistor. An amorphous silicon channel layer is formed over an insulating substrate. An active region is patterned out in the amorphous silicon channel layer. An oxide layer and a gate electrode are sequentially formed over the amorphous silicon channel layer. A lightly doped source/drain region is formed in the amorphous silicon channel layer and then a spacer is formed over the gate electrode. A source/drain region is formed in the amorphous silicon channel layer. A portion of the oxide layer above the source/drain region is removed. An isolation spacer is formed on the sidewalls of the spacer. A self-aligned silicide layer is formed at the top section of the spacer and the source/drain region. Finally, a metal-induced lateral crystallization process is conducted to transform the amorphous silicon channel layer into a lateral-crystallization-polysilicon channel layer.

Abstract: An improved silicon on sapphire structure and/or device has one or more buffer layers. In a first preferred embodiment, the buffer layer is layer of silicon oxide material that prevents the stress induced defects in the silicon layer. In an alternative embodiment, the buffer layer comprises two layers. A first silicon oxide layer attached to the silicon to insure a perfect interface between the silicon. A second silicon oxide layer then is attached to the sapphire layer. The first and second silicon oxide layers are then attached, e.g., by a wafer bonding technique. This structure has no conductive paths beneath the oxide insulator(s) and therefore enables improved performance in radio frequency applications.

Abstract: The present invention provides semiconductor structures and methods for forming semiconductor structures which include monocrystalline oxide films exhibiting both high dielectric constants and low leakage current densities. In accordance with various aspects of the invention, a semiconductor structure includes a monocrystalline semiconductor substrate and one or more stoichiometrically graduated monocrystalline oxide layers. The stoichiometrically graduated monocrystalline oxide layer may include a perovskite material, such as an alkaline-earth metal titanate. Semiconductor devices fabricated in accordance with aspects of the present invention exhibit a high dielectric constant as well as a reduced leakage current density.

Abstract: Disclosed are an SOI device having no edge leakage current and a method of fabricating the same. The SOI device comprises: an SOI substrate of a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; an oxide layer formed to be in contact with the buried oxide layer at the semiconductor layer portion corresponding to a field region so that an active region is defined; a gate electrode pattern having a gate oxide layer, the gate oxide layer only formed on the active region; a source region and a drain region formed inside the active region of the semiconductor layer of both sides of the gate electrode pattern; and a gate electrode line formed on the gate electrode pattern and on the field region so as to interconnect the gate electrode patterns of the respective active regions arranged in a line.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a complaint substrate includes first growing a monocrystalline binary metal oxide material layer (14) on a substrate (12). The binary metal oxide material layer (14) is lattice matched to both the underlying substrate (12) and the overlying monocrystalline material layer (16).

Abstract: A high quality semiconductor structure includes a monocrystalline substrate and a perovskite stack overlying the substrate. The perovskite stack may be formed of a first accommodating layer formed of a first perovskite oxide material having a first lattice constant. A second accommodating layer is formed on the first accommodating layer. The second accommodating layer is formed of a second perovskite oxide material having a second lattice constant which is different from the first lattice constant of the first accommodating layer. A monocrystalline material layer is formed overlying the second accommodating layer. A strain is effected at the interface between the perovskite stack and the substrate, at the interface between the perovskite stack and the monocrystalline material layer and/or at the interface between the first accommodating layer and the second accommodating layer. The strain reduces defects in the monocrystalline material layer and results in reduced Schottky leakage current.

Abstract: A SOI semiconductor device comprises: a SOI substrate in which a buried dielectric film and a surface semiconductor layer are laminated; at least one well formed in the surface semiconductor layer; and at least one transistor which is formed in the well and has a channel region and source/drain regions in the surface semiconductor layer, wherein the well is completely isolated in the surface semiconductor layer and has a well-contact for applying a bias voltage to the well, the transistor is isolated by a device isolation film formed in a surface of the surface semiconductor layer, the channel region is partially depleted, and the surface semiconductor layer under the source/drain regions is fully depleted.

Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).

Abstract: A high quality semiconductor device comprising at least a semiconductor film having a microcrystal structure is disclosed, wherein said semiconductor film has a lattice distortion therein and comprises crystal grains at an average diameter of 30 Å to 4 &mgr;m as viewed from the upper surface of said semiconductor film and contains oxygen impurity and concentration of said oxygen impurity is not higher than 7×1019 atoms.cm−3 at an inside position of said semiconductor film. Also is disclosed a method for fabricating semiconductor devices mentioned hereinbefore, which comprises depositing an amorphous semiconductor film containing oxygen impurity at a concentration not higher than 7×1019 atoms.cm−3 by sputtering from a semiconductor target containing oxygen impurity at a concentration not higher than 5×1018 atoms.

Abstract: A semiconductor device has a nMOS transistor and a pMOS transistor formed on a substrate made of glass or plastics with buffer layer in between. The nMOS transistor has a conduction region made of polycrystal Si and a gate electrode associated therewith, while the pMOS transistor has a conduction region made of polycrystal Si and a gate electrode associated therewith. The gate electrodes are made of p-type SiGe or P-type Ge. The relation between the gate length L or the gate width W of the gate electrodes and the average grain size d of the conduction regions associated therewith is given by: L≦d, W>d. The semiconductor device exhibits the small range of variations in characteristics even if the gate length is reduced. Also, speed-up and voltage reduction can be achieved.

Abstract: A semiconductor device comprises an embedded insulation layer 101 formed on a semiconductor substrate 100, plural power semiconductor elements 2, 3 formed on a semiconductor substrate 100 on the embedded insulation layer, a trench 4 formed on the semiconductor substrate and isolating between the power semiconductor elements, and an isolator 5 insulating and driving control electrodes of the power semiconductor elements, and the power semiconductor elements 2, 3 such as transistors can be used, being connected each other in series.

Abstract: A logic circuit is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The logic circuit utilizes both SOI field effect transistors (FETs) and SOI diodes to provide for reduced size of the logic circuit and reduced power consumption when the logic circuit is in operation. A method of performing certain logic function is also provided.

Abstract: Provided is a semiconductor device capable of reducing its size, increasing its packing density, preventing a deterioration in circuit characteristics, and increasing flexibility in wiring design. The semiconductor device comprises a chip core region and an IO region on a semiconductor substrate. In the chip core region, a large number of circuits are arranged. In the IO region, a ring wiring of a laminated structure with a top layer corresponding to a first potential, and a bottom layer corresponding to a second potential is provided. The top layer of the ring wiring and the circuits are connected via first connecting lines, and the bottom layer and the circuits are connected via second connecting lines, so electric power is supplied to the circuits.

Abstract: A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate s formed during the BEOL process. The transistor may by a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

Abstract: In a thin-film transistor of multi-gate structure, the width of a channel forming region 108 closest to a drain region 102 is made the narrowest. This prevents a transistor structure closest to the drain region from first deteriorating. Further, the channel length at the vicinity of a center of an active layer is intentionally widened, so that the amount of current flowing through the vicinity of the center of the active layer is decreased and the deteriorating phenomenon due to heat accumulation is prevented. Therefore, a semiconductor device with a high reliability is realized.

Abstract: A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region.

Abstract: A III nitride buffer film including at least Al element and having a screw-type dislocation density of 1×108/cm2 or below is formed on a base made of a sapphire single crystal, etc., to fabricate an epitaxial base substrate. Then, a III nitride underfilm is formed on the III nitride buffer film, to fabricate an epitaxial substrate.

Abstract: There is provided a semiconductor device that has a reduced parasitic capacitance bonding pad structure using a silicon-on-insulator substrate. In the semiconductor device according to the present invention, a pn junction is formed by forming a semiconductor region, that has a different conductivity type from the active layer, in an active layer below a bonding pad to generate a depletion layer. Thus, a parasitic capacitance connected to the bonding pad can be reduced by a capacitance that is formed by the generation of this depletion layer. Also, a leakage current from the bonding pad can be suppressed by the generation of the pn junction.

Abstract: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first oxidation region is formed in the first semiconductor layer below the source region and a second oxidation region is formed in the first semiconductor layer below the drain region. Both the first oxidation and second oxidation regions are contiguous with the second insulating layer.

Abstract: A SOI DRAM unit comprising a MOS transistor and an improved SOI substrate having a back-gate control. The SOI substrate includes a first insulating layer, a first semiconductor layer having a first conductivity type, a second insulating layer, and a second semiconductor layer having a first conductivity type formed on a substrate, respectively. The MOS transistor includes a gate formed on the second semiconductor layer and a source and drain region, having a second conductivity type, formed on either side of the gate in the second semiconductor layer, wherein the source and the drain electrically connects to a bit line and a capacitor, respectively. A first doped region having a second conductivity type is formed in the first semiconductor layer below the source region and a second doped region having a second conductivity type is formed in the first semiconductor layer below the drain region. Both the first doped region and the second doped region are contiguous with the second insulating layer.

Abstract: An FET device comprises a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each edges, the edges of the FET diffusion regions being separated by the channel region; and a body contact region of the first conductivity type extending continuously from the channel region. The first conductivity type material in the body contact region is thinner than the first conductivity type material in the channel region. The FET also includes a second dielectric layer formed on the body contact region.

Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.

Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

Abstract: A method for making a self-aligned FET with an electrically active mask comprises the steps of forming a semiconductor layer on an insulating substrate, forming an electrically nonconductive oxide layer on the semiconductor layer, forming an electrically conductive metal layer on the oxide layer, patterning the metal layer and the oxide layer to form an electrically active gate on semiconductor layer, introducing dopants into the semiconductor layer to form a source region and a drain region masked by the metal gate, and illuminating the source and the drain regions with a pulsed excimer laser having a wavelength from about 150 nm to 350 nm to anneal the source region and the drain region.

Abstract: A substrate for forming a semiconducting layeris provided to grow the semiconducting layer on a major surface thereof, wherein the substrate comprises a single crystal of a chemical formula of XB2 where X contains one of Ti and Zr and the major surface may preferably be substantially parallel to plane (0001) of the single crystal because the plane (0001) of the boride substrate is highly coherent to the lattices of GaN and AlN layers grown eptaxially on the substrate. The single crystal of the substrate may be a solid solution containing impurities of not more than 5%, wherein at least one of the impurities is one selected from Cr, Hf, V, Ta and Nb. Further, a semiconductor device includes the substrate of a single crystal of a chemical formula of XB2 and at least one semiconducting layer which is grown epitaxially on the substrate, the semiconducting layer including a nitride semiconductor of a chemical formula of ZN where Z is one of gallium, aluminum and indium and boron.

Abstract: There is disclosed a method of fabricating a semiconductor device having excellent characteristics. The device comprises a substrate having an insulating surface. A hydrogen-rich region is formed inside the substrate by ion doping. Thermal processing is performed at 300 to 450° C. to thermally diffuse hydrogen ions. Thus, dangling bonds and defect levels in an active layer are compensated. Since the hydrogenation from inside the semiconductor device is enabled in this way, hydrogen termination can be performed at a high efficiency.

Abstract: The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Abstract: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer.

Abstract: A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Abstract: A coplanar gate-source-drain “Poly Thin Film Transistor” (hereinafter referred as Poly-TFT) and the method for fabricating the same are provided according to the present invention. The Poly-TFT includes a metal layer formed upon a transparent substrate. Wherein the metal layer includes the respective metal wires of gate, drain and source while the gaps are formed in between the metal wires of source and gate as well as in between the metal wires of drain and gate. The Poly-TFT further includes an insulating layer to cover the metal wire of gate, and includes a layer of polycrystalline semiconductor across and upon the insulating layer with both ends contacting the metal wires of drain and source respectively. Meanwhile, the areas on the layer of polycrystalline semiconductor in contact with the metal wires of drain and source are doped with the impurity ions of high concentration.

Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.

Abstract: A SOI field effect transistor structure providing ESD protection. The structure has a source, a drain, a body, and a gate. The gate is formed from a thick oxide layer and a metal contact. The gate is formed during the BEOL process. The transistor may be a p-type transistor or an n-type transistor. The transistor may have its drain tied to either the gate, the body, or both the gate and body. When used as a protection device, the drain is tied to a signal pad and the source is tied to a potential reference.

Abstract: FS-isolated fields (10a, 10b). LOCOS-isolated fields (11c, 11d). FS-isolated fields (10e, 10f), LOCOS-isolated field (11g, 11h) and FS-isolated field (10i) are arranged in this order. Thus, a master layout can he provided, where SOI transistors having bodies to be supplied with fixed potential and those having bodies not to be supplied with fixed potential are mixed.

Abstract: A method of manufacturing a polycrystalline silicon film having a particular field effect mobility is disclosed. A first polycrystalline silicon film is formed on a transparent insulation substrate. The surface of the silicon film is oxidized, and an amorphous silicon film is formed on the first polycrystalline silicon film and oxide layer. The amorphous silicon film is subjected to a solid phase growth process to be converted to a second polycrystalline silicon film. The field effect mobility of the second polycrystalline silicon film can be adjusted to a desired value by controlling the relative thicknesses of the first and second polycrystalline silicon films.

Abstract: The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.

Abstract: A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Abstract: A thin film transistor and a method for fabricating the same in which a self alignment method is used to form an offset area and source and drain electrodes are disclosed, the TFT including a substrate; a trench formed in the substrate; an active layer formed on the substrate and on the trench; a gate insulating film formed on the active layer; a gate electrtode formed on the gate insulating film on at least one side of the trench; a source region formed in the active layer on a bottom side of the trench; and drain regions formed in the active layer on the substrate to be isolated form the gate electrode.

Abstract: A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.