Particular Barrier Material Patents (Class 257/35)
  • Publication number: 20020084453
    Abstract: A hybrid oxide heterostructure device is disclosed. The device includes a substrate, and formed monolithically on the substrate, by atomic layer-by-layer molecular-beam epitaxy, successive metal oxide layers forming a high-temperature superconducting (HTS) structure and a multi-layer magnetic memory/storage structure. The HTS structure includes one or more HTS metal oxide layers formed on the substrate, and electrical contacts formed on the one or more HTS layers. The magnetic-memory structure includes one or more metal oxide magnetic layers formed monolithically on, below, or between the layer(s) of the HTS device, and having electrical contacts formed on one or more of the magnetic layers. Application of current or voltage to an HTS structure, under conditions effective to establish a superconducting current in the HTS structure, is effective to alter read or write characteristics of the memory-storage structure.
    Type: Application
    Filed: September 27, 2001
    Publication date: July 4, 2002
    Inventor: Ivan Bozovic
  • Patent number: 6344659
    Abstract: The present invention relates on an interferometer arrangement comprising a source electrode and a drain electrode, a base electrode to which the source electrode and the drain electrode are connected through tunnel barriers, the base electrode thus forming a double barrier quantum well, and first and second superconducting gate electrodes to control the source-drain current. The base electrode comprises a ferromagnetic material enabling resonant tunneling of source-drain electrons when there are bound states within the quantum well structure matching the energy of said source-drain electrons. The invention also relates to a logical element comprising such an interferometer arrangement and to a method of controlling the conductance of an interferometer.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: February 5, 2002
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Zdravko Ivanov, Robert Shekhter, Anatoli Kadiqrobov, Tord Claeson, Mats Jonson, Erland Wikborg
  • Patent number: 6188919
    Abstract: A SNS Josephson junction (10) is provided for use in a superconducting integrated circuit. The SNS junction (10) includes a first high temperature superconducting (HTS) layer (14) deposited and patterned on a substrate (18), such that the first HTS layer (14) is selectively removed to expose a top surface of the substrate (18) as well as to form an angular side surface (22) on the first HTS layer (14) adjacent to the exposed top surface of the substrate (18). Ion implantation is used to form a junction region (12) having non-superconducting properties along the angular side surface (22) of the first HTS layer (14). A second HTS layer (16) is then deposited and patterned over at least a portion of the first HTS layer (14) and the exposed top surface of the substrate (18), thereby forming a SNS Josephson junction.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: February 13, 2001
    Assignee: TRW Inc.
    Inventors: John R. LaGraff, James M. Murduck, Hugo W-K. Chan
  • Patent number: 6157044
    Abstract: A tunnel junction type Josephson device includes a pair of superconductor layers formed of a compound oxide superconductor material and an insulator layer formed between the pair of superconductor layers. The insulator layer is formed of a compound oxide which is composed of the same constituent elements as those of the compound oxide superconductor material of the superconductor layers but with an atomic ratio which does not present a superconductivity characteristics. In addition, the superconductor layers and the insulator layer are continuously formed while supplying oxygen.
    Type: Grant
    Filed: March 10, 1993
    Date of Patent: December 5, 2000
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hidenori Nakanishi, Saburo Tanaka, Hideo Itozaki, Shuji Yazu
  • Patent number: 6087687
    Abstract: A semiconductor device is provided, which is readily and correctly designed even when the semiconductor device is further miniaturized. This device includes a semiconductor substrate, a source region and a drain region formed to be apart from each other in the substrate, a gate insulator formed on a main surface of the substrate, and a gate electrode formed on the gate insulator. The gate insulator includes a ferroelectric region and a dielectric region located in a same level as that of the ferroelectric region. The ferroelectric region is contacted with the main surface of the substrate and the gate electrode. The dielectric region is contacted with the main surface of the substrate and the ferroelectric region. The whole bottom of the ferroelectric region is contacted with the main surface of the substrate in such a way that no overlap exists between the ferroelectric region and the dielectric region.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: July 11, 2000
    Assignee: NEC Corporation
    Inventor: Yuukoh Katoh
  • Patent number: 6051846
    Abstract: A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.
    Type: Grant
    Filed: April 1, 1993
    Date of Patent: April 18, 2000
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael J. Burns, Paul R. de la Houssaye, Graham A. Garcia, Stephen D. Russell, Stanley R. Clayton, Andrew T. Barfknecht
  • Patent number: 6011981
    Abstract: An oxide superconducting multilayered thin film structure having a laminated layer structure of oxide superconductor thin film layers and non-superconductor thin film layers constituted by a combination of material groups for making strain free interfaces among both thin film layers. For example, an oxide superconductor multilayered film constituted by a laminated layer structure where thin films of an oxide superconductor represented by the chemical formula of M'Ba.sub.2 Cu.sub.3 O.sub.7-.delta. (M'; a rare earth element of Nd, Sm, Eu or the like or an alloy of these, .delta.; oxygen depletion amount) and thin films of an oxide represented by the chemical formula of M*Ba.sub.2 Cu.sub.3 O.sub.7-.delta. (M*; an element of Pr, Sc or the like or an alloy of these, .delta.; oxygen depletion amount) are alternately stacked. The oxide thin films are thin films fabricated by a pulsed laser deposition process or a sputtering process. A Josephson device can be provided by using the multilayered film.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: January 4, 2000
    Assignee: International Superconductivity Technology Center
    Inventors: Gustavo Alvarez, Furen Wang, Jian-Guo Wen, Naoki Koshizuka, Youichi Enomoto, Tadashi Utagawa, Shoji Tanaka
  • Patent number: 5965900
    Abstract: The invention relates to a detector cell comprising tunnel-effect superconductive devices organized in a two-dimensional array and placed on a common substrate, each superconductive device comprising a tunnel-effect superconductive junction and being electrically connected to a bottom connection area and to a top connection area. The superconductive devices are separated from one another by trenches extending down to and including the bottom connection area and defining individual bottom connection areas disposed between each of said junctions and the substrate. At least one individual bottom connection area is electrically connected to at least one bottom connection area of an adjacent superconductive device by a localized bridge region.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: October 12, 1999
    Assignee: Agence Spatiale Europeenne
    Inventors: Anthony Peacock, Robert Venn
  • Patent number: 5910662
    Abstract: A semiconductor substrate comprising a single crystal substrate base such a silicon and a superconducting thin film layer deposited on said substrate base and composed of compound oxide such as Ln.sub.1 Ba.sub.2 Cu.sub.3 O.sub.7-.delta.. (Ln is lanthanide).
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: June 8, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideo Itozaki, Keizo Harada, Naoji Fujimori, Shuji Yazu, Tetsuji Jodai
  • Patent number: 5892243
    Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c, superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c, superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c, superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ionmilling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: April 6, 1999
    Assignee: TRW Inc.
    Inventor: Hugo W. Chan
  • Patent number: 5885937
    Abstract: This invention provides a superconducting tunnel junction element showing satisfactory Josephson effect. The element includes a Bi-based layered compound such as Bi.sub.2 Sr.sub.2 (Ca.sub.0.6 Y.sub.0.4)Cu.sub.2 O.sub.8, Bi.sub.2 Sr.sub.2 Cu.sub.2 O.sub.6 and Bi.sub.2 Sr.sub.2 CaCu.sub.2 O.sub.8 as the barrier layer between the superconducting oxide electrodes. The structural matching of the superconducting oxide with the Bi-based compound is supposed to be good. Some kinds of Cu-based superconducting oxides such as YSr.sub.2 Cu.sub.2.7 Re.sub.0.3 O.sub.7, Sr.sub.2 CaCu.sub.2 O.sub.6 and (La.sub.0.9 Sr.sub.0.1).sub.2 CuO.sub.4 are used for the electrodes to obtain a Josephson element which can work at a high temperature. When using the superconducting oxides including Ba such as YBa.sub.2 Cu.sub.3 O.sub.7 for the electrode, forming a thin film between the electrode and the barrier is better to prevent Ba from reacting with Bi in the barrier layer.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: March 23, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Adachi, Masahiro Sakai, Akihiro Odagawa, Kentaro Setsune
  • Patent number: 5831279
    Abstract: A device with weak links (Josephson junctions) in a superconducting film has two single crystals connected through an interconnecting arrangement that may have one or more sublayers. At least two grain boundaries or at least one barrier are/is formed in the substrate.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: November 3, 1998
    Assignee: Telefonktiebolaget LM Ericsson
    Inventors: Erland Wikborg, Evgeni Stepantsov, Zdravko Ivanov, Tord Claeson
  • Patent number: 5821557
    Abstract: A Josephson junction includes a substrate, a first superconducting layer, a second superconducting layer transversely overlaid on the first layer with an insulating layer interposed therebetween, the insulating layer is an oxide or a nitride of the superconducting material, and the insulating layer including a low oxygen- or nitrogen-concentrated area in contact with each of the first and second layers. A process for fabricating the Josephson junction includes the steps of preparing a substrate, forming a first superconducting layer, forming a second superconducting layer transversely on the first layer with an insulating layer interposed therebetween wherein the insulating layer is an oxide or nitride of the superconducting material, and injecting ion beams into the insulating layer so as to form low oxygen- or nitrogen-concentrated area linking the first and second layers.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: October 13, 1998
    Assignee: Shimadzu Corporation
    Inventors: Shinji Nagamachi, Masahiro Ueda, Kei Shinada, Mitsuyoshi Yoshii
  • Patent number: 5804835
    Abstract: This is an invention of a superconductive device that is equipped with a first superconductive electrode, a second superconductive electrode and a junction that is made of a superconductive material that connects these superconductive electrodes, wherein there are 2-terminal or 3-terminal superconductive devices that use a junction that is in a superconductive state that is weaker than the first and the second superconductive electrodes or in a normal conductive state that is near the superconductive state. The differences between the critical current, the critical temperature, the pair potential and the carrier densities of the first and the second superconductive electrodes and the junction are used as a means of putting the junction in the states mentioned above. Based on the methods mentioned above, a superconductive device which has few pattern rule restrictions and which is easy to fabricate can be offered.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 8, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Taketomi Kamikawa, Eiji Natori, Setsuya Iwashita, Tatsuya Shimoda
  • Patent number: 5793056
    Abstract: A technique for defining the active area of a high-T.sub.c superconductor Josephson junction uses an epitaxial slotted insulator patterned over the edge of the superconductor thin film-insulator bilayer. The superconductor/normal-metal/superconductor edge junction formed between the slotted insulator has a small active area. The counter electrode provided as an interconnect of the junction can therefore be wider than the active area of the edge junction since it can overlap onto the patterned slotted insulator. The use of the slotted insulator enables fabrication of junctions having resistances and critical currents in the desired range for high-T.sub.c superconductor circuits while enabling the use of wide, low inductance interconnects.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: August 11, 1998
    Assignee: Northrop Grumman Corporation
    Inventors: Martin G. Forrester, Brian D. Hunt
  • Patent number: 5757243
    Abstract: An effective high frequency oscillator is made of a plurality of Josephson devices. A high frequency converter as a high frequency circuit is made of the high frequency oscillator, nonlinear superconductor devices, and transmission line. Josephson devices are connected in parallel to make a superconductor module. Then superconductive modules are connected in series for high frequency via a phase locking circuit such as a thin film type capacitor to make the high frequency oscillator. Consequently, the high frequency oscillator is used as a local oscillator for a frequency converter. The high frequency system comprises a high frequency package housing a high frequency circuit, a cooling unit including a low temperature stage in thermal contact with the high frequency package, and a shielding case for housing the high frequency circuit and the low temperature stage. The high frequency system of the present invention provides a small-sized and power-saving high frequency circuit having operational stability.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: May 26, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Mizuno, Akira Enokihara, Hidetaka Higashino, Kentaro Setsune
  • Patent number: 5753935
    Abstract: In a radiation detection device using superconducting tunnel junctions, the increase in electric capacitance and the decrease in electric resistance due to the increase in junction area for improvement of the detection efficiency are largely repressed by the invention. The junctions are connected in series. The number of the series-connected junctions is settled in the range of larger than 0.05 (SC.sub.o /C')0.5 and smaller than 20 (SC.sub.o /C')0.5 or 10SCo/C', whichever is larger, where S is the total area of the junctions, cm.sup.2, C.sub.o is the electric capacitance per unit area of the junctions, F/cm.sup.2, and C' is the electric capacitance connected to the device in parallel so as to transfer and amplify the signals from the device, F.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: May 19, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Masahiko Kurakado, Atsuki Matsumura, Tooru Takahashi
  • Patent number: 5736488
    Abstract: This invention relates to multilayered superconductive composites, particularly to composites based on thallium-containing superconducting oxides, and their process of manufacture.
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: April 7, 1998
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Dean Willett Face, Kirsten Elizabeth Myers
  • Patent number: 5696392
    Abstract: A conductor suitable for use in oxide-based electronic devices and circuits is disclosed. Metallic oxides having the general composition AMO.sub.3, where A is a rare or alkaline earth or an alloy of rare or alkaline earth elements, and M is a transition metal, exhibit metallic behavior and are compatible with high temperature ceramic processing. Other useful metallic oxides have compositions (A.sub.1-x A'.sub.x)A".sub.2 (M.sub.1-y M'.sub.y).sub.3 O.sub.7-.delta. or (A.sub.1-x A'.sub.x).sub.m (M.sub.1-y M'.sub.y).sub.n O.sub.2m+n, where 0.ltoreq.x, y.ltoreq.1 and 0.5.ltoreq.m, n.ltoreq.3, A and A' are rare or alkaline earths, or alloys of rare or alkaline earths, A' and A" are alkaline earth elements, alloys of alkaline earth elements, rare earth elements, alloys of rare earth elements, or alloys of alkaline earth and rare earth elements, and M and M' are transition metal elements or alloys of transition metal elements.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: December 9, 1997
    Assignee: Conductus, Inc.
    Inventors: Kookrin Char, Theodore H. Geballe, Brian H. Moeckly
  • Patent number: 5665980
    Abstract: A method of fabricating a superconducting quantum interference device (DC-SQUID) constructed from short weak links with untrafine wires. The method comprises the following steps: successive forming a niobium nitride film and a silicon nitride film on a substrate; oblique etching of the niobium nitride film and said silicon nitride film with respect to the substrate by a reactive ion etching process using a mixture of oxygen and CF.sub.4 gases to form an olique edge; and successive forming a barrier thin film and a counterelectrode of niobium on the said edge. The short weak links wire fabricated by field evaporation technique. The counterelectrode material were field-evaporated and formed the conductive paths in the pinholes in the insulating thin film.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: September 9, 1997
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yoshio Onuma, Katsuyoshi Hamasaki
  • Patent number: 5635730
    Abstract: A superconducting oxide thin film device is composed of a LaAlO.sub.3 substrate and a YBCO thin film with a BaCeO.sub.3 buffer layer disposed between the two. The adhesion between the film and the substrate is increased by the presence of the buffer layer. The buffer layer also inhibits peeling of the film from the substrate and diffusion of Ba from the film into the substrate.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 3, 1997
    Assignee: Advanced Mobile Telecommunication Technology Inc.
    Inventor: Nobuyoshi Sakakibara
  • Patent number: 5629267
    Abstract: A superconducting element is disclosed which comprises a lower superconducting layer, an upper superconducting layer, and an intermediate layer interposed between the lower and upper superconducting layers. The lower and upper superconducting layers are both form of a superconducting cuprate. The intermediate layer is formed of a layered cuprate containing in the crystal structure thereof multiple fluorite blocks represented by the formula:[B]AE.sub.2 (RE1.sub.1-y RE2.sub.y).sub.m+1 Cu.sub.2 O.sub.z(wherein [B] stands for a block layer, AE for an alkaline earth element, RE1 for at least one element selected from the group consisting of lanthanide elements and actinoid elements which form ions of valency of larger than 3, RE2 for at least one element selected from the group consisting of lanthanide elements which form ions of valency of 3 and yttrium, m for a number satisfying the expression m.gtoreq.2, y for a number satisfying the expression 0.ltoreq.y<1, and z for the oxygen content).
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: May 13, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sumio Ikegawa, Tadao Miura
  • Patent number: 5627139
    Abstract: A HTSC Josephson device wherein the barrier layer is a cubic, conductive material.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: May 6, 1997
    Assignee: The Regents of the University of California
    Inventors: David K. Chin, Theodore Van Duzer
  • Patent number: 5600172
    Abstract: A surface of a thin film superconductor element is coated with a layer containing pre-selected dye, or multiple dyes, alone or in combination with intermediate reflective coatings (best mode), which, when maintained near T.sub.c, upon exposure to a selected frequency of light acts as a narrow bandwidth absorber to change the resistive property of the underlying superconductor following energy transfer from the dye to the superconductor. The resistance change is electronically detectable to function as a wavelength selective high speed optoelectronic switch or sensor element.
    Type: Grant
    Filed: November 3, 1994
    Date of Patent: February 4, 1997
    Assignee: Electric Power Research Institute
    Inventors: John T. McDevitt, David C. Jurbergs
  • Patent number: 5596206
    Abstract: A new type of superconducting device is disclosed. The device embodies a superconducting ceramic film as an active part. A control electrode is provided on the superconducting film in which a passing current is controlled by applying a voltage on an intermediate portion of the film.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: January 21, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5593950
    Abstract: A lattice matching device includes a substrate having thereon monocrystal regions having different lattice mismatches with respect to a LnBa.sub.2 Cu.sub.3 O.sub.x superconductor. A superconducting thin film is formed on the substrate, which film consists essentially of a superconductor of LnBa.sub.2 Cu.sub.3 O.sub.x wherein Ln represents yttrium or a lanthanide, and 6<x<7. The first and second superconducting thin film portions have different axes of orientation perpendicular to a main surface of the substrate, and arranged in contact with each other or at a distance which allows transmission of electron pairs from one to another.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: January 14, 1997
    Assignee: Nippon Telegraph & Telephone Corporation
    Inventors: Masashi Mukaida, Shintaro Miyazawa, Junya Kobayashi
  • Patent number: 5589696
    Abstract: A tunnel transistor comprises a semiconductor film (27) between a gate isolating film (17) and parts of first (13) and second (15) semiconductor layers which are formed in a substrate (11) to serve as source and drain regions with a spacer region left therebetween and covered with the semiconductor film. The gate isolating film is over the part of the first semiconductor layer and is made of either an insulating material or a semiconductor material, each of which materials should have a wider forbidden bandwidth than a semiconductor material of the semiconductor film, such as silicon dioxide, silicon nitride, or aluminium nitride, or gallium phosphide for silicon, or AlGaAs fox gallium arsenide. A source electrode is formed on an uncovered area of the first semiconductor layer. The semiconductor film forms a tunnel junction with the first semiconductor layer and an ohmic junction with the second semiconductor layer, which junction may be either a homojunction or a heterojunction.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: December 31, 1996
    Assignee: NEC Corporation
    Inventor: Toshio Baba
  • Patent number: 5545612
    Abstract: A superconductor element includes a first layer of an oxide superconductor, a second layer of an insulator, semiconductor, or metal, and an interlayer interposed between the first and second layers and formed of AgO.sub.x (where in 0<.times.< 1/2) .
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: August 13, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Mizushima, Jiro Yoshida, Koh-ichi Kubo
  • Patent number: 5543630
    Abstract: The edge-defined, film-fed growth technique process is modified to produce a thin ribbon of bi-crystalline sapphire wherein the grain boundary is an essentially straight boundary and the angle is predetermined by selective cutting of the two seeds which are placed closely together during growth. The angle selection is optimized based on the superconducting material to be deposited and the application intended. After the ribbon is pulled, the ribbon is processed by cutting an appropriate section therefrom with the grain boundary. The substrate is polished and the high Tc superconducting material is deposited thereon to produce devices which rely on weak link Josephson junctions.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: August 6, 1996
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: David F. Bliss, Herbert E. Bates
  • Patent number: 5541422
    Abstract: The invention relates to a tunnel diode provided with two metallically conducting electrodes (1, 2) with an insulating dielectric (3) in between, which forms a barrier with a barrier level for electrons and which has a thickness such that electrons can tunnel through the barrier from the one to the other electrode. Such a tunnel diode has the disadvantage that it has no memory. In many applications it is desirable for the tunnel diode to hold a certain switching state, such as open/closed. According to the invention, the tunnel diode is characterized in that the dielectric (3) comprises a layer of a material which is ferroelectric at room temperature with a remanent polarization which influences the barrier level. It is achieved thereby that the tunnel diode has various switching states in dependence on the remanent polarization of the dielectric (3). The switching state is maintained until the polarization of the dielectric (3) changes.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: July 30, 1996
    Assignee: U.S. Philips Corporation
    Inventors: Ronald M. Wolf, Paulus W. M. Blom, Marcellinus P. C. M. Krijn
  • Patent number: 5539215
    Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, a first and a second superconducting regions formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer separated from each other and gently inclining to each other, a third superconducting region formed of an extremely thin c-axis oriented oxide superconductor thin film between the first and the second superconducting regions, which is continuous to the first and the second superconducting regions.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: July 23, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5528052
    Abstract: Proposed is a method for operating a field-effect device comprised of a superconducting current channel having source and drain electrodes connected thereto, said superconducting current channel being separated from a gate electrode by an insulating layer, where the resistance of said current channel is controlled by varying the critical current of the superconducting material through the application of an electrical field across the superconducting current channel, which in turn changes the density of the mobile charge carriers in the superconducting material. Taught is also an inverted MISFET device for performing that method, the device being characterized in that on an electrically conductive substrate an insulating layer is provided which in turn carries a layer consisting of a superconducting material, and that a gate electrode is attached to said substrate, and source and drain electrodes are electrically connected to said superconductor layer.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: June 18, 1996
    Assignee: International Business Machines Corporation
    Inventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller, Darrell G. Schlom
  • Patent number: 5525582
    Abstract: A Josephson junction device comprising a single crystalline substrate including a principal surface, a layer of the same material as the substrate formed on the principal surface of the substrate so as to form a step on the principal surface, and an oxide superconductor thin film formed on the principal surface of the substrate. The oxide superconductor thin film includes a first and a second superconducting portions respectively positioned above and below the step, which are constituted of single crystals of the oxide superconductor, a junction portion between the first and the second superconducting portions, which is constituted of a single crystal of the oxide superconductor of which crystal orientation is different from those of the first and second superconducting portions, and grain boundaries between the first superconducting portion and the junction portion and between the second superconducting portion and the junction portion, which constitute one weak link of the Josephson junction.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: June 11, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Saburo Tanaka, Takashi Matsuura, Hideo Itozaki
  • Patent number: 5514877
    Abstract: A superconducting device or a super-FET has a pair of superconducting electrode regions (20b,20c) consisting of a thin film (20)oxide superconductor being deposited on a substrate (5) and a weak link region (20a), the superconducting electrode regions (20b, 20c) being positioned at opposite sides of the weak link region (20a) these superconducting electrode regions (20b, 20c) and the weak link region (20a) being formed on a common plane surface of the substrate (5). The weak link region (20a) is produced by local diffusion of constituent element(s) of the substrate (5) into the thin film (20) of the oxide superconductor in such a manner that a substantial wall thickness of the thin film (20) of the oxide superconductor is reduced at the weak link region (20a) so as to leave a weak link or superconducting channel (10) in the thin film (20) of oxide superconductor over a non-superconducting region (50) which is produced by the diffusion.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: May 7, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5504058
    Abstract: In a method of manufacturing a superconducting device which has a first thin film of oxide superconductor material formed on a substrate and a second thin film formed on the first thin film of oxide superconductor material, after the second thin film is deposited on the first thin film of oxide superconductor material, a multi-layer structure formed of the first and second thin films is patterned so that a side surface of the first thin film is exposed. In this condition, the whole of the substrate is heated in an O.sub.2 atmosphere or in an O.sub.3 atmosphere so that oxygen is entrapped into the first thin film of oxide superconductor material. Thereafter, the patterned multi-layer structure is preferably covered with a protection coating.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: April 2, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Sou Tanaka, Mitsuchika Saitoh, Michitomo Iiyama
  • Patent number: 5498881
    Abstract: A superconducting device has a substrate and a superconducting film formed on the substrate. A surface of the substrate has a first surface portion of which a curvature is constant or changes continuously, a second surface portion of which a curvature is constant or changes continuously, and a third surface portion at which the first and second surface portions meet and at which the curvatures of the first and second surface portions become discontinuous. The superconducting film formed on the surface of said substrate has a grain boundary serving as a junction only in a portion corresponding to the third surface portion of the substrate.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: March 12, 1996
    Assignees: International Superconductivity Technology Ctr., Sharp Kabushiki Kaisha
    Inventors: Manabu Fujimoto, Keiichi Yamaguchi, Youichi Enomoto, Tsutomu Mitsuzuka, Katsumi Suzuki
  • Patent number: 5494891
    Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: February 27, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Michitomo Iiyama
  • Patent number: 5488030
    Abstract: There is disclosed a superconductor junction structure comprising: a first superconducting layer of an oxide superconductor formed in a desired pattern on a substrate; a non-superconducting layer of a non-superconductor formed on at least a part of the side faces of the first superconducting layer, a portion of the surface of the substrate near the part, and a top face of the first superconducting layer; and a second superconducting layer of the oxide superconductor formed on the non-superconducting layer, the non-superconducting layer being formed thin at the part, and forming a tunnel barrier.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: January 30, 1996
    Assignee: Sumitomo Electric Industries, Inc.
    Inventors: Saburo Tanaka, Takashi Matsuura, Hideo Itozaki
  • Patent number: 5480861
    Abstract: A layered structure formed on a substrate comprising an oxide superconductor thin film deposited on the substrate, a noble metal monolayer deposited on the oxide superconductor thin film and an insulator thin film deposited on the noble metal monolayer. The noble metal monolayer prevents interdiffusion between the oxide superconductor thin film and the insulator thin film so that they have excellent properties.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: January 2, 1996
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: So Tanaka, Michitomo Iiyama
  • Patent number: 5480859
    Abstract: A superconductor device is provided including a base, a base electrode formed on the base which is made of a Bi-system oxide superconductive material containing an alkaline earth metal, a barrier layer formed on the base electrode which is made of Bi--Sr--Cu--O, a counter electrode formed on the barrier layer which is made of a Bi-system oxide superconductive material containing an alkaline earth metal, a contact electrode formed so as contact with the counter electrode, and a separation layer for separating said contact electrode from said base electrode.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: January 2, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Mizuno, Hidetaka Higashino, Kentaro Setsune
  • Patent number: 5477061
    Abstract: A Josephson device comprises a first electrode layer of a superconducting material and containing Nb therein as a constituent element, an overlayer of a nitride of a refractory metal element provided on the first electrode layer, a barrier layer of an insulating compound that contains the metal element as a constituent element and acting as a barrier of a Josephson junction, the barrier layer being provided on the overlayer, and a second electrode layer of a superconducting material and containing Nb therein as a constituent element, the second electrode layer being provided on the barrier layer.
    Type: Grant
    Filed: September 20, 1991
    Date of Patent: December 19, 1995
    Assignee: Fujitsu Limited
    Inventor: Shinichi Morohashi
  • Patent number: 5472934
    Abstract: An anisotropic superconductor junction device consisting of a lower superconducting layer and an upper superconducting layer separated by a barrier layer, in which the upper and lower superconducting layers and the barrier layer each have a (103) crystal orientation in which the c axis is arranged in the same direction at an angle of 45 degrees relative to the plane of the junction.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: December 5, 1995
    Assignees: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Hiroshi Akoh, Hiroshi Sato
  • Patent number: 5471069
    Abstract: A superconducting device includes a superconducting channel constituted in an oxide superconductor the film deposited on a deposition surface of a substrate. A source electrode and a drain electrode are formed on the oxide superconductor thin film at opposite ends of the superconducting channel, so that a superconducting current can flow through be superconducting channel between the superconductor source electrode and the superconductor drain electrode. A gate electrode is formed through a gate insulator layer on the superconducting channel so as to control the superconducting current flowing through the superconducting channel. The gate electrode is in the form of a thin film and stands upright with respect to the gate insulator layer.
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: November 28, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5468973
    Abstract: A stacked Josephson junction device includes a pair of copper oxide superconductor layers and a non-superconductor layer formed between the pair of oxide superconductor layers. The copper oxide superconductor layers are composed of a compound copper oxide having the composition expressed by the general formula:LnBa.sub.2 Cu.sub.3 O.sub.v(where Ln is Y or rare earth element and 6<v.ltoreq.7).The non-superconductor layer is composed of a chemical compound having the composition expressed by the general formula:Bi.sub.2 Y.sub.x Sr.sub.y Cu.sub.z O.sub.w(where x, y, z and w indicate ratio of components0.ltoreq.x.ltoreq.2,1.ltoreq.y.ltoreq.3,1.ltoreq.z.ltoreq.3,6.ltoreq.w.ltoreq.13.
    Type: Grant
    Filed: March 31, 1994
    Date of Patent: November 21, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keizo Harada, Hideo Itozaki
  • Patent number: 5466664
    Abstract: A method of manufacturing a superconducting device involves forming a thin film on the surface of a substrate, forming a superconducting gate electrode on a portion of the thin film, etching the portions of the thin film using the gate electrode as a mask thereby providing a superconducting channel under the gate, forming a step portion on the superconducting channel and under the gate, converting the oxide portion of the step portion into a gate insulation portion by heating the substrate in a vacuum, forming a second oxide superconducting film on the exposed surface of the channel so that superconducting source and drain electrodes are formed on each side of the gate such that the drain and source have a thickness greater than that of the channel and are electrically isolated from the gate electrode.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: November 14, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Takao Nakamura, Michitomo Iiyama
  • Patent number: 5462916
    Abstract: The disclosed superconductive optoelectronic device with the basic substance Bi.sub.2 O.sub.3 or Bi.sub.2 O.sub.3 ;M.sup.2+ (M=Ca,Sr,Cu) of superconductive-conjugate photoconductivity has a substrate, a photoconductive gate region formed on the substrate, and a source region and a drain region formed on the substrate at opposite sides of the gate region so as to face toward each other across the gate region. The source region and the drain region are made of a Bi-based superconductive material. The gate region is made of such the basic material Bi.sub.2 O.sub.3 or Bi.sub.2 O.sub.3 ;M.sup.2+ (M=Ca,Sr,Cu) of superconductive-conjugate photoconductivity, which reveals photoconductivity at a temperature below the transition temperature of the above relevant Bi-based superconductive material. Also disclosed are superconductive optoelectronic devices formed of an organized integration of the above superconductive optoelectronic devices to develop effectively a new field of "Superconductive Optoelectronics".
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: October 31, 1995
    Assignee: The University of Tokyo
    Inventor: Taizo Masumi
  • Patent number: 5447907
    Abstract: A superconducting device comprising a substrate having a principal surface, a superconducting source region and a superconducting drain region formed of an oxide superconductor on the principal surface of the substrate separated from each other, a superconducting channel formed of the oxide superconductor between the superconducting source region and the superconducting drain region. The superconducting channel electrically connects the superconducting source region to a superconducting drain region, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region. The superconducting device comprises a gate electrode through a gate insulator on the superconducting channel for controlling the superconducting current flowing through the superconducting channel, and non-superconducting oxide layers having a similar crystal structure to that of the oxide superconductor.
    Type: Grant
    Filed: December 10, 1992
    Date of Patent: September 5, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5441926
    Abstract: A superconducting transistor having a source region and a drain region are formed by a YBCO film on a barrier layer, which is composed of a PBCO film formed on an STO substrate. A gate electrode is disposed on the thinner wall at the back of the STO substrate. In a superconducting transistor so constructed the electric field created by the gate voltage works effectively at an interface with the barrier layer, more carriers can be drawn out relative to the applied gate voltage, and it becomes possible for a large superconduction current to flow.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: August 15, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Hiroshi Kimura, Toshiyuki Matsui, Takeshi Suzuki, Kazuo Mukae, Akihiko Ohi
  • Patent number: 5430011
    Abstract: A superconducting thin film formed on a substrate, comprising at least one oxide superconductor layer formed on the principal surface of said substrate and at least one oxide layer formed of an oxide which compensates for crystalline incompleteness at the surface of said oxide superconductor layer, and which is arranged on or under the superconducting layer.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: July 4, 1995
    Assignee: Sumitomi Electric Industries, Ltd.
    Inventors: So Tanaka, Michitomo Iiyama
  • Patent number: RE37587
    Abstract: A SQUID includes a substrate and a superconducting current path of a patterned oxide superconductor material thin film formed on a surface of the substrate. A c-axis of an oxide crystal of the oxide superconductor material thin film is oriented in parallel to the surface of the substrate.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: March 19, 2002
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takashi Matsuura, Saburo Tanaka, Hideo Itozaki