Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.

Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.

Abstract: An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes. A first drain region has a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. The first drain region and the first, second, third and fourth source regions communicate with at least two of the N plane-like metal layers. A first gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions are arranged adjacent to corners of the first drain region.

Abstract: A display substrate having a low-resistance metallic layer and a method of manufacturing the display substrate. The gate conductors are extended in a first direction. The source conductors are extended in a second direction crossing the first direction including a lower layer of molybdenum or a molybdenum alloy, and an upper layer of aluminum or an aluminum alloy. The pixel areas are defined by the gate conductors and the source conductors. A switching element is formed in each of the pixel areas and includes a gate electrode extended from the gate conductor and a source electrode extended from the source conductor. The pixel electrode includes a transparent conductive material, and is electrically connected to a drain electrode of the switching element.

Abstract: An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active layers; first to fourth ohmic contact layers respectively contacting both sides of the first active layer and both sides of the second active layer; first and second source electrodes and first and second drain electrodes respectively on the first, third, second and fourth ohmic contact layers; a data line connected to the first source electrode; a first passivation layer connected to the first gate electrode; a power line; one end and the other end of a connection electrode respectively connected to the first drain electrode and the second gate electrode; a second passivation layer; and a pixel electrode-connected to the second drain electrode.

Abstract: A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located within a semiconductor substrate. A gate oxide is located between the gate electrode and the active regions, and source/drains are located adjacent the gate electrode and within the active region. An etch stop layer is located over the gate electrode and the gate electrode has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that in one embodiment overlies the active region, and in another embodiment is less than one alignment tolerance from the active region.

Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Abstract: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.

Abstract: A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.

Abstract: An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first set of equivalent crystal planes of a semiconductor substrate and a second channel of the second field effect transistor is oriented to at least one of a second, different set of equivalent crystal planes. The first set of equivalent crystal planes is parallel to a main surface of the semiconductor substrate and the second set of equivalent crystal planes is perpendicular to the main surface.

Abstract: A light emitting device is provided. The light emitting device includes a p-type semiconductor, an n-type semiconductor, a semiconductor film connected between the p-type semiconductor and the n-type semiconductor, a first electrode disposed on the semiconductor film and configured to apply an electric field to the semiconductor film, and a second electrode disposed under the semiconductor film and configured to apply an additional electric field to the semiconductor film.

Abstract: A method of manufacturing a semiconductor device having gate electrodes of a suitable work function material is disclosed. The method comprises providing a substrate (100) including a number of active regions (110, 120) and a dielectric layer (130) covering the active regions (110, 120), and forming a stack of layers (140, 150, 160) over the dielectric layer. The formation of the stack of layers comprises depositing a first metal layer (140), having a first thickness, e.g.

Abstract: An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate.

Abstract: A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

Abstract: An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated.

Abstract: A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.

Abstract: A display substrate includes; a substrate, a gate electrode arranged on the substrate, a semiconductor pattern arranged on the gate electrode, a source electrode arranged on the semiconductor pattern, a drain electrode arranged on the semiconductor pattern and spaced apart from the source electrode, an insulating layer arranged on, and substantially covering, the source electrode and the drain electrode to cover the source electrode and the drain electrode, a conductive layer pattern arranged on the insulating layer and overlapped aligned with the semiconductor pattern, a pixel electrode electrically connected to the drain electrode, and a storage electrode arranged on the substrate and overlapped overlapping with the pixel electrode, the storage electrode being electrically connected to the conductive layer pattern.

Abstract: A field transistor is divided into a number of cells (6) and includes a separate first gate line (20) connected to first transistor cells (8) and a separate second gate line (22) connected to second transistor cells (10). A drive circuit is used to drive all the cells (6) in a normal, saturated operations state but to drive only the second cells (10) in a linear operations state to reduce the number of cells used in the linear operations state.

Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: Manufacture of TFTs corresponding to various circuits makes structures thereof complex, which involves a larger number of manufacturing steps. Such an increase in the number of the manufacturing steps leads to a higher manufacturing cost and a lower manufacturing yield. In the invention, a high concentration of impurities is doped by using as masks a tapered resist that is used for the manufacture of a tapered gate electrode, and the tapered gate electrode, and then the tapered gate electrode is etched in the perpendicular direction using the resist as a mask. A semiconductor layer under the thusly removed tapered portion of the gate electrode is doped with a low concentration of impurities.

Abstract: A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Abstract: Nonvolatile integrated circuit memory devices having a 2-bit memory cell include a substrate, a source region and a drain region in the substrate, a step recess channel between the source region and the drain region, a trapping structure including a plurality of charge trapping nano-crystals on the step recess channel, and a gate on the trapping structure. Related fabrication methods are also described.

Abstract: A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad.

Abstract: A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.

Abstract: A semiconductor device comprising a substrate having a well region, at least one well pickup region formed on the substrate to surround the well pickup region, a first drain region formed on the substrate to be positioned on one side of the source region, and a first gate electrode formed on the substrate to be positioned between the source region and the first drain region.

Abstract: A planar, double-gate transistor structure comprising upper and lower gate stacks that each comprises a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics having gate-lengths less than 65 nm.

Abstract: A transistor having an electrode layer that can reduce or prevent a coupling effect, a fabricating method thereof, and an image sensor having the same are provided. The transistor includes a semiconductor substrate and a well of a first conductivity type formed on the semiconductor substrate. A heavily-doped first impurity region of a first conductivity type surrounds an active region defined in the well. Heavily-doped second and third impurity regions of a second conductivity type are spaced apart from each other in the active region an define a channel region interposed therebetween. A gate is formed over the channel region to cross the active region. The gate overlaps at least a portion of the first impurity region and receives a first voltage. An electrode layer is formed between the semiconductor substrate and the gate, such that the electrode layer overlaps a portion of the first impurity region contacting the channel region and receives a second voltage.

Abstract: A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping layer disposed between the gate electrode and the plug, and a gate hard mask layer whose sidewall disposed over the gate electrode is extended to a top surface of the capping layer. By employing the capping layer having a sidewall with a negative slope, the plug having the sidewall with a positive slope can be formed regardless of a shape or profile of the sidewall of the gate electrode. As a result, the contact area between the substrate and the plug is increased.

Abstract: A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive body from a second plane that is out of the first plane.

Abstract: Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the boundary between the active region and the isolation region adjacent to the active region. The gate electrode includes a first portion which is located above the active region with the gate insulating film interposed therebetween and is entirely made of a silicide in a thickness direction and a second portion which is located above the isolation region and is made of a silicon region and the silicide region covering the silicon region.

Abstract: An insulated gate field effect transistor has a drain region (2,4), a body region (6) of opposite conductivity type and a source region (8) and an insulated gate (14) extending laterally over the body region (6), defining a channel region (30) extending in the body region (6) from a source end adjacent to the source region (8) to a drain end adjacent to a drain end part (26) of the drain region (4). A conductive shield plate (22) is provided adjacent to the drain end for shielding the gate. Embodiments include a shield plate extension (32) extending over the drain region from the shield plate (22) towards the gate (14).

Abstract: A non-volatile memory (NVM) cell comprising a layer of discrete charge storing elements, a control gate, and a select gate is provided. The control gate has a first sidewall with a lower portion being at least a first angle 10 degrees away from 90 degrees with respect to substrate. Further, the select gate has a second sidewall with a lower portion being at least a second angle at least 10 degrees away from 90 degrees with respect to the substrate. The NVM cell further comprises a layer of dielectric material located between the first sidewall and the second sidewall.

Abstract: An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated.

Abstract: The present invention provides a semiconductor device, which includes a substrate and a sensing memory device. The substrate includes a metal-oxide-semiconductor transistor having a gate. The sensing memory device is disposed on the gate of the metal-oxide-semiconductor transistor and includes followings. The second conductive layer is covering the first conductive layer. The charge trapping layer is disposed between the first conductive layer and the second conductive layer, wherein the first conductive layer has a sensing region therein when charges stored in the charge trapping layer, and the sensing region is adjacent to the charge trapping layer. The first dielectric layer and the second dielectric layer are respectively disposed between the charge trapping layer and the first conductive layer and between the charge trapping layer and the second conductive layer, wherein a third dielectric layer is disposed between the gate and the sensing memory device.

Abstract: A semiconductor structure having a recessed active region and a method for forming the same are provided. The semiconductor structure comprises a first and a second isolation structure having an active region therebetween. The first and second isolation structures have sidewalls with a tilt angle of substantially less than 90 degrees. The active region is recessed. By recessing the active region, the channel width is increased and device drive current is improved.

Abstract: A semiconductor device includes a substrate including a semiconductor layer at a surface, a gate insulating film disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating film. The gate electrode includes a conductive layer consisting of a nitride of a predetermined metal in contact with the gate insulating film. The conductive layer is formed by stacking a first film consisting of a nitride of the predetermined metal and a second film consisting of the predetermined metal, and diffusing nitrogen from the first film to the second film by solid-phase diffusion.

Abstract: An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device can include a gate insulating layer on a semiconductor substrate, a gate electrode on the gate insulating layer and source/drain regions in the semiconductor substrate at sides of the gate electrode. The gate electrode includes a first gate electrode and a second gate electrode on and electrically connected to the first gate electrode.

Abstract: A semiconductor device can prevent exposure of an inner wall of a recess pattern caused by misalignment between masks. A gate electrode is formed inside the recess pattern so that only a gate hard mask layer is exposed above a substrate surface. Since the gate electrode is not exposed above the substrate, it is possible to prevent SAC failure and decrease an aspect ratio of a gate pattern to increase an open margin of a contact hole. Thus, a semiconductor device having a recess channel gate structure which exhibits a superior refresh property is fabricated.

Abstract: A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface.

Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

Abstract: A transistor, comprising a first gate structure formed on a substrate, and having a stacked structure of a first gate electrode and a first gate hard mask, a first gate spacer formed on sidewalls of the first gate structure, a second gate structure having a stacked structure of a second gate electrode and a second gate hard mask, the second gate structure surrounding both sidewalls and top surfaces of the first gate structure and the first gate spacer, and a second gate spacer formed on sidewalls of the second gate structure.