Abstract: A computer implemented method provides for orientation and lay-out asymmetrical semiconductor devices. The sources of operating potential (20, 30) are identified. The PMOS transistors (22-28) are combined between the first (more positive) source of operating potential and a common node (12) into a combination block (48). The NMOS transistors (14-18) are combined between the common node and the second (less positive) source of operating potential into another combination block (52). The PMOS source terminals are coupled to more positive potentials, and the PMOS drain terminals are coupled to less positive potentials within the first combination block. The NMOS source terminals are coupled to less positive potentials, and the NMOS drain terminals are coupled to more positive potentials within the second combination block. For transmission gates (60, 62), a driving source is identified and the PMOS and NMOS source terminals are coupled to the driving source.

Abstract: A charge generation device configured within a semiconductor region of a substrate. The device includes a source for providing an input charge and an input diffusion which receives said input charge. A barrier gate associated with the input diffusion determines a selected potential of the input diffusion. A preset diffusion presets the input diffusion to the selected potential. An output element receives the input charge from the input diffusion. A first coupling means is provided for coupling the preset diffusion to the input diffusion subsequent to the output diffusion receiving the input charge during a first clock cycle, and for decoupling the preset diffusion from the input diffusion prior to the input diffusion receiving the input charge during a second clock cycle.

Abstract: A method of forming a line for floating gate transistors is described and which includes, providing a substrate having a plurality of discrete field oxide regions, and intervening active area regions therebetween; forming a first alternating series of floating gates over a first alternating series of active area regions; forming a second alternating series of floating gates over a second alternating series of active area regions, the second series of floating gates disposed in spaced, overlapping and partial covering relation relative to the first alternating series of floating gates; forming a layer of dielectric material over the first and second series of floating gates; and forming a control gate layer of electrically conductive material over the layer of dielectric material. The present invention further relates to a memory chip, and die having a line of floating gate transistors formed from the same method.

Abstract: An improved transistor structure includes an insulated conductive gate spacer which is contacted and driven separately from the gate of the transistor. The gate spacer serves as a control or second gate for the transistor and may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistor are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors. When the improved transistor is used selectively within an integrated circuit, the remaining devices can be structured as standard LDD transistors using the gate spacers in a conventional manner.

Abstract: A semiconductor device has a structure in which pluralities of gate electrodes, drain electrodes, and source electrodes extend in parallel to each another. The semiconductor device includes at least one isolation area formed in a direction perpendicular to at least one gate electrode so as to separate one active layer area formed on a semiconductor substrate into a plurality of active layer areas. The at least one gate electrode is connected to each of the plurality of active layer areas separated by the at least one isolation area.

Abstract: A thin film transistor comprises a dielectric substrate (1), a semiconductor layer (3) of poly-crystalline silicon layer having a drain region (8), an active gate region (4, 8-0), and a source region (7) placed on said substrate (1), a drain terminal (10) and a source terminal (10A) connected to said respective regions for external connection, a gate electrode (6) coupled with a part of said gate region (4) through a dielectric layer (4A), wherein length (d) of said gate electrode (6) is shorter than the length of gate region (4 plus 8-0), so that an offset region (8-0), where no gate electrode faces with said gate region, is produced.

Abstract: In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, By existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

Abstract: A diode is provided comprising first and second semiconductor regions. The first semiconductor region is of one conductivity type and the second is of the opposite conductivity type. A third region is provided which is either an intrinsic semiconductor region or a low concentration region. The low concentration region has an impurity concentration lower than that of the first and second semiconductor layers. The third region is arranged to separate the first and second semiconductor regions. A control electrode region is provided over the third region through an insulative film.

Abstract: A power MOSFET includes a pair of electrically isolated gates having different gate widths. The MOSFET is connected in a switching mode DC--DC converter, with the gates being driven by a pulse width modulation (PWM) control to vary the duty cycle of the gate drive signal and thereby regulate the output voltage of the DC--DC converter. In light load conditions, the larger gate is disconnected from the PWM control to reduce the gate capacitance which must be driven by the PWM control. In normal load conditions, the larger gate is connected to the PWM control to reduce the on-resistance of the MOSFET. Both of these operations increase the efficiency of the DC--DC converter.

Abstract: A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Abstract: This invention relates to MOS transistors and a method for fabricating the MOS transistors having LDD (Lightly Doped Drain) structures, which comprises a first conduction type semiconductor substrate, a second conduction type high density source and drain regions formed spaced from each other in the first conduction type semiconductor substrate, a second conduction type low density impurity region formed on sides facing each other of, and adjacent to the second conduction type high density source and drain regions, a first gate insulation film formed on both ends of a upper part of the semiconductor substrate region between the second conduction type low density impurity region, a second gate insulation film formed on upper part of the semiconductor substrate region between the first gate insulation films, a first conduction layer in a form of side wall spacer formed on the first gate insulation film, a second conduction layer formed on the second gate insulation film, a third conduction layer formed on the f

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A combination of a lower thin film transistor formed on an insulating substrate and an upper thin film transistor laminated over the lower transistor has a lower channel formed in the lower transistor, an upper channel formed in the upper transistor, a lower gate electrode disposed under the lower channel, an intermediate gate electrode disposed between the lower channel and the upper channel, and an upper gate electrode disposed over the upper channel.

Abstract: Upward and downward variation of a threshold voltage of a TFT is effectively suppressed by a semiconductor device and a method of manufacturing the same. In the semiconductor device, a conductive layer is formed on the substantially same plane as a semiconductor layer forming a channel region and source/drain regions of the TFT, and is spaced from the semiconductor layer by a predetermined distance. A predetermined potential is applied to the conductive layer. Thereby, an electric field is applied from the conductive layer to the channel region of the TFT, so that variation of the threshold voltage of the TFT is effectively prevented.

Abstract: The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.

Abstract: A MOS TFT includes a back gate electrode of a silicide formed on an underlying insulating layer, and a polysilicon layer deposited on the underlying insulating layer so as to completely cover the back gate electrode. A gate oxide and a gate electrode are formed on the polysilicon layer in the named order and positioned above the back gate electrode. In alignment with the gate oxide and the gate electrode, a pair of high concentration source/drain regions are formed in the polysilicon layer, so that a channel is formed by a portion of the polysilicon layer under the gate oxide. The whole is coated with a CVD oxide silicon protection film, and a source/drain electrode is formed to contact to each of the source/drain regions through a contact hole formed through the oxide silicon protection film. By fixing a potential of the back gate, a source-drain breakdown voltage can be considerably increased.

Abstract: A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.

Abstract: A novel structure of a polycrystalline silicon thin film transistor manifested in a drain offset region and a sub-gate structure. The drain offset region is formed between a channel region and a drain region in the polycrystalline silicon thin film. The sub-gate structure comprises at least one sub-gate, except for a main gate which is provided in a normal field effect transistor. This structure is applicable to either an upper gate type or a bottom gate type thin film transistor. The sub-gate structure may include an upper sub-gate and/or a bottom sub-gate. The upper sub-gate overlays the channel region, drain offset and drain regions through an insulation layer. The bottom sub-gate underlies the channel region, drain offset and drain regions through an insulation layer. The sub-gate is applied with the same voltage or less as the drain voltage thereby permitting a relaxation of a high field concentration caused at a drain junction to be realized.

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR.sub.1 comprising a semiconductor channel layer Ch.sub.1, first and second conductive gates G.sub.1, G.sub.2, and first and second conductive layers L.sub.1, L.sub.2 ; and a switching transistor TR.sub.2 comprising a semiconductor channel forming region Ch.sub.2, a third conductive gate G.sub.3, and third and fourth conductive layers L.sub.3, L.sub.4, wherein the fourth conductive layer L.sub.4 is connected to the second conductive gate G.sub.2, the first conductive gate G.sub.1 and the third conductive gate G.sub.

Abstract: A semiconductor transistor device comprises a gate electrode disposed over an insulating surface, a spacer element located at the end of the gate electrode, a gate insulating film covering the gate electrode, a first diffusion region spaced apart from one end of the gate electrode, separated therefrom by the gate insulating film and by the spacer element which reduces the electric field between the gate and first diffusion region, the first diffusion region extending vertically above the gate insulating film, and a second diffusion region disposed above the gate insulating film having one end spaced from the first diffusion vertically extending region.

Abstract: An MOS transistor has a source region, a drain region, first gate electrode with a first channel zone allocated to it, second gate electrodes having a second channel zone allocated to it, and a third gate electrode with a corresponding third channel zone. The second channel zone is more highly doped than the base material in which the MOS transistor is formed, while the third channel zone is more lightly doped than the second channel zone. The second and third gate electrodes are conductively connected so that higher drain voltages are accommodated at high-frequencies while avoiding tunnel punch-through.

Abstract: The invention provides a semiconductor device equipped with a high-voltage MISFET capable of forming a push-pull circuit on one chip by optimizing a junction-separation structure. In an n-channel MOSFET, when a potential is applied to the gate electrode, to the source electrode, and across the drain electrode and the semiconductor substrate to expand the depletion layer from the junction face of a semiconductor substrate and a well formed thereon, the leading edge of the depletion layer does not reach a low-concentration drain diffusion region formed on the well. When a potential is applied to the drain electrode, to the semiconductor substrate, and across the source electrode and the gate electrode to expand a depletion layer from the junction face of the low-concentration drain diffusion region and the well, and a depletion layer from the junction face of semiconductor substrate and the well, the depletion layers are connected with each other.

Abstract: A submicron MOSFET is fabricated on an ultrathin layer with a generally intrinsic channel having a dopant concentration less than about 10.sup.16 cm.sup.-3. The channel thickness is preferably no greater than about 0.2 microns; the ratio of channel thickness to length is less than about 1:4, and preferably no greater than about 1:2. Punchthrough and other short-channel effects are inhibited by the application of an appropriate back-gate voltage, which may also be varied to adjust the voltage threshold.

Abstract: First and second N-channel MOS transistors, each serving as a transfer gate, have their current paths connected, at their first ends, to bit lines, respectively, and their gates connected to a word line. Third and fourth N-channel MOS transistors, forming a flip-flop circuit, have their current paths connected, at their first ends, to the second ends of the current paths of the first and second transistors, respectively, and at their second ends, to a first power supply. The first ends of the current paths of the third and fourth transistors are connected to first ends of first and second thin-film transistors, respectively. The second ends of the current paths of the first and second thin-film transistors are connected to a second power supply. Each of the first and second thin-film transistors has first and second gates on both sides of its channel region.

Abstract: A thin-film transistor using hydrogenated amorphous silicon (a-Si:H), and particularly a thin-film device such as a thin-film transistor having high conductivity, large drivability and high process margin, and a display panel using the same transistors. The object of the invention is to reduce defects due to shorts between the gate and the source or between the gate and the drain, to prevent signal line defect even in case defects develop due to shorts, and to expand the design margin and process margin in the array. A capacity is connected to the gate electrode of the channel side and a voltage is applied to the gate electrode via the capacity.

Abstract: A field effect semiconductor device having multiple vertically stacked channels (12, 14, 16) separated by independent gate electrodes (13, 15) is provided. The channels (12, 14, 16) are formed on a wide bandgap buffer layer (11) and each channel is coupled a drain electrode (21). Each channel is also coupled to a source electrode (25-26). The quantum well channels (12, 14, 16) and quantum well gates (13, 15) are separated from each other by barrier layers (18) of a wide bandgap semiconductor material.

Abstract: A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) are disposed to create inversion regions, and a second conductivity type opposite said first conductivity type, in the underlying source inversion region (40) and drain inversion region (42) of semiconductor layer (12) upon application of voltage. The transistor has a gate (54) insulatively overlying the channel region (44) to control the conductivity thereof.