With Barrier Region Of Reduced Minority Carrier Lifetime (e.g., Heavily Doped P+ Region To Reduce Electron Minority Carrier Lifetime, Or Containing Deep Level Impurity Or Crystal Damage), Or With Region Of High Threshold Voltage (e.g., Heavily Doped Channel Stop Region) Patents (Class 257/376)
  • Structure and method of manufacture for semiconductor device
    Patent number: 5160996
    Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type, a well which is a second conductivity type, a buried layer, which is of the first conductivity type, and an insulating isolation layer formed extending to an upper surface of a side region of the well. The buried layer has a first portion of a higher dopant concentration than the semiconductor substrate and formed in a deep region of the semiconductor substrate directly below the well, and a second portion formed in a region of the substrate which is positioned higher than the region in which the first portion is formed. The first and second portions of the buried layer are formed integrally in a region of the semiconductor substrate which is directly below the insulating isolation layer, surround the well within the semiconductor substrate, and have a high concentration of a dopant that is of the first conductivity type at a position which is directly below the insulating isolation layer.
    Type: Grant
    Filed: August 9, 1991
    Date of Patent: November 3, 1992
    Assignee: Matsushita Electric Industrial Co., Inc.
    Inventor: Shinji Odanaka