Abstract: Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed on the substrate using polycrystalline or amorphous titanium oxides; and an insulating layer formed on the active layer. Further, the method of manufacturing the thin film transistor includes: forming a substrate; forming an active layer on the substrate using polycrystalline or amorphous titanium oxides; and forming an insulating layer on the active layer.

Abstract: A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain region disposed in the semiconductor substrate; a silicide layer disposed on top of the gate and the surface of the source/drain region; and a retarded interface layer disposed in the junction between the silicide layer and the gate and source/drain region.

Abstract: Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line includes a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further include gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

Abstract: A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.

Abstract: The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films.

Abstract: A method for fabricating a semiconductor structure. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. A semiconductor layer and a gate stack on the semiconductor layer are provided. The semiconductor layer includes (i) a channel region directly beneath the gate stack, and (ii) first and second semiconductor regions essentially not covered by the gate stack, and wherein the channel region is disposed between the first and second semiconductor regions. The first and second semiconductor regions are removed. Regions directly beneath the removed first and second semiconductor regions are removed so as to form first and second source/drain regions, respectively, such that top surfaces of the first and second source/drain regions are below a top surface of the channel region.

Abstract: A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semiconductor substrate and the gate electrode and having a plurality of contact holes formed therein, and contact plugs formed within the contact holes. The contact plugs can include a first contact plug and a second contact plug electrically connected to the gate electrode, and a third contact plug and a fourth contact plug electrically connected to the source/drain regions.

Abstract: Provided are semiconductor devices having low resistance contacts and methods of manufacturing the same.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench to cover a bottom surface and a side surface of the trench and an upper surface of the first liner nitride layer, etching overhangs generated during the forming of the first HDP oxide layer by introducing a hydrofluoric acid (HF) solution into the semiconductor substrate, forming a second liner nitride layer over the first HDP oxide layer, removing the second liner nitride layer formed on the first HDP oxide layer while forming a second HDP oxide layer to fill the trench, and subjecting the second HDP oxide layer to planarization, so as to form a trench isolation layer.

Abstract: During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency.

Abstract: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.

Abstract: A semiconductor device includes: an n-channel MIS transistor and a p-channel MIS transistor. An n-channel MIS transistor includes: a first gate insulating film having an amorphous layer or an epitaxial layer formed on a p-type semiconductor region between a first source/drain regions; and a first gate electrode having a stack structure formed with a first metal layer and a first compound layer. The first metal layer is formed on the first gate insulating film and made of a first metal having a work function of 4.3 eV or smaller, and the first compound layer is formed on the first metal layer and contains a compound of a second metal and a IV-group semiconductor. The second metal is different from the first metal. A p-channel MIS transistor includes a second gate electrode having a second compound layer containing a compound of the same composition as the first compound layer.

Abstract: A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

Abstract: Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

Abstract: In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10?11 ?cm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having first and second active areas defined thereon by isolation layers, a first gate electrode in the first active area, in which the first gate electrode includes a first silicide, and a second gate electrode in the second active area, in which the second gate electrode includes a second silicide having a composition ratio of silicon different from a composition ratio of silicon of the first silicide.

Abstract: A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal.

Abstract: A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

Abstract: A trench metal oxide semiconductor field effect transistor (MOSFET) with a terraced trench gate. An epitaxial layer with a plurality of trenches is provided and a gate oxide layer is covered the sidewalls and bottoms of the trenches. A polysilicon layer is filled in the trenches, wherein the polysilicon layer is higher than the sidewalls of the trenches to be used as a gate of the MOSFET. A plurality of sources and bodies are formed in the epitaxial layer, and the bodies at both sides of the trenches. An insulating layer is covered on the substrate, wherein a plurality of metal contact windows are provided. Metal plugs are filled in the metal contact windows to form metal connections for the MOSFET.

Abstract: A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary of the contact layer is disposed above a bottommost boundary of the surface layer.

Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract: A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film, the area of the second gate electrode on the surface of the semiconductor substrate being larger than that of the first gate electrode; selectively etching or grinding an upper part of the second gate electrode so that the thickness of the second gate electrode becomes smaller than the thickness of the first gate electrode; depositing a metal film on the first gate electrode and the second gate electrode; and siliciding the whole of the first gate electrode and the whole of the second gate electrode.

Abstract: A semiconductor structure fabrication method. The method includes providing a structure which includes (a) first and second semiconductor regions, (b) first and second gate dielectric regions on the first and second semiconductor regions, respectively, (c) a high-K dielectric region on the first gate dielectric region, K being greater than 4, (d) an electrically conductive layer on the high-K dielectric region, (e) a poly-silicon layer on the electrically conductive layer and the second gate dielectric region, and (f) a hard mask layer on the poly-silicon layer. The hard mask layer is patterned resulting in first and second hard mask regions. The poly-silicon layer is etched with the first and second hard mask regions as blocking masks resulting in first and second poly-silicon regions. The first and second poly-silicon regions are exposed to a surrounding ambient.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.

Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

Abstract: A element isolation insulating film is formed around the device regions in the silicon substrate. The device regions are formed an n-type diffusion layer region, a p-type diffusion layer region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type source/drain region, and a nickel silicide film. Each gate dielectric film is made up of a silicon oxide film and a hafnium silicon oxynitride film. The n-type gate electrode is made up of an n-type silicon film and a nickel silicide film, and the p-type gate electrode is made up of a nickel silicide film. The hafnium silicon oxynitride films are not formed on the sidewalls of the gate electrodes.

Abstract: Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.

Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.

Abstract: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm?2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

Abstract: A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate dielectric. A dielectric layer is formed over the silicon-containing layer. A top layer is formed over the dielectric layer. The gate dielectric, the silicon-containing layer, the dielectric layer, and the top layer are patterned into a gate stack. A spacer is formed along an edge of the gate stack. The top layer and the dielectric layer are removed. A metal layer is deposited on the silicon-containing layer and silicided.

Abstract: A semiconductor device including a silicon substrate; a gate insulating film on the silicon substrate; a gate electrode on the gate insulating film; and source/drain regions formed in the substrate on both sides of the gate electrode, wherein the gate electrode includes a first silicide layered region formed of a silicide of a metal M1; and a second silicide layered region on the first silicide layered region, the second silicide layered region being formed of a silicide of the same metal as the metal M1 and being lower in resistivity than the first silicide layered region.

Abstract: A CMOS image sensor and a method for forming the same are provided. According to the method, a gate insulating layer and a doped polysilicon layer which are sequentially stacked on a substrate are patterned to form a transfer gate and a reset gate set apart from each other. A floating diffusion layer between the transfer gate and the reset gate, a light receiving element at a side of the transfer gate away from and opposite to the floating diffusion layer and a source/drain region at a side of the reset gate away from and opposite to the floating diffusion layer are formed. An insulation layer and a mold layer are sequentially formed on an entire surface of the substrate, and the mold layer is planarized until the insulation layer is exposed. The exposed insulation layer is removed to further expose an upper surface of the gates. A selective silicidation process is carried out using a metal gate layer to form a metal gate silicide on the exposed gate.

Abstract: A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.

Abstract: A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducing layer is formed over at least a portion of the functional features and the non-functional feature. A device includes a semiconductor layer, a first dummy gate electrode, and a stress-inducing layer. The plurality of transistor gate electrodes is formed above the semiconductor layer. The plurality includes at least a first end gate electrode, a second end gate electrode, and at least one interior gate electrode. The first dummy gate electrode is disposed proximate the first end gate electrode. The stress-inducing layer is disposed over at least a portion of the plurality of transistor gate electrodes and the first dummy gate electrode.

Abstract: A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the trench, a first poly silicon film formed inside of the trench, and a cell plate electrode located above the dielectric film. The cell plate electrode includes a first poly silicon film formed on the dielectric film partially filling the trench, and a second poly silicon film formed on the first poly silicon film to completely fill the trench. The second poly silicon film includes a sufficient film thickness for forming gate electrodes, wherein the impurity concentration of the first poly silicon film is higher than the impurity concentration of the second poly silicon film.

Abstract: In one aspect, there is provided a method of manufacturing a semiconductor device. This method includes forming gate structures over a substrate, wherein the gate structures include gate electrodes located adjacent source/drain regions. A protective layer is formed over the gate structures and a CMP layer is formed over the protective layer. A portion of the CMP layer and the protective layer is removed to expose a portion of the gate electrodes with remaining portions of the CMP layer and the protective layer remaining over the source/drain regions. The exposed portion of the gate electrodes are doped with an n-type dopant or a p-type dopant, and the remaining portions of the CMP layer and the protective layer located over the source/drain regions are removed subsequent to the doping.

Abstract: Provided are a semiconductor device and a method of forming the same. The method includes forming an interlayer dielectric on a semiconductor substrate, forming a contact hole in the interlayer dielectric to expose the semiconductor substrate, forming a metal pattern including a dopant on the exposed semiconductor substrate, and performing a heat treatment process to react the semiconductor substrate with the metal pattern to form a metal silicide pattern. The heat treatment process includes diffuses the dopant into the semiconductor substrate.

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.

Abstract: A semiconductor device has an n-channel MISFET having first diffusion layers formed in a first region of a surface portion of a semiconductor substrate so as to sandwich a first channel region therebetween, a first gate insulating film formed on the first channel region, and a first gate electrode including a first metal layer formed on the first gate insulating film, and a first n-type polysilicon film formed on the first metal layer, and a p-channel MISFET having second diffusion layers containing boron as a dopant and formed in a second region of the surface portion of the semiconductor substrate so as to sandwich a second channel region therebetween, a second gate insulating film formed on the second channel region, and a second gate electrode including a second metal layer containing nitrogen or carbon and formed on the second gate insulating film and a second n-type polysilicon film formed on the second metal layer and having a boron concentration of not more than 5×1019 cm?3 in a portion adjacent an in

Abstract: A low contact resistance CMOS integrated circuit and method for its fabrication are provided. The CMOS integrated circuit comprises a first transition metal electrically coupled to the N-type circuit regions and a second transition metal different than the first transition metal electrically coupled to the P-type circuit regions. A conductive barrier layer overlies each of the first transition metal and the second transition metal and a plug metal overlies the conductive barrier layer.

Abstract: A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

Abstract: A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer, and a silicide layer on the second silicon-containing layer. The element in the second silicon-containing layer has a second atomic percentage of the element to the element and silicon, wherein the second atomic percentage is substantially lower than the first atomic percentage.

Abstract: A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate.

Abstract: A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a semiconductor substrate; a first silicide layer formed on the first source layer and the first drain layer; a first gate electrode formed on a first gate insulating film formed on the surface of the semiconductor substrate and having a second silicide layer; and a silicon nitride film formed on the sidewall of the first gate electrode; a second transistor including: a second source layer and a second drain layer both formed in the surface of the semiconductor substrate; a third silicide layer formed on the second source layer and the second drain layer and equal in thickness to the first silicide layer; a second gate electrode formed on a second gate insulating film formed on the surface of the semiconductor substrate and having a fourth silicide layer thinner in thickness than the second silicide layer.