Abstract: A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interlayer insulation layer formed over the gate electrode and the substrate, and a shared contact piercing the interlayer insulation layer and contacting the gate electrode and one of the LDD-type source/drain regions including at least a part of a lightly doped drain region. Multiple-layer spacers are formed on both sides of the gate structure and used as a mask in forming the LDD-type regions. At least one layer of the spacer is removed in the contact opening to widen the opening to receive a contact plug.

Abstract: A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.

Abstract: A resistance element of a semiconductor device includes a first resistance pattern and a second resistance pattern formed adjacent to the first resistance pattern at a lower level, wherein the second resistance pattern is defined by the first resistance pattern in a self-aligned relationship and connected to the first resistance pattern in series.

Abstract: After a MOS type transistor is formed on the surface of a semiconductor substrate, an interlayer insulating film covering the transistor is formed. The insulating film includes a silicon oxide film made of hydrogen silsesquioxane resin in a ceramic state. After a wiring layer is formed on the insulating film, a silicon oxide film as a surface protection film is formed on the insulating film, covering the wiring layer. In order to reduce process damages, heat treatment is performed 30 minutes at 400° C. in a nitrogen gas atmosphere. With this heat treatment, hydrogen in the silicon oxide film is released and diffuses into the channel region of the transistor to lower interfacial energy levels. Since the silicon nitride film does not transmit hydrogen, it is not necessary for the heat treatment atmosphere to contain hydrogen. A variation in threshold voltages of MOS type transistors can be easily lowered.

Abstract: A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Abstract: A field effect transistor includes a pair of source/drain regions having a channel region positioned therebetween. A gate is positioned operatively proximate the channel region. The gate includes semiconductive material conductivity doped with at least one of a p-type or n-type conductivity enhancing impurity effective to render the semiconductive material electrically conductive, a silcide layer and a conductive diffusion barrier layer effective to restrict diffusion of p-type or n-type conductivity enhancing impurity. The conductive diffusion barrier layer includes TiWxNy. Integrated circuitry is also disclosed.

Abstract: A semiconductor device having active regions connected by an interconnect line, which includes first and second transistors each having active regions and formed spaced apart from each other in a semiconductor substrate, an isolation region for isolating the first and second transistors from each other, a slit formed in the isolation region to allow those paired active regions of the first and second transistors which are opposed to each other with the isolation region interposed therebetween to communicate with each other through it, a conductive film formed on the inner walls of the slit, and an interconnect layer having first and second portions, each of which is electrically connected with a corresponding one of the paired active regions, and a third portion which is formed along the slit on the isolation region to connect the first and second portions with each other.

Abstract: The semiconductor device comprises a gate electrode 26 formed on a semiconductor substrate 10, a source region 45a having a lightly doped source region 42a and a heavily doped source region 44a, a drain region 45b having a lightly doped drain region 42b and a heavily doped drain region 44b, a first silicide layer 40c formed on the source region, a second silicide layer 40d formed on the drain region, a first conductor plug 54 connected to the first silcide layer and a second conductor plug 54 connected to the second silicide layer. The heavily doped drain region is formed in the region of the lightly doped region except the peripheral region, and the second silicide layer is formed in the region of the heavily doped drain region except the peripheral region. Thus, the concentration of the electric fields on the drain region can be mitigated when voltages are applied to the drain region.

Abstract: There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.

Abstract: Without forming a silicide film on a surface of a photodiode PD formation portion and a surface of a drain portion of a reset transistor T1 having an impurity region as a drain connected to an impurity region of the photodiode PD, the silicide film is formed on a surface of a source portion of the reset transistor T1 and a surface of a source/drain portion of other MOS transistors.

Abstract: A semiconductor device, including a dummy diffused layer in the upper part of a substrate, has its noise immunity improved. The dummy diffused layer is formed between analog and digital blocks to eliminate dishing, which usually occurs during a CMP process for defining STI regions. The surface of the dummy diffused layer is covered with an anti-silicidation film at least partially and a dummy gate electrode so as not to be silicided. The dummy gate electrode can be formed along with a normal gate electrode for a transistor. Accordingly, there is no need to add any extra process step to the fabrication process.

Abstract: In a semiconductor device in which a source/drain and a wiring layer are connected to each other through an associated buried conductive layer, a separation width of the buried conductive layer on a upper portion of a gate electrode is made small in order to manufacture a highly reliable and fine MOS transistor. After a silicon oxide film has been formed on a first polycrystalline silicon film so as to be aligned with a width of a gate electrode, a second polycrystalline silicon film formed on the whole surface of a substrate is selectively etched away so as to be left only on both side faces of a pattern of the silicon oxide film. Thereafter, the first polycrystalline silicon film is separated with a width which is smaller than that of the gate electrode by a width of a pattern of the second polycrystalline silicon film. In such a way, the buried conductive layer including the first and second polycrystalline silicon films is formed.

Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.

Abstract: A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a second opening are located in the insulating fill layer, a first source or drain electrode is located in the first opening and a second source or drain electrode is located in the second opening. At least one of the first and the second source or drain electrodes comprise a polysilicon layer and a metal silicide layer.

Abstract: A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.

Abstract: In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.

Abstract: Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration.

Abstract: A reliable electrode structure capable of ensuring a sufficient width for a second conductive layer is provided. The electrode structure comprises a first conductive layer having first side walls and containing at least either polycrystalline silicon or amorphous silicon, a second conductive layer, formed on the first conductive layer, having second side walls and containing a metal and silicon, and side wall oxide films formed to be in contact with the first side walls and the second side walls. The first conductive layer and the second conductive layer contain nitrogen in the vicinity of the first and second side walls. The nitrogen concentration in the second side walls is larger than the nitrogen concentration in the first side walls.

Abstract: When an arsenic ion (As+) large in mass is injected, polysilicon films are covered with a fifth resist mask so as to cover an end of the resist mask covering the polysilicon films to form a PMOS forming region. Through this process, a silicide non-forming region is arranged not to overlap with a pn junction to prevent the silicide non-forming region from increasing in resistance.

Abstract: P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.

Abstract: A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

Abstract: On a semiconductor substrate having a gate electrode and an LDD layer formed thereon, an SiN film to be a silicide block is formed. An opening communicating with the LDD layer is provided for the SiN film. Impurities are introduced into the LDD layer through the opening to form a source/drain layer, and the surface thereof is silicided to form a silicide film. Next, an interlayer insulation film of SiO2 is formed and then etched under a condition of an etching rate of SiO2 higher than that of SiN to form a contact hole reaching the LDD layer from the upper surface of the interlayer insulation film via the opening.

Abstract: A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.

Abstract: The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.

Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Abstract: An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

Abstract: A gate electrode of an n-channel IGFET includes a first region composed of at least a first IV group element and a second IV group element which are different from each other, and a second region composed of the first IV group element. Similarly, a gate electrode of a p-channel IGFET includes first and second regions. For example, the first region is made of SiGe while the second region is made of Si. In both of the n-channel and P-channel IGFET, silicide electrodes are formed on the gate electrodes 4N and 4P through silicidation of at least parts of the second regions.

Abstract: An object is to prevent protrusion of a plug from an interlayer insulating film to prevent formation of a step between circuit parts exceeding a step height allowed in a planarization process and also to prevent formation of particles due to a protruded plug. An interlayer insulating film (11) is etched back over the entire surface under an etching condition in which the etching selectivity of a polysilicon plug (13) with respect to the interlayer insulating film (11) is 10, for example, to recess the polysilicon plug (13) to a given depth in a bit line contact hole (12) to form a recessed polysilicon plug (27).

Abstract: An electronic device supported on a semiconductor substrate. The semiconductor device includes a diffusion area in the substrate and a polysilicon layer extending over the substrate and contacting the diffusion area. The electronic device further includes a conductive contact covering and contacting both the polysilicon layer and the diffusion area. Therefore, the semiconductor device disclosed in this invention includes poly-to-diffusion connection for a semiconductor device that has a diffusion are and a polysilicon area. The semiconductor device further includes a contact that covers both the diffusion area and the polysilicon area with a contact filling material forming the connection between these two areas.

Abstract: A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Abstract: Each of a plurality of repeating units comprises a plurality of memory cells. A second-conductivity-type well is formed in a surface layer of a semiconductor substrate extending over the plurality of the repeating units. In the second-conductivity-type well, first-conductivity-type channel MOS transistors of the plurality of the repeating units are provided. A second-conductivity-type well tap region is formed in one of the memory cells in each repeating unit and in the second-conductivity-type well. In the memory cell provided with the second-conductivity-type well tap region or in the memory cell adjacent thereto, an interlayer connection member is provided. The interlayer connection member is connected to the source region of one of the first-conductivity-type channel MOS transistors and to the corresponding second-conductivity-type well tap region.

Abstract: A semiconductor device includes a substrate of a first conductive type, and a well region of an opposite second conductive type is formed in the substrate. A first impurity region of the first conductive type extends to a first depth within the well region, and a second impurity region of the first conductive type is spaced from the first impurity region to define a channel region therebetween and extends to a second depth within the well region. Preferably, the second depth is greater than the first depth. A gate electrode is located over the channel region, and a silicide layer is formed at a third depth within the first impurity region. The third depth is less than the first depth, and a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer.

Abstract: A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate—gate electrode layer, a second gate—gate electrode layer, a first drain—drain wiring layer, a second drain—drain wiring layer, a first drain-gate wiring layer and second drain-gate wiring layers. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively. The width of the first gate—gate electrode layer in the first load transistor is larger than the width of the first gate—gate electrode layer in the first driver transistor.

Abstract: A local interconnect structure that includes a silicon spacer. After deposition of polysilicon gates and formation of spacers on a semiconductor substrate, photolithography and oxide etch steps are performed to remove a portion of a spacer along a segment of the gate where local interconnection is to be formed. A thin screen oxide layer is deposited over the wafer, followed by the formation of diffusion regions. A silicon layer (either amorphous or polycrystalline) is then deposited. The silicon layer is then selectively etched so as to form a silicon spacer along the segment of the gate where local interconnection is to be formed. A conventional SALICIDE process is performed, leading to simultaneous silicidation of the diffusion region, the gate, and the silicon spacer. The resulting local interconnect electrically connects the gate and the diffusion region.

Abstract: A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

Abstract: A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.

Abstract: A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: A semiconductor device includes an insulated gate electrode pattern formed on a well region. The semiconductor device further includes a sidewall spacer formed on sidewalls of the gate electrode pattern. A source region and a drain region are formed adjacent opposite sides of the gate pattern. In accordance with one embodiment of the present invention, one of the source or drain regions includes a first-concentration impurity region formed under the sidewall spacer. The semiconductor device further includes a silicide layer formed within the well region wherein at least a part of the silicide layer contacts a portion of the well region to bias the well region. A method of manufacturing the semiconductor device is also provided.

Abstract: A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region formed in a semiconductor body. The gate electrode is a component of a strip-shaped word line. Source and drain regions are disposed between gate electrodes of adjacent memory cells. Source regions are provided with polysilicon layers, in the form of a strip, as common source lines. Drain regions are connected as bit lines through polysilicon fillings to metallic interconnects applied to the top face of the semiconductor body.

Abstract: Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: It is a purpose of the invention to provide a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors having minute size and improved performance and uniformity. The source contact resistance is set in a value smaller than that of the drain contact resistance by making the diameter of a source contact of an insulated gate field effect transistor larger than that of the drain contact, so as to improve the current driving capability of the transistor and to reduce the variation in the capability.

Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

Abstract: A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate and then patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the exposed surface of the device region. A conductive layer is formed on the gate dielectric layer and then patterned to form a horizontal surround gate surrounding the device region. A source/drain region is formed in a portion of the substrate adjacent to the device region.

Abstract: A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.

Abstract: In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share the common gate length direction, and are arranged in the same pitch. The first gate electrodes and the second gate electrodes are all made to extend, in the gate width direction, beyond the longest active region width. With such a configuration, it is possible to provide a semiconductor device having a pattern structure that will not cause performance degradation of transistors when designing a semiconductor integrated circuit within a semiconductor device.

Abstract: A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode and the silicon layers and contain respective voids.