Abstract: A method of controlling an etch-pattern density of a polysilicon layer includes depositing polysilicon on a wafer. The method includes determining polysilicon-etch regions that include DMOS source regions within circuit-device areas of the wafer. The method includes calculating an etch area of the polysilicon-etch regions and then comparing the calculated etch area of the polysilicon-etch regions to a predetermined minimum etch area. If the calculated etch area is less than a predetermined threshold, the method adds polysilicon-etch regions within non-circuit-device areas to the determined polysilicon-etch regions within the circuit-device areas until the comparing step results in the calculated etch area of the polysilicon-etch regions being greater than the predetermined minimum etch area. The method includes etching the polysilicon from the polysilicon-etch regions in both the circuit-device areas and the non-circuit-device areas.

Abstract: According to one embodiment, a transistor includes a first electrode, a second electrode, a current path between the first and second electrodes, the current path including an oxide semiconductor layer, a control terminal which controls an on/off action of the current path, an insulating layer between the control terminal and the oxide semiconductor layer, a first oxide layer between the first electrode and the oxide semiconductor layer, the first oxide layer being different from the oxide semiconductor layer, and a second oxide layer between the second electrode and the oxide semiconductor layer, the second oxide layer being different from the oxide semiconductor layer.

Abstract: A transistor includes: a semiconductor substrate; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate; a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes; a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; and a ground pad on the semiconductor substrate and connected to both ends of the metal wiring.

Abstract: A layout of a random access memory is provided. The layer comprises a first sub-layout having a first pattern including a first number (N1) of first patterns and an adjacent second pattern having a second number (N2) of second patterns; a second sub-layout having a first gate pattern and a second gate pattern; and an interchangeable third sub-layout having covering patterns variable for forming different static random access memory when used with the first sub-layout and the second sub-layout.

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor.

Abstract: [Problem] There is demand for chip resistors that are compact and that have high resistivity. [Solution] A chip resistor (100) has a substrate (11), a first connection electrode (12) and a second connection electrode (13) that are formed on the substrate (11), and a resistor network that is formed on the substrate (11) and that has ends one of which is connected to the first connection electrode (12) and the other one of which is connected to the second connection electrode (13). The resistor network is provided with a resistive circuit. The resistive circuit has a resistive element film line (103) that is provided along inner wall surfaces of trenches (101). The resistive element film line (103) extending along the inner wall surfaces of the trenches (101) is long and has a high resistivity as a unit resistive element. [Effect] The resistivity of the chip resistor (100) as a whole can be increased.

Abstract: A semiconductor device includes a fin-shaped silicon layer on a silicon substrate, and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, where a pillar diameter of the pillar-shaped silicon layer is equal to a fin width of the fin-shaped silicon layer, and where the pillar diameter and the fin width parallel to the surface. A first diffusion layer is in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer, and a second diffusion layer is in an upper portion of the pillar-shaped silicon layer. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and a contact is on the second diffusion layer.

Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.

Abstract: Fabrication methods and structure include: providing a wafer with at least one fin extended above a substrate in a first region, and at least one fin extended above the substrate in a second region of the wafer; forming a gate structure extending at least partially over the at least one fin to define a semiconductor device region in the first region; implanting a dopant into the at least one fin in the first region and into the at least one fin in the second region of the wafer, where the implanting of the dopant into the at least one fin of the second region modulates a physical property of the at least one fin to define a resistor device region in the second region; and disposing a conductive material at least partially over the at least one fin in the first region and over the at least one fin in the second region of the wafer, in part, to form a source and drain contact in the first region, and a fin-type metal-semiconductor resistor in the second region.

Abstract: Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

Abstract: A power semiconductor package includes a substrate having a plurality of metal leads, a power semiconductor die attached to a first one of the leads and a magnetic field sensor integrated in the same power semiconductor package as the power semiconductor die and positioned in close proximity to a current pathway of the power semiconductor die. The magnetic field sensor is operable to generate a signal in response to a magnetic field produced by current flowing in the current pathway, the magnitude of the signal being proportional to the amount of current flowing in the current pathway.

Abstract: A semiconductor package includes a semiconductor die attached to a substrate and a magnetic field sensor included as part of the same semiconductor package as the semiconductor die and positioned in close proximity to a current pathway of the semiconductor die so that the magnetic field sensor can sense a magnetic field produced by current flowing in the current pathway. The magnetic field sensor includes a first magnetic field sensing component galvanically isolated from the current pathway and positioned so that a magnetic field produced by current flowing in the current pathway impinges on the first magnetic field sensing component in a first direction. The magnetic field sensor also includes a second magnetic field sensing component galvanically isolated from the current pathway and positioned so that the magnetic field impinges on the second magnetic field sensing component in a second direction different than the first direction.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.

Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Abstract: A semiconductor device of an embodiment includes: an SiC layer; a gate insulating film provided on a surface of the SiC layer, the gate insulating film including an oxide film or an oxynitride film in contact with the surface of the SiC layer, the oxide film or the oxynitride film containing at least one element selected from B, Al, Ga (gallium), In, Sc, Y, La, Mg, Ca, Sr, and Ba, a concentration peak of the element in the gate insulating film being on the SiC side of the gate insulating film, the concentration peak of the element being in the oxide film or the oxynitride film, the gate insulating film having a region with a concentration of the element being not higher than 1×1016 cm?3 on the opposite side to the SiC layer with the concentration peak; and a gate electrode on the gate insulating film.

Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.

Abstract: A semiconductor structure includes a resistor on a substrate formed substantially simultaneously with other device elements, such as one or more transistors. A diffusion barrier layer deposited on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor in a substantially similar manner as that used to form the gate of the transistor. The filler material is removed.

Abstract: At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer. A mask layer is applied over the conductive line structures, and is lithographically patterned to form opening therein. Portions of the conductive line structures are removed from underneath the openings in the patterned mask layer to form via cavities. The via cavities are vertically extended through the at least one via level dielectric layer employing a combination of the mask layer and the at least one line level dielectric layer as an etch mask. At least one conductive material can be deposited in the via cavities to form conductive via structures, which, in conjunction with the conductive line structures, constitute integrated line and via structures.

Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.

Abstract: A fuse circuit includes a substrate, a top semiconductor layer doped a first conductivity type having a well doped a second conductivity type formed therein including a well contact. A field dielectric layer (FOX) is on the semiconductor layer. A fuse is on the FOX within the well including a fuse body including electrically conductive material having a first and second fuse contact. A transistor is formed in the semiconductor layer including a control terminal (CT) with CT contact, a first terminal (FT) with FT contact, and a second terminal (ST) with a ST contact. A coupling path is between the CT contact and well contact, a first resistor is coupled between the FT contact and CT contact, and a coupling path is between the ST contact and the first fuse contact.

Abstract: A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: An electronic device includes a first substrate including a first electrode formed on a surface of the first substrate, an electronic component mounted on another surface of the first substrate, a second substrate placed on the first substrate via the electronic component, and a shield disposed between the first substrate and the second substrate.

Abstract: Methods for forming integrated graphite-based structures with interconnections between leads and graphene layers are provided. A substrate is patterned to form a plurality of elements on the substrate. A trench separates a first element from an adjacent element in the plurality of elements. A lead is deposited on a side wall of the first element, and a layer from the top of the first element is removed to expose a portion of the lead. Both the deposition of the lead and removal of a layer from the top of the first element are conducted before generation of graphene layers on the top of the first element and the bottom of the trench. Thus, an integrated graphite-based structure having spatially isolated but electrically connected graphene layers is formed.

Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Abstract: Identifying marks are often used for authentication and tracking purposes with various types of articles, but the marks themselves can sometimes be subject to replication or removal by an outside entity, such as a person or group having malicious intent. This can make it easier for an outside entity to produce a counterfeit article or to sell a stolen article. Carbon nanotubes and other carbon nanomaterials can be used to form identifying marks that are not visible to the naked eye, thereby making the marks more difficult for an outside entity to tamper with. Various articles can include an identifying mark that is localized and not visible to the naked eye, the identifying mark being electrically conductive and containing a carbon nanomaterial. By electrically interrogating the article, such as through spatially measuring eddy currents about the article, the marks can be located and authenticated.

Abstract: Provided is a semiconductor device including a substrate, first and second gate structures provided on the substrate, a source/drain region provided adjacent to the first gate structure, an interlayered insulating layer provided on the substrate to cover the source/drain region and the first and second gate structures, a source/drain contact hole penetrating the interlayered insulating layer and exposing the source/drain region, a trench formed in the interlayered insulating layer to expose a top surface of the second gate structure, a source/drain contact plug provided in the source/drain contact hole to be in contact with the source/drain region, and a resistor pattern provided in the trench to be in contact with a top surface of the second gate structure.

Abstract: An imaging device which is highly stable to irradiation with radiations such as X-rays and can inhibit a decrease in electrical characteristics is provided. The imaging device obtains an image using radiations such as X-rays and includes pixel circuits which are arranged in a matrix and which a scintillator overlaps. Each of the pixel circuits includes a switching transistor whose off-state current is extremely low and a light-receiving element. A shielding layer formed using a metal material and the like overlaps the transistor and the light-receiving element. With the structure, an imaging device which is highly stable to irradiation with radiations such as X-rays and can inhibit a decrease in electrical characteristics can be provided.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.

Abstract: A variable inductor includes a spiral inductor, a loop conductor, and a switch for opening or short-circuiting an end of the loop conductor. The loop conductor is formed in a direction perpendicular to the spiral inductor and is used for adjusting the inductance value of the spiral inductor by opening or short-circuiting the end of the loop conductor by the switch.

Abstract: An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (STI) feature of a first width and a second STI feature of a second width in a semiconductor substrate. The first width is less than the second width. The first STI feature has an etch-resistance less than that of the second STI feature.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a doped substrate, a gate structure, a source, a drain and a field doped region. The source and the drain are in the doped substrate on opposing sides of the gate structure respectively. The field doped region has a conductivity type opposite to a conductivity type of the source and the drain. The field doped region is extended from the source to be beyond a first gate sidewall of the gate structure but not reach a second gate sidewall of the gate structure opposing to the first gate sidewall.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state, wherein the non-ohmic element includes a first silicon germanium region in the silicon portion.

Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.

Abstract: Provided are a multi-layer interconnection structure and a manufacturing method thereof. The multi-layer interconnection structure includes a substrate; a first wiring on the substrate; an interlayer insulation layer on the first wiring; a second wiring on the interlayer insulation layer; and a via contact including at least one conductive filament penetrating through the interlayer insulation layer between the second wiring and the first wiring to be electrically connected to the first wiring and the second wiring.

Abstract: Identifying marks are often used for authentication and tracking purposes with various types of articles, but they can sometimes be subject to replication or removal by an outside entity, such as a person or group having malicious intent. Carbon nanotubes and other carbon nanomaterials can be used to form identifying marks that are not visible to the naked eye, thereby making the marks more difficult for an outside entity to tamper with. Various articles can include an identifying mark that is not visible to the naked eye, the identifying mark containing a nanomaterial that includes a plurality of carbon nanotubes with a registered distribution of chiralities. The registered distribution of chiralities can be further tailored to increase the level of security provided by the mark.

Abstract: A method of fabricating a semiconductor apparatus includes forming an insulating layer on a semiconductor substrate, forming a source post in the insulating layer, and forming a semiconductor layer over the source post and the insulating layer.

Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.

Abstract: Semiconductor packages with air core inductors (ACIs) having metal-density layer units of fractal geometry are described. In an example, an inductor structure includes a stack of metal loops. One or more input terminals is coupled to the stack of metal loops. One or more output terminals is coupled to the stack of metal loops. One or more metal-density layer units is disposed above and over the stack of metal loops. At least one of the metal-density layer units has a fractal geometry.

Abstract: A semiconductor device includes a semiconductor body of a first semiconductive material. A transistor is disposed in the semiconductor body. The transistor includes source and drain regions of a second semiconductive material embedded in the semiconductor body. A resistor overlies a top surface of the semiconductor body and is laterally spaced from the transistor. The resistor is formed from the second semiconductive material.

Abstract: A nitride-based semiconductor device includes a buffer layer on a substrate, a nitride-based semiconductor layer on the buffer layer, at least one ion implanted layer within the nitride-based semiconductor layer, and a channel layer on the nitride-based semiconductor layer.

Abstract: A packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor.

Abstract: A field plate of a semiconductor device is provided with i) an insulating film that is formed on a surface of the semiconductor substrate, and includes a plurality of first regions, one for each of a plurality of FLR layers, that contact the layers and are arranged at intervals in a radial direction, and a plurality of second regions, one for each of the first regions, that are adjacent to the first regions in the radial direction, and ii) a plurality of first conductive films that are formed, one for each of the layers, inside of the insulating film, are arranged at intervals in the radial direction along the layers when a semiconductor substrate is viewed from above, and that are electrically connected to the layers. A thickness of at least a portion of the second regions is thicker than a thickness of the first regions.

Abstract: An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials.

Abstract: An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed at second ends of the plurality of first transistors along a second direction.

Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.

Abstract: A semiconductor structure including a high-voltage transistor; voltage dropping circuitry, at least part of which is overlapping the high-voltage transistor; at least one intermediate contact point to the voltage dropping circuitry, connected to at least one intermediate position between a first and a second end of the voltage dropping circuitry; and at least one external connection connecting the at least one intermediate contact point to outside of the semiconductor structure.

Abstract: Methods for a low voltage antifuse device and the resulting devices are disclosed. Embodiments may include forming a plurality of fins above a substrate, removing a portion of a fin, forming a fin tip, forming a first area of a gate oxide layer above at least the fin tip, forming a second area of the gate oxide layer above a remaining portion of the plurality of fins, wherein the first area is thinner than the second area, and forming a gate over at least the fin tip to form an antifuse one-time programmable device.

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.