Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.

Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

Abstract: An RF power transistor package includes an input lead, an output lead, and an RF power transistor having a gate, a drain and a defined gain over an RF frequency range for which the RF power transistor is configured to operate. The RF power transistor package further includes a transformer electrically isolating and inductively coupling the gate of the RF power transistor to the input lead. The transformer is configured to block signals below the RF frequency range of the RF power transistor and pass signals within the RF frequency range of the RF power transistor. The RF power transistor package also includes a DC feed terminal for providing DC bias to the gate of the RF power transistor.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract: A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

Abstract: The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Abstract: A semiconductor chip having a P? substrate and an N+ epitaxial layer grown on the P? substrate is shown. A P? circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat.

Abstract: A thin film transistor (TFT) array substrate includes a TFT including an active layer, a gate electrode, a source electrode, a drain electrode, a first gate insulating layer and a second gate insulating layer formed between the active layer and the gate electrode, and an interlayer insulating layer formed between the gate electrode and the source electrode and the drain electrode; a pixel electrode formed in an opening of the interlayer insulating layer, the pixel electrode including transparent conductive oxide; a translucent electrode formed in a region corresponding to the pixel electrode, between the first gate insulating layer and the second gate insulating layer; and a capacitor including a lower electrode formed from the same layer as the active layer, and an upper electrode formed from the same layer as the translucent electrode.

Abstract: Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.

Abstract: An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials.

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

Abstract: A programmable memory is provided. The programmable memory has a select transistor that includes a gate, a source, and a drain. An anti-fuse device is connected to a drain region of the select transistor. The anti-fuse device includes a dielectric layer on an upper substrate of the drain region, a polysilicon layer on the dielectric layer, and an anti-fuse electrode line in contact with the drain region. The dielectric layer breaks down and the anti-fuse device is programmed when the select transistor is turned on and a high voltage is applied through the anti-fuse line.

Abstract: An OTP anti-fuse memory array without additional selectors and a manufacturing method are provided. Embodiments include forming wells of a first polarity in a substrate, forming a bitline of the first polarity in each well, and forming plural metal gates across each bitline, wherein no source/drain regions are formed between the metal gates.

Abstract: Semiconductor devices are provided. A semiconductor device may include a transistor area and a resistor area. The transistor area may include a gate structure. The resistor area may include an insulating layer and a resistor structure on the insulating layer. A top surface of the gate structure and a top surface of the resistor structure may be substantially coplanar.

Abstract: Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).

Abstract: Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.

Abstract: In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.

Abstract: An electrical device is provided that includes a substrate having an upper semiconductor layer, a buried dielectric layer and a base semiconductor layer. At least one isolation region is present in the substrate that defines a semiconductor device region and a resistor device region. The semiconductor device region includes a semiconductor device having a back gate structure that is present in the base semiconductor layer. Electrical contact to the back gate structure is provided by doped epitaxial semiconductor pillars that extend through the buried dielectric layer. An epitaxial semiconductor resistor is present in the resistor device region. Undoped epitaxial semiconductor pillars extending from the epitaxial semiconductor resistor to the base semiconductor layer provide a pathway for heat generated by the epitaxial semiconductor resistor to be dissipated to the base semiconductor layer. The undoped and doped epitaxial semiconductor pillars are composed of the same epitaxial semiconductor material.

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

Abstract: There are disclosed impedance matching networks and technique for impedance matching to microwave power transistors. Distributed capacitor inductor networks are used so as to provide a high degree of control and accuracy, especially in terms of inductance values, in comparison to existing lumped capacitor arrangements. The use of bond wires is reduced, with inductance being provided primarily by microstrip transmission lines on the capacitors.

Abstract: Disclosed is a semiconductor device, an electronic circuit, and a method. The semiconductor device includes a semiconductor body; at least one transistor cell including a source region, a drift region, a body region separating the source region from the drift region, and a drain region in the semiconductor body, and a gate electrode dielectrically insulated from the body region by a gate dielectric; a source node connected to the source region and the body region; a contact node spaced apart from the body region and the drain region and electrically connected to the drain region; and a rectifier element formed between the contact node and the source node.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device.

Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.

Abstract: A cascode switch device is provided. The cascode switch device includes a high voltage (HV) transistor having a first drain electrode, a first source electrode, and a first gate electrode and a low voltage (LV) transistor cascoded with the HV transistor and having a second drain electrode, a second source electrode, and a second gate electrode. A first ratio of an equivalent capacitance of a second drain-to-source capacitance between the second drain and the second source electrodes, a gate-to-drain capacitance between the second gate and the second drain electrodes and a gate-to-source capacitance between the first gate and the first source electrodes to a first drain-to-source capacitance between the first source and the first drain electrodes being based on a second ratio of a drain voltage of the HV transistor to a break-down voltage of the LV transistor so as to provide voltage protection for the LV transistor.

Abstract: Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode.

Abstract: Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area.

Abstract: An anti-fuse includes a single transistor formed over an active region of a semiconductor substrate and entering a fuse cut state by a threshold voltage being varied upon receiving a voltage applied thereto. The single transistor includes a device isolation film formed in the semiconductor substrate to define the active region, and a liner trap film formed between the device isolation film and the active region in such a manner that electrons are trapped in the liner trap film upon receiving the voltage.

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. A surface portion of the substrate extending from the source to the drain has an asymmetric dopant concentration profile.

Abstract: A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).

Abstract: An integrated circuit product is disclosed that includes a resistor body and an e-fuse body positioned on a contact level dielectric material, wherein the resistor body and the e-fuse body are made of the same conductive material, a first plurality of conductive contact structures are coupled to the resistor body, conductive anode and cathode structures are conductively coupled to the e-fuse body, wherein the first plurality of conductive contact structures and the conductive anode and cathode structures are made of the same materials.

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate and a gate structure over a top surface of the substrate. The MOSFET further includes a source in the substrate on a first side of the gate structure and a drain in the substrate on a second side of the gate structure opposite the first side. The gate structure includes a variable thickness gate dielectric layer. The variable thickness gate dielectric layer includes a first portion closest to the drain, the first portion having a first thickness. The variable thickness gate dielectric layer further includes a second portion distal from the drain, the second portion having a second thickness less than the first thickness.

Abstract: An integrated circuit includes a transistor. The transistor includes a first gate dielectric structure over a substrate, a work-function layer over the first gate dielectric structure, a conductive layer over the work-function layer, and a source/drain (S/D) region adjacent to each sidewall of the first gate dielectric structure. Additionally, the integrated circuit includes a resistor structure. The resistor structure further includes a first doped semiconductor layer over the substrate, wherein a top surface of the resistor structure is substantially planar with a top surface of the transistor.

Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: A semiconductor device includes a substrate having a transistor area, a gate structure disposed on the transistor area of the substrate, a first interlayer insulating layer covering the gate structure, a blocking pattern disposed on the first interlayer insulating layer, and a jumper pattern disposed on the blocking pattern. The jumper pattern includes jumper contact plugs vertically penetrating the first interlayer insulating layer to be in contact with the substrate exposed at both sides of the gate structure, and a jumper section configured to electrically connect the jumper contact plugs.

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

Abstract: The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.

Abstract: An integrated power module having a dielectric substrate, a source conductor trace formed on the dielectric substrate, a drain conductor trace formed on the dielectric substrate, a gate conductor trace formed on the dielectric substrate, a transistor chip having a top surface and a bottom surface connected to the drain conductor trace, a back-contact resistor having a flat planar structure with a top surface and a bottom surface connected to the gate conductor trace, and a first wire bond connecting the top surface of the transistor chip to the top surface of the back-contact resistor.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.