Abstract: A semiconductor device is provided with a memory cell. The semiconductor device includes a first gate-gate electrode layer, a second gate-gate electrode layer, a first drain-drain wiring layer, a second drain-drain wiring layer, a first drain-gate wiring layer and a second drain-gate wiring layer. The first drain-gate wiring layer and an upper layer and a lower layer of the second drain-gate wiring layer are located in different layers, respectively.

Abstract: A conductor film and a cap insulating film are sequentially formed, and a laminated film constituted of the cap insulating film and the conductor film is patterned, and then a gate electrode is formed. Next, source and drain diffusion regions are formed, and a first silicon nitride film is formed on a sidewall of the laminated film, and then a second silicon nitride film is formed on an entire surface, and further a silicon oxide film is deposited. Next, the silicon oxide film is left between the gate electrodes, and the second silicon nitride film on the laminated film is removed, and the cap insulating film left above the gate electrode is removed, and a metal silicide film is formed on a surface of the gate electrode, and then a third silicon nitride film is left on the gate electrode.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.

Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Abstract: An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.

Abstract: A semiconductor integrated circuit device having a capacitor element including a lower electrode provided over an element isolation region of a principal surface of a semiconductor substrate, and an upper electrode provided over the lower electrode via a dielectric film interposed therebetween, has oxidation resistant films between the element isolation region of the principal surface of the semiconductor substrate and the lower electrode, and between the lower electrode and the upper electrode.

Abstract: A resin-sealed semiconductor device is provided which allows unwanted air to be bled out steadily and readily from the space defined between the resistor of a plate-like shape and the insulating substrate in the resin sealing step. The resin-sealed semiconductor device includes a resistor of a plate-like form anchored at both ends to the upper main surface of a substrate thereof. A space is provided between the resistor and the substrate. The primary components including the resistor mounted on the substrate are sealed with a curing resin material. In particular, the resistor has an aperture provided in a portion thereof, which is opposite to the substrate and defines the space with the substrate, for communication between the space and the upper side of the resistor.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A semiconductor device has a semiconductor element formed on a semiconductor substrate and a first insulating film having contact holes. The semiconductor element has a gate electrode, a source region and a drain region. The semiconductor element also has metal wirings each for connecting a respective one of the contact holes to the gate electrode, the source region and the drain region of the semiconductor element. A second insulating film is formed on the first insulating film and the metal wirings. The second insulating film has a chemical-mechanical polished portion defining a flattened upper surface of the second insulating film. Resistors are formed on and are disposed directly in contact with the flattened upper surface of the second insulating film and are connected in series to form a bleeder resistor circuit or a ladder circuit.

Abstract: A semiconductor device including a resistor and a method of forming the same. In the semiconductor device, a conductive pattern, which connects source regions, and a resistor are formed of the same material, which can be polysilicon. In the method, the conductive pattern and the resistor are simultaneously formed. Thus, it is possible to obtain a constant sheet resistance without an additional photo mask.

Abstract: A method for fabricating resistors within a semiconductor integrated circuit device is disclosed. A resistor is fabricated by first depositing a passivation layer on a semiconductor substrate having multiple transistors previously formed thereon. Next, a first contact window and a second contact window are formed through the first passivation layer at a first contact location and a second contact location, respectively. The first and second contact windows are then filled with metal, such as tungsten, and the metal at the first and second contact windows is planarized to form a first bottom contact and a second bottom contact, respectively. A resistive film, such as polysilicon, subsequently deposited over the first passivation layer. Next, a second passivation layer is formed over the resistive film. Finally, a first top contact and a second top contact are formed to respectively connect the first bottom contact and the second bottom contact to the resistive film.

Abstract: A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal oxide material having a high dielectric constant, and a second layer formed on the first layer. The second layer is formed of a metal silicate material having a dielectric constant lower than the dielectric constant of the first layer. A semiconductor transistor incorporating the multilayer dielectric film is also provided.

Abstract: It is an object to provide a semiconductor device in which a resistance value of a resistor formed by a silicon film is changed with difficulty. A resistor (31) is formed by an amorphous silicon film, and silicides (32a) and (32b) are formed in connecting portions of contact plugs (5a) and (5b) in a surface portion thereof. Since the resistor (31) is the amorphous silicon, a hydrogen atom is bonded with more difficulty as compared with the case in which polycrystalline silicon is used for a material of the resistor. Thus, it is possible to obtain a semiconductor device in which a resistance value of the resistor formed by the silicon film is changed with difficulty. Moreover, the suicides (32a) and (32b) are formed in the connecting portions of the contact plugs (5a) and (5b). Therefore, when contact holes for the contact plugs (5a) and (5b) are to be formed on a first interlayer insulating film (4a) by etching, the resistor (31) is etched with difficulty.

Abstract: The present invention provides a high dopant concentration diffused resistor, a method of manufacture therefor, and an integrated circuit including the same. In one embodiment of the invention, the high dopant concentration diffused resistor includes a doped tub located over a semiconductor substrate and a doped resistor region located in the doped tub, the doped resistor region forming a junction within the doped tub. In a related embodiment, the high dopant concentration diffused resistor further includes first and second terminals each contacting the doped tub and the doped resistor region, wherein the first and second terminals cause the doped tub and doped resistor region to have a zero potential difference at any point across the junction when a voltage is applied to the first and second terminals.

Abstract: A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.

Abstract: A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p-type deep guard ring and a heavily doped p-type shallow impurity region are formed in said lightly doped semiconductor layer in such a manner that a diode has a major p-n junction between the heavily doped n-type impurity region and the heavily doped p-type shallow impurity region and other p-n junction between the lightly doped n-type semiconductor layer and the lightly doped p-type guard ring, wherein the other p-n junction is wider in area than the major p-n junction so that the breakdown voltage is adjustable without increase of parasitic capacitance dominated by the other p-n junction.

Abstract: A semiconductor device includes metal silicide films formed on the surface of a source-drain region and of a gate electrode. On the metal silicide films, impurity regions are formed of a conductivity type opposite to the conductivity type of the source-drain region. This structure enables the contact resistance at the interfaces between contact layers and the metal silicide films even when the semiconductor integrated circuit is scaled down, thereby providing a high-speed semiconductor device and its manufacturing method.

Abstract: A semiconductor device comprises a MOS transistor and a resistor. The resistor has a P-type resistor formed from a P-type semiconductor, an N-type resistor formed from an N-type semiconductor and disposed adjacent the P-type resistor, and an insulating film disposed between the P-type and N-type resistors. The P-type resistor is arranged at the low potential side of the semiconductor device and the N-type resistor is arranged at the high potential side thereof. A portion of the insulating film between the P-type and N-type resistors is made electrically conductive by irradiating the portion with a laser beam to destroy the insulating property thereof to thereby achieve conductivity between the P-type and N-type resistors. A gate electrode of the MOS transistor is formed of a P-type polysilicon thin film having the same high concentration impurity as that of the region where the P-type resistor is in contact with a metal wiring, thereby enhancing the current driving capacity of a driver MOS.

Abstract: To improve performance, a capacitor is provided between storage nodes of an SRAM and a device having an analog capacitor on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are formed over the local wiring LIc.

Abstract: A voltage nonlinear resistor is composed of an aggregate of silicon carbide particles doped with impurities, in which oxygen and at least one of aluminum and boron are diffused in the vicinity of the surfaces of the silicon carbide particles, the diffusion length of the oxygen is about 100 nm or less from the surfaces of the silicon carbide particles, and the diffusion length of at least one of the aluminum and the boron is in the range of about 5 to 100 nm from the surfaces of the silicon carbide particles. A method for fabricating a voltage nonlinear resistor and a varistor using a voltage nonlinear resistor are also disclosed.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: An isolation is formed in a part of a P-well of a semiconductor substrate. A resistor film as a first conductor member is formed on the isolation. An insulating film covering the resistor film except for contact formation regions and an upper electrode film as a second conductor member are formed simultaneously with the formation of a gate electrode and a gate oxide film. Silicide films of a refractory metal are formed on the respective surfaces of the gate electrode, N-type high-concentration diffusion layers, the contact formation regions of the resistor film, and the upper electrode film. By utilizing a salicide process, a resistor and an inductor each occupying a small area can be formed without lowering the resistance of the resistor film. A capacitor, the resistor, and like component are selectively allowed to function.

Abstract: A semiconductor device is provided, which is provided with a high resistance to surge currents. The semiconductor device comprises three N+ diffusion layers 4a, 4b, and 4c in a region surrounded by an element-separating insulating film 3a. The N+ diffusion layer 4a forms a source diffusion layer of an N-channel MOS transistor 11a, the N+ diffusion layer 4c forms a source diffusion layer of another N-channel MOS transistor 11b, and the N+ diffusion layer 4b forms drain diffusion layers for two N-channel MOS transistors 11a and 11b. That is, respective drain diffusion layers of two N-channel MOS transistors are shared. Furthermore, a ring-shaped mask insulating film 18 is formed on the N+ diffusion layer 4b. A silicide layer 6b is formed on the N+ diffusion layer 4b except the area covered by the ring-shaped mask insulating film 18.

Abstract: A semiconductor device includes an NMOSFET and a PMOSFET. Each MOSFET includes first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like, a channel region formed between the first and second impurity diffusion layers, a gate insulation layer at least formed on the channel region, and a gate electrode formed on the gate insulation layer. The gate electrode includes a tantalum nitride layer in a region in contact with at least the gate insulation layer. The semiconductor device exhibits high current drive capability and can be manufactured at high yield.

Abstract: An integrated static random access memory device includes four transistors and two resistors defining a memory cell. The four transistors are in a semiconductor substrate and are mutually interconnected by a local interconnect layer. The local interconnect layer is under a first metal level and a portion of the local interconnect layer defines above the substrate a base metal level. The two resistors extend in contact with a portion of the local interconnect layer between the base metal level and the first metal level.

Abstract: A circuit-containing photodetector is provided which can have a high sensitivity and response to light of a short wavelength and can be manufactured in a good yield. The circuit-containing photodetector includes a semiconductor substrate, a semiconductor layer formed thereon, and a conductive impurity region formed in the semiconductor layer for transmitting a signal. In the semiconductor layer, a trench is formed to have a depth to reach the substrate. An impurity region of a photodetector element is formed at the surface of the semiconductor substrate exposed at the bottom of the trench. A signal processing circuit for processing an electric signal from the photodetector element is formed on the semiconductor layer. The conductive impurity region for transmitting the electric signal from the photodetector element is formed to extend from the bottom of the trench to the upper surface of the semiconductor layer.

Abstract: It is intended to provide a semiconductor device in which a fuse required conventionally is omitted and an initial resistance value can be maintained even under stress imposed due to packaging or the like, a high-accuracy bleeder resistance circuit that can maintain an accurate voltage division ratio, and a high-accuracy semiconductor device with such a bleeder resistance circuit, for example, a voltage detector or a voltage regulator. In a semiconductor device with a resistor, the resistor includes a P-type resistor made of a P-type semiconductor and an N-type resistor made of an N-type semiconductor which are combined to form one body, and the P-type resistor and the N-type resistor are placed on low and high potential sides, respectively. The P-N junction is irradiated with a laser beam or the like, whereby rectification is damaged to allow conduction.

Abstract: Terminal regions of source/drain zones of an MOS transistor are configured over the substrate in the form of conductive structures, are separated from the substrate by separating layers, and exhibit a larger horizontal cross-section than doped regions forming the source/drain zones that are arranged in the substrate.

Abstract: A Static Random Access Memory (SRAM) device includes at least a transfer transistor, a driving transistor and a load resistor which are commonly connected to a node. A well has a first conductive type, and is placed on a substrate. A first impurity region has a second conductive type opposite to the first conductive type, and is placed in the well. A second impurity region has the first conductive type and has higher impurity concentration than the well, and is placed at a lower portion of the first impurity region. The node is composed of at least the first impurity region and the second impurity region.

Abstract: Gate electrodes are formed on an element formation region of a silicon substrate. A sidewall insulation film having a width at least half the distance between the gate electrodes is formed on both side faces of respective gate electrodes. The distance L between the gate electrode and another gate electrode is greater than the distance between the gate electrodes. An n+ source region is formed in self-alignment at this region. Accordingly, a semiconductor device is obtained that has the symmetry of the characteristics of access transistors ensured and that has the contact resistance in the storage node contact reduced.

Abstract: A semiconductor device capable of easily setting the sheet resistance of a resistive element or the like to an arbitrary value is obtained. This semiconductor device comprises a first silicide film formed on a first silicon region and a second silicide film, formed on a second silicon region, consisting of the same silicide material as the first silicide film and differing from the first silicide film in film quality to have a sheet resistance value different from that of the first silicide film. When an impurity is introduced into the second silicide film itself so that the second silicide film differs from the first silicide film in film quality in this case, for example, a second silicide film having an arbitrary high sheet resistance value can be obtained by controlling the type of and an introduction condition for the impurity.

Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

Abstract: A thin film transistor array substrate includes a substrate, a gate wire with a gate line and a gate electrode formed on the substrate, a gate insulating layer covering the gate wire, and a semiconductor pattern formed on the gate insulating layer. A data wire is formed on the gate insulating layer and the semiconductor pattern with a data line, and a source electrode and a drain electrode. The data wire bears a multiple-layered structure having a metallic layer and an intermetallic compound layer. A protective layer is formed on the data wire and the semiconductor pattern. A pixel electrode is formed on the protective layer while contacting the drain electrode through a contact hole.

Abstract: A voltage nonlinear resistor is composed of an aggregate of silicon carbide particles doped with impurities, in which oxygen and at least one of aluminum and boron are diffused in the vicinity of the surfaces of the silicon carbide particles, the diffusion length of the oxygen is about 100 nm or less from the surfaces of the silicon carbide particles, and the diffusion length of at least one of the aluminum and the boron is in the range of about 5 to 100 nm from the surfaces of the silicon carbide particles. A method for fabricating a voltage nonlinear resistor and a varistor using a voltage nonlinear resistor are also disclosed.

Abstract: A semiconductor device comprises a first insulating layer formed on a substrate; a resistor layer formed on the first insulating layer and having a prescribed electrical resistance; a second insulating layer formed on the resistor layer; a plurality of wirings electrically connected, at positions spaced apart from each other on the resistor layer, to the resistor layer through holes formed in the second insulating layer. Further the semiconductor device comprises a heat storage layer formed in the vicinity of the resistor layer for storing heat generated when a current flows in the resistor layer Hence, even if a large current such as a surge current flows in the resistor layer, heat generated in the resistor layer can be stored in the heat storage layer provided in the vicinity of the resistor layer. Therefore, a stable and reliable semiconductor device free of the breakdown of the resistor layer can be provided.

Abstract: A semiconductor device comprises a first insulating layer formed on a substrate; a resistor layer formed on the first insulating layer and having a prescribed electrical resistance; a second insulating layer formed on the resistor layer; a plurality of wirings electrically connected, at positions spaced apart from each other on the resistor layer, to the resistor layer through holes formed in the second insulating layer. Further the semiconductor device comprises a heat storage layer formed in the vicinity of the resistor layer for storing heat generated when a current flows in the resistor layer.

Abstract: A semiconductor device includes a polysilicon resistor that can suppress variations in resistance value in environments with an ambient temperature higher than room temperature. The resistance value Rcon of a polysilicon contact is reduced to 2% or less of the sum of the resistance value Rcon of the polysilicon contact and the resistance value Rpoly of a polysilicon resistor. Hence, a semiconductor device that is not significantly affected by a variation in the resistance of the polysilicon contact is realized. This device suppresses variations in resistance value in environments with an ambient temperature higher than room temperature.

Abstract: At least one diffusion region exists between a plurality of resistors formed on an element isolation layer, and the plurality of resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal to each other.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. A resistor, a lower plate of an analog capacitor and a gate electrode of a MOS transistor are simultaneously formed over a substrate where an isolation film is formed. Junction region are formed at both sides of the gate in the substrate. A dummy gate electrode over the resistor where a first insulating layer is arranged between the resistor and the dummy gate electrode and an upper plate over the lower plate where a second insulating layer is arranged between the lower and upper plates, are simultaneously formed. A metal silicide layer is then formed over the dummy gate electrode, the resistor, the gate electrode, the junction regions and the lower and upper plates of the analog capacitor.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent energy. As a result, adjacent columnar or needle-like crystals are joined together to form a region having substantially no grain boundaries, i.e., a monodomain region which can substantially be regarded as a single crystal. A semiconductor device is formed by using the monodomain region as an active layer.

Abstract: The present invention generally relates to electrical detection of V-groove width during the fabrication of photosensitive chips, which create electrical signals from an original image, as would be found, for example, in a digital scanner or facsimile machine.

Abstract: An IC card comprises: a plane coil having respective terminal sections; a semiconductor element arranged at a position not overlapping with the plane coil, the semiconductor element having electrode terminals; means for electrically connecting the respective terminal sections of the plane coil to the electrode terminals of the semiconductor element; and a reinforcing frame arranged on a face substantially the same as that of the semiconductor element so that the semiconductor element is surrounded by the reinforcing frame.

Abstract: In a static random access memory cell including two cross-coupled drive MOS transistors and two transfer MOS transistors connected to the drive MOS transistors, a plurality of gate electrodes of the drive MOS transistors and the transfer MOS transistors are formed over a semiconductor substrate, and a plurality of source/drain impurity diffusion regions of the transistors are formed within the semiconductor substrate. A plurality of pocket regions of the same conductivity type as the semiconductor substrate are formed within the semiconductor substrate. Each of the pocket regions is adjacent to the source of one of the drive MOS transistors and beneath the gate electrode thereof. The impurity concentration of the pocket regions is larger than that of the semiconductor substrate.

Abstract: A MOS (Metal Oxide Semiconductor) transistor includes a gate electrode, a drain electrode, and a source electrode. The MOS transistor has an on-state resistance when the MOS transistor is in an ON state. The MOS transistor further includes a specific electrode, wherein the specific electrode connects the source electrode to a power supply section to which a power is supplied. The specific electrode has a resistance substantially identical to the on-state resistance. The specific electrode has a width substantially identical to a width of the gate electrode. The specific electrode and the gate electrode are formed at a same time.

Abstract: A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations.

Abstract: The invention relates to an integrated CMOS circuit for use at high frequencies with active CMOS components (12) and passive components (16, 18, 20). The active CMOS components (12) are formed in a semiconductor substrate (10) which has a specific resistivity in the order of magnitude of k&OHgr;cm. In the semiconductor substrate (10), and under the active CMOS components (12), a buried layer (22) is formed which has a specific resistivity in the order of magnitude of &OHgr;cm. The passive components (16, 18, 20) are formed in or on a layer (14) of insulating material which is arranged on the semiconductor substrate (10). A conducting contact layer (24) is arranged on that surface of the semiconductor substrate (10) which is not facing the layer (14) of insulating material.

Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.

Abstract: An SRAM cell is arranged in a semiconductor device. A metal oxide semiconductor field effect transistor is arranged in the SRAM cell. An interlayer insulating film is formed on the metal oxide semiconductor field effect transistor. A load resistor conductive layer is formed on the interlayer insulating film. In addition, a wiring conductive layer which connects the gate electrode of the metal oxide semiconductor field effect transistor to the load resistor conductive layer is provided. The resistance of the wiring conductive layer is lower than the resistance of the load resistor conductive layer. A side wall is formed between the load resistor conductive layer and the wiring conductive layer.