Abstract: This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data “1” or “0” in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.

Abstract: In a case of a liquid crystal display apparatus, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one insulating film, and a thickness thereof is set to, for example, 30 nm. This TFT has a structure in which LDD regions (low concentration impurity regions) are not provided. A TFT having a CMOS structure, which is driven at a high voltage (18 V), has a gate insulating film constituted by two insulating films having a thickness of, for example, 130 nm in total. In an n-type TFT, a low concentration impurity region is provided on a drain side. A p-type TFT has a structure having no LDD region. A pixel TFT has a gate insulating film constituted by two insulating films, and LDD regions provided in both of its source/drain.

Abstract: A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of ?5V, a select-and-connect circuit supplying the voltages of 5V and ?5V to a memory cell array, a 5 V voltage level detection circuit detecting the voltage derived from the voltage supply circuit, and a ?5 V voltage level detection circuit detecting the voltage derived from the voltage polarity inversion circuit. Absolute values of the voltages detected by the voltage level detection circuits are lower than ever before. This allows a gate insulation film to be thinner. A memory-function film is formed on both sides of a gate electrode in the semiconductor storage device. This also make the gate insulation film thinner. The thin gate insulation film suppresses the short-channel effect, so that each memory element of the memory cell array is miniaturized.

Abstract: A semiconductor device includes a semiconductor substrate. A gate electrode is formed on the semiconductor substrate via a gate insulating film. A source region and a drain region of a first conductivity type are formed on the first side and the second side of the gate electrode, respectively, in the semiconductor substrate. A punch-through stopper region of a second conductivity type is formed in the semiconductor substrate such that the second conductivity type punch-through stopper region is located between the source region and the drain region at distances from the source region and the drain region and extends in the direction perpendicular to the principal surface of the semiconductor substrate. The concentration of an impurity element of the second conductivity type in the punch-through stopper region is set to be at least five times the substrate impurity concentration between the source region and the drain region.

Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: A compact mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines, a plurality of bit lines, and a plurality of MOS-type and diffusion-type memory cells arranged in an array. The memory cells in one column are coupled to one bit line, and the gates of the MOS-type cells in one row are coupled to one word line via contacts, wherein two columns of memory cells share a column of contacts. A MOS-type cell shares its source and drain with two memory cells in the same column, and a diffusion-type cell directly connects with the diffusions of two adjacent memory cells. A constant number of continuous memory cells are grouped as a memory string, wherein the two diffusions of the two terminal memory cells are electrically connected to a bank select transistor and a ground line, respectively.

Abstract: A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

Abstract: A cellularly constructed semiconductor component has a connection electrode, which contact-connects some of the cells, and a connection line, which contact-connects the connection electrode. In which case, in a region at a distance from a connection contact between the connection line and the connection electrode, at least some of the cells are not connected to the connection electrode.

Abstract: There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

Abstract: A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.

Abstract: Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

Abstract: A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract: With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard CMOS process. The standard MOSFET presents an “OFF” state before the burning and an “ON” state with a stable low-resistance path after the burning.

Abstract: A method of deforming a pattern comprising the steps of: forming, over a substrate, a layered-structure with an upper surface including at least one selected region and at least a re-flow stopper groove, wherein the re-flow stopper groove extends outside the selected region and separate from the selected region; selectively forming at least one pattern on the selected region; and causing a re-flow of the pattern, wherein a part of an outwardly re-flowed pattern is flowed into the re-flow stopper groove, and then an outward re-flow of the pattern is restricted by the re-flow stopper groove extending outside of the pattern, thereby to form a deformed pattern with at least an outside edge part defined by an outside edge of the re-flow stopper groove.

Abstract: The present invention is directed to a semi-programmable ASIC using two metals for the metal layers. The semi-programmable ASIC may have a prefabricated first section and a customized second section. The prefabricated first section and the customized second section may each include one or more metal layers. The one or more metal layers included in the prefabricated first section may be used to define undifferentiated sets of electrical and logic elements. An undifferentiated set of electrical and logic elements may be a NAND logic gate, a NOR logic gate, or the like. The one or more metal layers included in the customized second section may be used to define logic functions of the undifferentiated sets of electrical and logic elements.

Abstract: A method and device for manufacturing a mask ROM integrated circuit device to reduce influences of punch through between source and channel regions that output improper program readings. The method includes forming well regions using an implant process on semiconductor substrate and forming a plurality of buried implant regions through first patterned mask. The first patterned mask is formed overlying the semiconductor substrate. Each of the buried implant regions includes a source region and a drain region for each respective memory cell region. The memory cell region is one of a plurality of memory cell regions. The method also forms pocket regions adjacent to a vicinity of each of the buried implant regions within the channel region for each of the memory cell regions. A first pocket region is defined between the channel region and source region and a second pocket region is defined between the channel region and the drain region for each memory cell region.

Abstract: A semiconductor device has a first semiconductor element and a second semiconductor element formed on a semiconductor substrate. The second semiconductor element is operated with a first voltage. The first semiconductor element is operated with a second voltage that is higher than the first voltage. The pairs of impurity regions of the first and second semiconductor elements respectively have first impurity areas and second impurity areas. Each of the first impurity areas have a predetermined impurity concentration and a conductivity type opposite to a conductivity type of the semiconductor substrate. The second impurity areas extend toward their corresponding gates from the first impurity areas. The second impurity areas have a same conductivity type as the first impurity areas and an impurity concentration lower than the concentration of the first impurity area.

Abstract: A method is provided for processing a semiconductor topography. In particular, a method is provided for decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In some embodiments, a width of the first transistor may be larger than a width of the second transistor. In addition or alternatively, the method may include performing a first implantation corresponding to a threshold voltage magnitude above a desired value for the first transistor. The method may further include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of the second transistor. In some embodiments, the method may include introducing dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region simultaneously.

Abstract: A structure of a 2-bit mask ROM device and a fabrication method thereof are provided. The memory structure includes a substrate, a gate structure, a 2-bit coding implantation region, a spacer, a buried drain region, an isolation structure and a word line. The gate structure is disposed on the substrate, while the coding implantation region is located in the substrate under the side of the gate structure. Further, at least one spacer is arranged beside the side of the gate structure and a buried drain region is disposed in the substrate beside the side of the spacer. Moreover, the buried drain region and the coding implantation region further comprise a buffer region in between. Additionally, an insulation structure is arranged on the substrate that is above the buried drain region, while the word lien is disposed on the gate structure.

Abstract: A semiconductor structure 300 comprises a plurality of first track conductors 303, a plurality of second track conductors 304, which are insulated with respect to the first track conductors 303 and form a grid together with these first track conductors 303, and a plurality of third track conductors 307 parallel above the first track conductors 303, which third track conductors 307 partly cover the second track conductors 304 and are insulated with respect thereto, in which semiconductor structure 300, between in each case two adjacent second track conductors 304, there is located an electrical contact 305 between each first track conductor 303 and the corresponding third track conductor 307 which lies above it.

Abstract: The present invention discloses an nF-opening-based mask-programmable read-only memory. Because its openings can be nx (n>1) wider than its address-selection lines, this memory can use less expensive opening mask. Other mask-programmable 3-D memory (3D-M) structures are also disclosed. The present invention makes further improvements to the 3D-M's peripheral circuits. Full-read mode and self-timing can be used to improve the speed and reduce the power consumption.

Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

Abstract: A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P?? blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P?? blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

Abstract: An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate c

Abstract: In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

Abstract: A semiconductor device has at least one high-voltage and low-voltage transistor on a single substrate. The reliability of the high-voltage transistor is enhanced by performing a LDD implantation in only the high-voltage transistor prior to conducting an oxidation process to protect the substrate and gate electrode. After the oxidation process is performed, the low-voltage transistor is subjected to an LDD implantation process. The resultant semiconductor device provides a high-voltage transistor having a deeper LDD region junction depth than the low-voltage transistor, ensuring reliability and performance.

Abstract: A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.

Abstract: An ultraviolet-programmable P-type Mask ROM is described. The threshold voltages of all memory cells are raised at first to make each memory cell to be in a first logic state, in which the channel is hard to switch on, in order to prevent a leakage current. After the bit lines and the word lines are formed, the Mask ROM is programmed by irradiating the substrate with UV light to inject electrons into the ONO layer under the openings to make the memory cells under the openings be in a second logic state.

Abstract: A multi-bit Read Only Memory (ROM) cell has a semiconductor substrate of a first conductivity type with a first concentration. A first and second regions of a second conductivity type spaced apart from one another are in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. The ROM cell has one of a plurality of N possible states, where N is greater than 2. The possible states of the ROM cell are determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost.

Abstract: A silicon nitride read-only-memory structure is provided. The silicon nitride read-only-memory includes a control gate over a substrate, a source region and a drain region in the substrate on each side of the control gate, a charge-trapping layer between the control gate and the substrate and a channel layer in the substrate underneath the charge-trapping layer and between the source region and the drain region. The charge-trapping layer further includes an isolation region. The isolation region partitions the charge-trapping layer into a source side charge-trapping block and a drain side charge-trapping block so that a two-bit structure is formed.

Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.

Abstract: An improved method for forming a flash memory is disclosed. A self-aligned source implanted pocket located underneath and around the source line junction is formed after the field oxide between adjacent word lines is removed, and before or after the self-aligned source doping is carried out, so that the configuration of the implanted boron follows the source junction profile.

Abstract: A semiconductor device, wherein the lowering, in comparison with a background art, of the resistance of a source line is achieved and a manufacturing method for the same are obtained. A protruding portion (2m) that protrudes in the Y direction towards each drain region (3m) from a trunk portion (1) is formed in a source line (SLa) in each of five memory cells corresponding to “1” of the ROM code from among eight memory cells belonging to the m-th row. In the same manner, a protruding portion (2n) that protrudes in the Y direction towards each drain region (3n) from the trunk portion (1) is formed in the source line (SLa) in each of four memory cells corresponding to “1” of the ROM code from among eight memory cells belonging to the n-th row.

Abstract: When a circuit that is likely to cause noise is enabled, a control circuit turns on a switch so that an inverter will be formed by one P-channel MOSFET and two parallel-connected N-channel MOSFETs. This helps enhance the current capacity of the inverter on its N-channel MOSFET side, and thereby lower the threshold voltage of the inverter.

Abstract: Disclosed are semiconductor devices and methods for fabricating the same. According to one embodiment, the method includes sequentially forming a gate insulation layer and a conductive layer on a semiconductor substrate. A buried impurity region is then formed in the semiconductor substrate. Thus, the gate insulation layer is formed before forming the buried impurity region, thereby substantially reducing impurity diffusion that can be caused by a thermal process for forming the gate insulation layer. In addition, the gate insulation layer is not exposed, thus protecting the gate insulation layer from being recessed.

Abstract: An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

Abstract: Examples including non-volatile semiconductor memory devices in which digitized image data and voice data can be more efficiently written and read, and methods for manufacturing the same, are described. In one example, a non-volatile semiconductor memory device 300 may include a first memory element 100 and a second memory element 200 formed in a wafer 11 and mutually isolated by an element isolation region 38, a first impurity diffusion layer 16 and a second impurity diffusion layer 14. The first and second memory elements 100 and 200 include gate dielectric layers 20 and 120, floating gates 22 and 122, selective oxide dielectric layers 24 and 124 and third impurity diffusion layers 15 and 25, respectively, and also include a common intermediate dielectric layer 26 and a common control gate 28, and connected to the first and second impurity diffusion layers 16 and 14 that are commonly shared.

Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

Abstract: MOS transistor cells 1 and MOS transistor cells 2 having different gate threshold voltages are formed on a chip 8. The MOS transistor cells 1, 2 having the different gate threshold voltages are connected in parallel.

Abstract: Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. Such memory cells can be programmed, read and erased by applying various potential levels to their control gates, their drain regions, the first semiconductor region, and the second semiconductor region.

Abstract: A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, and a selection gate transistor one of the source/drain diffusion layer regions of which is connected to a bit line or a source line and the other of the the source/drain diffusion layer regions of which is connected to the memory cell unit. The shape of the source diffusion layer region of the selection gate transistor is asymmetrical to the shape of the drain diffusion layer region thereof below the selection gate transistor.

Abstract: A Mask ROM and a method for fabricating the same are described. The Mask ROM comprises a substrate, a plurality of gates on the substrate, a gate oxide layer between the gates and the substrate, a plurality of buried bit lines in the substrate between the gates, an insulator on the buried bit lines and between the gates, a plurality of word lines each disposed over a row of gates perpendicular to the buried bit lines, and a coding layer between the word lines and the gates.

Abstract: A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.

Abstract: A method of fabricating a memory device having a buried source/drain region is provided, in which a dielectric layer and a word-line is sequentially formed on the substrate, then a buried source/drain region is formed in the substrate. After that, a barrier layer is formed on the exposed surface of the word-line, then a metal layer is formed over the substrate. The metal layer is patterned to leave a portion covering the buried source/drain region beside the word-line and crossing over the word-line.

Abstract: A gate electrode conductive film is formed on the surface of a semiconductor substrate. First and second gate mask patterns made of a first insulating material are formed on the gate electrode conductive film on first and second sections. Sidewall spacers are formed on the sidewalls of the first and second gate mask patterns, the sidewall spacer being made of a second insulating material having an etching resistance different from the first insulating material. The second section is covered with a mask pattern and the sidewall spacer on the sidewall of the first gate mask pattern is removed. The gate electrode conductive film is etched to leave first and second gate electrodes on the first and second sections.

Abstract: In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.

Abstract: A nonvolatile semiconductor memory device includes memory cells including a first MOS transistor, and a boosting circuit including a capacitor element. The first MOS transistor includes a charge accumulation layer and a control gate formed on the charge accumulation layer with an inter-gate insulating film interposed therebetween. The capacitor element includes a first and a second semiconductor layers, a capacitor insulating film, and a third semiconductor layer. The first and second semiconductor layers are formed on a semiconductor substrate and separated from each other. The capacitor insulating film is formed on the top and side of each of the first and second semiconductor layers and on the semiconductor substrate between the first and second semiconductor layers and is made of the same material as that of the inter-gate insulating film. The third semiconductor layer is formed on the capacitor insulating film and is isolated electrically from the second semiconductor layer.

Abstract: A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.