Abstract: Structures and methods are presented for forming a field shield for a trench capacitor for a memory cell with a contact through insulator along a sidewall of the trench to a desired region of the semiconducting substrate. The desired region is typically held at a substantially fixed potential; in any case it does not include a node diffusion.

Abstract: A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151, . . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160).

Abstract: An integrated circuit device (10) is provided that comprises an P-FET (12) and an N-FET (14) formed on a semiconductor substrate (32). The P-FET (12) is formed in an n- tank (46). The source (18) and back-gate contact (22) of the P-FET (12) are connected to the V.sub.DD supply voltage. A current sink region (50) is formed in contact with the bulk semiconductor substrate (32). Periodic back-gate contacts (30) and (52) are made to the current sink region (50). The source (26) of N-FET (14) is also connected to the back-gate contacts (30) and (52). The current sink region (50) provides a low resistance path for charge within the substrate (32) to paths to the supply voltage V.sub.SS. This low resistance path prevents voltage from building up in the substrate (32) and thereby prevents latchup from occurring.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: A circuit die 100 with improved substrate noise isolation may be achieved by providing a first circuit element 102 and a second circuit element 103 on a substrate 101. The first circuit element 102 generally injects noise into the substrate 101 while the second circuit element 103 is adversely affected by noise being carried in the substrate 101. To reduce the noise interference, a noise isolation ring 104-017 may be placed around the first circuit element 102 and/or the second circuit element 103 wherein the noise isolation ring is of a conducted material. A first lead 202 is electrically connected to a first circuit element 102, a second lead 205 is electrically connected to the second circuit element 103, and a third lead 201 is electrically connected to the noise isolation ring 105, wherein the third lead 201 is electrically isolated from both the first and second leads 202 and 205.

Abstract: An insulated gate semiconductor device such as a MOSFET realizes high-frequency high-output operations. A first main electrode (1a) set at grounding potential is Formed on the bottom surface of a substrate. A second main electrode region (4) set at power source potential is formed on the top surface of the substrate. This structure involves very low grounding inductance. A buried insulation film (9) is formed under the second main electrode region, to reduce capacitance and improve power gains at high frequencies. Unlike an ordinary SOI semiconductor device, the buried insulation film of this MOSFET is not entirely formed through the substrate. A conductive region (10) is formed from the top surface to the bottom surface of the substrate at a location where the insulation film is not present, to improve heat dissipation and provide high output power. The buried insulation film (9) is formed by SIMOX, buried epitaxy, or silicon direct bonding (SDB) method.

Abstract: A semiconductor structure of merged isolation and node trench construction is presented, along with a method of fabrication, wherein an isolation implant layer is formed at the intersection of the storage node, isolation trench and field isolation region. The isolation implant layer has higher concentration of implant species than the adjacent field isolation region and is positioned to prevent a parasitic leakage mechanism between the source/drain diffusion of the storage node and an adjacent bit line contact diffusion. Implantation occurs during memory structure fabrication through the deep trench sidewall near the upper surface of the substrate.

Abstract: A semiconductor device is an SOI type field effect transistor in which an active region is isolated and insulated by a transistor for isolation. A contact hole for isolation is formed in a gate dielectric thin film for isolation between a gate electrode of the transistor for isolation and a channel region below the gate electrode. In the semiconductor device thus structured, surplus carriers produced in a channel region below a transfer gate electrode are drawn through channel region and isolation contact hole into isolation gate electrode, thereby preventing such a disadvantageous phenomenon as a kink effect or the like due to a floating-substrate effect.

Abstract: A field effect transistor signal switching device includes a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and first and second control electrodes disposed on the substrate for controlling the selective transmission of an input signal applied to the input electrode to the first and second output electrodes, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads, and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads.

Abstract: A vertical field effect transistor of the structure having a gate pad and a gate finger, includes a semiconductor substrate of a first conduction type, and a first diffusion region of a second conduction type opposite to the first conduction type, formed in a principal surface of the substrate under the gate pad and the gate finger. A second diffusion region of the second conduction type is formed in the principal surface of the substrate and electrically connected to a source electrode so as to form a protection diode between the substrate and the second diffusion region. The second diffusion region is separated from the first diffusion region.

Abstract: A semiconductor memory device comprising a substrate, a longitudinal source diffusion layer for a plurality of memory transistor source regions continuously formed on the substrate, and a longitudinal drain diffusion layer for a plurality of memory transistor drain regions continuously formed on the substrate in parallel to the source diffusion layer. A word line is formed crossing over the diffusion layers. And an electrically insulating film is interposed between the word line and the diffusion layers. The insulating film is thicker than a gate oxide film formed between the diffusion layers.

Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.

Abstract: First and second N-channel MOS transistors, each serving as a transfer gate, have their current paths connected, at their first ends, to bit lines, respectively, and their gates connected to a word line. Third and fourth N-channel MOS transistors, forming a flip-flop circuit, have their current paths connected, at their first ends, to the second ends of the current paths of the first and second transistors, respectively, and at their second ends, to a first power supply. The first ends of the current paths of the third and fourth transistors are connected to first ends of first and second thin-film transistors, respectively. The second ends of the current paths of the first and second thin-film transistors are connected to a second power supply. Each of the first and second thin-film transistors has first and second gates on both sides of its channel region.

Abstract: A trench structure (10) using germanium silicate. The trench structure (10) has a substrate material (12) and a hard mask material (14) that overlies the substrate material (12). An opening is formed in the hard mask material and the opening is used to form a trench (16) in the substrate material (12). The trench (16) has a sidewall portion and a bottom portion. A barrier (18 and 20) is formed overlying the bottom portion of the trench (16) and adjacent to the sidewall portion of the trench (16). A planar germanium silicate region (22) is formed overlying the barrier (18 and 20).

Abstract: A semiconductor integrated circuit arrangement prevents the occurrence of latch up. The circuit includes a first semiconductor island of a first conductivity type and a second semiconductor island of the first conductivity type located within a base semiconductor region of a second conductivity type. A resistive diffusion region of the second conductivity type is located within the first semiconductor island region. The second semiconductor region is connected to ground. A high potential electrode connected to the resistive diffusion region is also connected to the first semiconductor island region. In this manner, an emitter and a base of a parasitic transistor of the integrated circuit are connected together to prevent the parasitic transistor from operating in a conductive state, thereby preventing latch up.

Abstract: A radiation hardened MOSFET is fabricated by forming a dielectric layer of boro-phosphosilicate glass (BPSG) over the field oxide layer of the MOSFET. The BPSG covers only a small part of the gate electrode of the MOSFET. The gate electrode of the MOSFET is formed from two layers of polycrystalline silicon so as to prevent contamination of the gate oxide by the BPSG dopants.

Abstract: A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.

Abstract: A semiconductor device comprises an MOSFET (13) comprising a switching gate electrode (5) and a field shield MOS structure (11) formed on an element isolating region of a semiconductor substrate (1) and performs the element isolation by applying a bias voltage to the field shield (9). The field shield (9) is provided on the element isolating region of the semiconductor substrate (1) through an insulating film (8). A sidewall spacer (12) having its width set such that the field shield (9) may be an offset gate is formed on the side portion of the field shield (9). Then, source and drain layers (6) are formed on the main surface of the semiconductor substrate (1) so as not to overlap with the field shield (9). According to the semiconductor device, since the field shield (9) is the offset gate, it is possible to set high the threshold value on a parasitic MOS transistor and miniaturize the elements.