Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during the intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to educe or eliminate antenna effect problems without significant loss of a die area.

Abstract: A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and a plurality of second vias. The conductive layers are parallel layers each at a different height level between the bonding pad and a substrate. The first vias connect the bonding pad electrically with a neighboring conductive layer as well as each neighboring conductive layer. The first conductive line connects electrically with the conductive layer nearest the substrate and the drain terminal of an ESD protection circuit. The second conductive lines are parallel lines each at a different height level between the first conductive line and the bonding pad. Each second conductive line connects electrically with the conductive layer at a corresponding height level.

Abstract: A stacked spacer structure and process adapted for a stacked layer on a semiconductor substrate is described. The stacked spacer structure is formed on the sidewalls of the stacked layer which comprising a conductive layer and a cap layer thereon. A dielectric layer made of a material with low dielectric constant lower than that of silicon nitride is formed on the semiconductor substrate. A first silicon nitride layer is then formed over the substrate. The first silicon nitride layer and dielectric layer are etched sequentially to form an inner spacer on the sidewalls of the stacked layer. A second silicon nitride layer is formed over the substrate, and etched to form an outer spacer on the sidewalls of the inner spacer. By forming the stacked spacer structure of the present invention embedded low dielectric material, the coupling capacitance produced therein will be greatly reduced.

Abstract: An method and apparatus for high voltage control of isolation region transistors (320) in an integrated circuit. Isolation region transistors (320) are formed between active devices by selective implantation of channel stop implants (140). Isolation region transistors (320) are those areas with a conductor (130) over an isolation region (120) with no channel stop implant (140). This provides an isolation region transistor (320) with a lower threshold voltage than the areas with channel stop implant (140). The voltage threshold of the isolation region transistors 320 are adjustable to a range of voltages by varying the length of channel stop implant (140). The apparatus may be fabricated using conventional fabrication processes.

Abstract: The present invention discloses semiconductor device which comprises a metal gate electrode surrounded by polysilicon layers and a gate insulating film whose edges are thicker than the center portion formed according to a reoxidation process using a thermal process before the formation of an ion implantation region in a process for forming the metal gate electrode using a replacement process and method for manufacturing the same.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a semiconductor substrate having a gate formed there over. The semiconductor device further includes an isolation region having at least one source/drain region formed there over.

Abstract: A semiconductor device having a MOS transistor capable of effectively reducing leakage current and a method of manufacturing the same are provided. A silicon nitride film (11) is formed at the interface between a silicon substrate (1) and an oxide film (2) in the area except for the region for forming a polysilicon gate electrode (3) (i.e., an out-of-gate-electrode region). A silicon nitride film (13) is formed at the interface between the oxide film (2) and the side surface of the polysilicon gate electrode (3). Since the silicon nitride films (11, 13) can suppress the progress of oxidation, the oxidation of the silicon substrate (1) and the polysilicon gate electrode (3) can be suppressed effectively during a smile oxidation processing for obtaining the final shape of the oxide film (2).

Abstract: The breakdown voltage of a semiconductor device, such as a transistor fabricated in a device region in and abutting the surface of a semiconductor body with a field oxide surrounding the device region, is improved by etching the field oxide abutting the device region to reduce the thickness thereof to about 0.6-1.4 &mgr;m and then forming a field plate in the recessed field oxide which is capacitively coupled to the underlying semiconductor body. The field plate can be floating, connected to a voltage potential, or connected to the semiconductor device.

Abstract: A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or “offset” towards a shallower part.

Abstract: A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.

Abstract: A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. Positive ions such as H+ and Na+ penetrating into the field oxide layer cause a p-substrate under the field oxide layer to become inverted or act like an n-type substrate, creating leakage current between source and drain regions of transistors which the field oxide layer separates. When high transistor threshold voltages such as 12 volts or more are desired, the nitride layer provides a significant reduction in current leakage.

Abstract: A semiconductor device is fabricated by injecting fluorine into a region of a semiconductor substrate other than a region of the semiconductor substrate where a thinnest gate insulating film is to be formed, among a plurality of regions where gate insulating films are to be formed. Then, the semiconductor substrate with fluorine injected therein is oxidized to form an oxide film in the plurality of regions. A surface of the oxide film is nitrided to turn a surface layer thereof into an oxynitride film or form a nitride film on the surface of the oxide film. The semiconductor device has a plurality of gate insulating films of different thicknesses which contain nitrogen in their surface layers.

Abstract: A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n+-type semiconductor layer is formed in the prospective source and drain regions of the first semiconductor layer via the gate electrode, and a third n−-type semiconductor layer is formed on the second semiconductor layer. Each of source and drain regions is formed from the second and third semiconductor layers. The upper edge of the source/drain regions is formed above the boundary between the first semiconductor layer and the gate insulating film. In an ON state, part of a depletion layer in the drain region is formed in the third semiconductor layer, and part of a depletion layer in the source region is formed in the second semiconductor layer.

Abstract: Conventionally, an insulating film for element isolation has had a uniformly large thickness either in a memory cell area and in a peripheral circuit area so that the total film thickness of the memory cell area having a floating gate electrode, a control gate electrode, and an erase gate electrode is extremely increased, resulting in a large height difference between the memory cell area and the peripheral circuit area. The insulating film for element isolation in the peripheral circuit area should be thick, while the insulating films for element isolation in the memory cell area need not be as thick as the insulating film for element isolation in the peripheral circuit area in terms of operation.

Abstract: In important applications of circuits comprising transistors of the lateral DMOST type, such as (half) bridges, the voltage on the output may become higher or lower than the supply voltage or earth in the case of an inductive load. The injection of charge carriers into the substrate can be prevented by screening the drain (18) of the Low-Side transistor from the substrate by means of a p-type buried layer (13) and an n-type buried layer (14) below said p-type buried layer. In order to avoid parasitic npn-action between the n-type buried layer (14) and the n-type drain (18), not only the back-gate regions (16a, 16c) at the edge of the transistor, but also the back-gate regions (16b) in the center of the transistor, are connected to the p-type buried layer, for example by means of a p-type well. As a result, throughout the relatively high-ohmic buried layer, the potential is well defined, so that said npn-action is prevented.

Abstract: This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.

Abstract: A high-voltage semiconductor device includes: a drain region; a metal electrode electrically connected to the drain region; and electrically floating plate electrodes formed on a field insulating film over a semiconductor region. Parts of the metal electrodes are extended onto the interlevel dielectric film and located over the respective plate electrodes. Each part of the metal electrode is capacitively coupled to associated one of the plate electrodes.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A MOS transistor for high-speed operation includes a gate insulator formed over a semiconductor substrate and a gate formed over the gate insulator. An insulating layer is formed on both sides of the gate insulator at the edge of the gate and thicker than the gate insulator. The device is also formed with LDD regions which form an LDD structure in the semiconductor substrate at least partially under the gate. The LDD structure defines a channel region under the gate insulator between the LDD regions. In one embodiment, the insulating layer formed on both sides of the gate extends toward the channel region but not beyond the LDD regions. In another embodiment, the insulating layer does extend beyond the LDD region but for a distance of less than 10 nm.

Abstract: The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region.

Abstract: A method for fabricating a CMOS image sensor resolves the abnormally elevated output at the first pixel without degrading the integration of the device. The method of the invention lengthens the field oxide layer within the scribe-line region to ensure the substrate and the conducting layer thereon are properly insulated. That prevents the leakage of the carriers generated by the Electro-optical effect to resolve the problem of an abnormally elevated output at the first pixel. In addition, a mask protects the dielectric layer on the scribe-line region from being etched, so the steep difference on the step height is improved to resolve the peeling of the photoresist. The field oxide layer under the dielectric layer covered by the dielectric layer then provides a better insulation.

Abstract: A process for making a MOS transistor. The transistor includes a source, a channel and drain formed on a portion of silicon film in a silicon-on-insulator type structure. A field insulation layer surrounds the film. A grid structure with insulated flanks is formed above the channel. Source and drain contacts are formed on the portion of the silicon film between the field insulation layer and the grid structure. The source and drain contacts are self-aligned on the grid structure and the field insulation layer is placed directly adjacent to the grid structure.

Abstract: In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.

Abstract: A photoresist pattern is formed on a field oxide film and an element forming region across the field oxide film and the element forming region such that a portion of a surface of the field oxide film and a portion of a surface of a silicon epitaxial layer are continuously exposed. The photoresist pattern is used as a mask to inject boron ions into the silicon epitaxial layer and heat treatment is performed thereon to form an external base containing the relatively significant crystal defect present in the silicon epitaxial layer in the vicinity of the field oxide film. Thus, a semiconductor device can be obtained including a bipolar transistor which provides improved breakdown voltage between the collector and the base and contemplates reduction of current leakage.

Abstract: Silicon conductive vias and pedestals are disclosed for use in microwave integrated circuits. The pedestals are isolated from a ground plane on the bottom surface by glass, while the vias are used to make electrical contact to ground. Electrical circuit elements in the top surface of the integrated circuit are selectively grounded or isolated by the choice of connection to a via or pedestal, respectively.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region.

Abstract: A semiconductor manufacturing process is provided in which an oxidation retarding species is introduced into regions of the substrate distal from the isolation structures. A subsequent thermal oxidation process results in the formation of a gate dielectric film in which the film thickness proximal to the isolation structures is greater than the film thickness distal from the isolation structures. Broadly speaking, an isolation structure is formed in an isolation region of a semiconductor substrate. A mask is then formed on an upper surface of the semiconductor substrate. The mask covers the isolation structure and portions of the semiconductor substrate proximal to the isolation structure. A nitrogen bearing impurity distribution is then introduced into portions of the semiconductor substrate exposed by the mask. The nitrogen bearing impurity distribution therefore substantially resides within portions of the semiconductor substrate distal from the isolation structures.

Abstract: In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is formed over a region of the semiconductor substrate. The gate oxide layer has a relatively thinner oxide region over the nitride layer and a relatively thicker oxide region over the substrate adjacent the nitride layer. A transistor gate is formed extending over the relatively thinner oxide region and over the relatively thicker oxide region. The transistor thus formed is therefore asymmetric. A first transistor active region is formed in the vicinity of the relatively thicker oxide region and a second transistor active region is formed in the vicinity of the relatively thinner oxide region. The nitride layer can be formed by rapid thermal nitridization of the semiconductor substrate. The relatively thinner oxide region can be one-half as thick as the relatively thinner oxide region.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, in which a gate insulating film is formed thicker at portions opposite to edge portions of a gate electrode for preventing the hot carrier possible to occur due to a strong electric field of the gate electrode, that can improve a device reliability, the device including a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, the gate insulating film having both end portions formed thicker than a center portion, a gate electrode formed on the gate insulating film, the gate electrode having a center portion formed thicker than portions thereof on both sides of the gate insulating film, and impurity regions formed in surfaces of the semiconductor substrate on both sides of the gate electrode, and the method including the steps of (1) forming a gate insulating film on a semiconductor substrate, and forming a gate electrode having a thicker center portion on the gate insulating film, (2) expanding thicknesses o

Abstract: A method and structure for forming a modified field oxide region having increased field oxide threshold voltages (V.sub.th) and/or reduced leakage currents between adjacent device areas is achieved. The method involves forming a field oxide using the conventional local oxidation of silicon (LOCOS) using a patterned silicon nitride layer as a barrier to oxidation. After forming the LOCOS field oxide by thermal oxidation and removing the silicon nitride, a conformal insulating layer composed of silicon oxide is deposited and anisotropically etched back to form sidewall insulating portions over the bird's beak on the edge of the LOCOS field oxide, thereby forming a new modified field oxide. P-channel implants are formed in the device areas. Then a second implant is used to implant through the modified field oxide to provide channel-stop regions with modified profiles that increase the field oxide V.sub.th and/or reduce leakage current between device areas.

Abstract: A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from the surface of the semiconductor substrate. The element isolation oxide film which is an element isolation insulating film for defining an element forming region on the semiconductor substrate has a projection portion above the surface of the semiconductor substrate. The projection portion has the width wider than that of the trench. The projection portion and a contact portion made in contact with the semiconductor substrate within the trench are made of thermal oxide films, and a portion other than the projection portion and the contact portion is made of a CVD dioxide film.

Abstract: The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.

Abstract: A nonvolatile memory device and a manufacturing method thereof are provided. The nonvolatile memory device includes memory cells which are formed in a cell array region, peripheral circuit devices which are formed in a peripheral circuit region at the periphery of the cell array region, a field oxide film which is formed between the cell array region and the peripheral circuit region, and a dummy conductive pattern which is formed along and on the field oxide film. Accordingly, damage to the substrate formed between the peripheral circuit region and the cell array region can be reduced, thus a characteristic of insulation between devices can be enhanced.

Abstract: A field effect transistor comprising a semiconductor substrate having a transistor trench extending downward from an upper surface of the semiconductor substrate. The trench extends to a trench depth below an upper surface of the semiconductor substrate. The transistor further includes a gate dielectric layer that is formed on a floor of the transistor trench over a channel region of the semiconductor substrate. A conductive gate structure is formed above and in contact with the gate dielectric layer. A source/drain impurity distribution is formed within a source/drain region of the semiconductor substrate. The source/drain region is laterally disposed on either side of the channel region of the semiconductor substrate. In a preferred embodiment, the trench depth is between 1,000-5,000 angstroms and a thickness of the conductive gate structure is less than 5,000 angstroms such that an upper surface of the conductive gate structure is level with or below an upper surface of the semiconductor substrate.

Abstract: To provide a simulation method capable of efficiently evaluating reliability of gate oxide films formed on the elements within short periods of time to evaluate characteristics of a semiconductor device made up of elements of any size and any number.In a semiconductor device having transistors formed thereon, a pattern 1 for evaluating characteristics of a semiconductor device characterized in that gate area portions 9, gate bird's-beak portions 10 and LOCOS bird's-beak portions 11, are factors affecting the insulation breakdown of the gate oxide film, are rendered to be variable, so that the shapes of these portions can be handled as independent parameters.

Abstract: The present invention provides an integrated circuit chip having one or more circuit elements that perform a desired circuit function with the circuit elements being encompassed by a molding compound that forms a package for the chip. The molding compound has a capacitance associated with it. The integrated circuit chip includes a second integrated circuit element within the molding compound in which the second integrated circuit element monitors the molding compound to detect a change in capacitance in the molding compound resulting from a removal of a portion or all of the molding compound. In response to a detection of a change in capacitance, the second integrated circuit element alters the desired circuit function provided by the other integrated circuit elements.

Abstract: There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode.

Abstract: A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a silicon substrate, and a contact hole is formed in an inter-level insulating layer of silicon oxide exposing a part of the upper silicon nitride layer and a part of the titanium silicide layer into the contact hole; while the inter-level insulating layer is being selectively etched so as to form the contact hole, the upper silicon nitride layer serves as an etching stopper, and the contact hole never reaches the silicon substrate beneath the buried isolating structure.

Abstract: An n well and a p well are formed in a silicon substrate. The n well has n type impurity concentration peaks and a p type impurity concentration peak. The p well has p type concentration peaks. The impurity concentration peaks serving as channel stopper regions for isolating elements exist only in proximity to the lower surface of an isolation oxide film but not in element regions.

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between the element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract: A semiconductor device manufactured by isolating an element by forming an insulating film on the surface of a semiconductor substrate at an element isolation region, selectively forming a resist film at a second region on the surface of the semiconductor substrate by photolithography, high speed operation having priority over high integration in the second region, and selectively implanting impurity ions as a channel stopper in a first region by using the resist film as a mask, high integration having priority over high speed operation in the first region.

Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.

Abstract: The present invention discloses a structure of a transistor in a semiconductor device and a method of manufacturing the same.The present invention manufactures a high voltage transistor by etching a silicon substrate to a depth deeper than that of the field oxide film by a self-aligned wet etching process using the field oxide film as a mask and, thereafter, by forming the first gate electrode which electrically switches ON and OFF between the source region and the drain region by using a gate electrode mask and simultaneously forming a second gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.Accordingly, the present invention can improve the degree of integration of the device by forming a gate electrode to prevent a junction breakdown below the bird's beak of the field oxide film.

Abstract: The semiconductor device has a large capacity of power driving, and can operate at a high speed. A first semiconductor region of a first conductivity type is formed on a metal substrate through a first insulating film. In the first semiconductor region, first source and drain regions of a second conductivity type are formed. Further, on the region which isolates the first source and drain regions, a first metallic gate electrode is formed through a second insulating film.

Abstract: A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bit line and a capacitor are formed on the semiconductor layer. The semiconductor layer has a substantially flat upper surface, and an interlayer insulating layer and a second interlayer insulating layer having substantially flat upper surfaces are formed on the semiconductor layer. A capacitor is formed on the second interlayer insulating layer, and the capacitor and the second interlayer insulating layer are covered with a third interlayer insulating layer. Thereby, a level difference between a memory cell array and a peripheral circuitry can be reduced in a semiconductor memory device.

Abstract: A high voltage PMOS or NMOS transistor 7 has improved on-resistance by truncating gate field oxide 43 so that drain region 42 may be implanted closer to channel region 49 than possible otherwise. By shortening the physical distance d2 between drain 42 and channel region 49, the drain to source on-resistance of the high voltage device is reduced and the performance of high voltage device 7 is thereby improved.