Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.

Abstract: A nano-oscillator magnetic wave propagation system has a group of aggregated spin-torque nano-oscillators (ASTNOs), which share a magnetic propagation material. Each of the group of ASTNOs is disposed about an emanating point in the magnetic propagation material. During a non-wave propagation state of the nano-oscillator magnetic wave propagation system, the magnetic propagation material receives a polarizing magnetic field. During a wave propagation state of the nano-oscillator magnetic wave propagation system, each of the group of ASTNOs initiates spin waves through the magnetic propagation material, such that a portion of the spin waves initiated from each of the group of ASTNOs combine to produce an aggregation of spin waves emanating from the emanating point. The aggregation of spin waves may provide a sharper wave front than wave fronts of the individual spin waves initiated from each of the group of ASTNOs.

Abstract: A spin orbit torque-based spintronics device that includes a ferromagnet layer having a first surface and a second surface opposed to each other, a metal layer and a spacer layer covering the first surface and the second surface of the ferromagnet layer, respectively, and an dielectric layer covering either the metal layer or the spacer layer. Also disclosed are two related spin orbit torque-based spintronics devices and methods of using these three spintronics devices.

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less table memory having a MTJ with only a single oxide layer. Other embodiments are described herein.

Abstract: A method provides a magnetic junction having a top and sides. A first magnetic layer, a nonmagnetic spacer layer and a second magnetic layer are deposited. The nonmagnetic spacer layer is between the first and second magnetic layers. A free layer is one of the magnetic layers. A reference layer is the other of the magnetic layers. The second magnetic layer includes an amorphous magnetic layer having nonmagnetic constituent(s) that are glass-forming. An anneal is performed in a gas having an affinity for the nonmagnetic constituent(s). The gas includes at least one of first and second gases. The first gas forms a gaseous compound with the nonmagnetic constituent(s) The second gas forms a solid compound with the nonmagnetic constituent(s). The second gas is usable if the anneal is performed after the magnetic junction has been defined. The solid compound is at least on the sides of the magnetic junction.

Abstract: Hybrid Hall Effect Devices implemented with Spin Transfer Torque write capability are configured as magnetoelectronic (ME) devices. These devices are useable as circuit building blocks in reconfigurable processing systems, including as logic circuits, non-volatile switches and memory cells.

Abstract: MRAM cell including a magnetic tunnel junction including a reference layer, a storage layer having a storage magnetization, a tunnel barrier layer between the reference and the storage layers; and an antiferromagnetic layer exchange-coupling the storage layer such as to pin the storage magnetization at a low temperature threshold and free it at a high temperature threshold. The storage layer includes a first ferromagnetic layer in contact with the tunnel barrier layer, a second ferromagnetic layer in contact with the antiferromagnetic layer, and a low saturation magnetization storage layer including a ferromagnetic material and a non-magnetic material. The MRAM cell can be written with improved reliability.

Abstract: A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a spin current injection capping layer between the free layer of a magnetic tunnel junction and the orthogonal polarizer layer. The spin current injection capping layer maximizes the spin torque through very efficient spin current injection from the polarizer. The spin current injection capping layer can be comprised of a layer of MgO and a layer of a ferromagnetic material.

Abstract: A magnetic tunnel junction cell includes a first electrode having an axis extending in a direction substantially perpendicular to an active surface of a substrate. The magnetic tunnel junction further includes a fixed layer, a U-shaped free layer, a tunnel layer sandwiched between the fixed layer and the U-shaped free layer and a second electrode embedded in the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer are disposed between the first electrode and the second electrode and constitute a magnetic tunnel junction. The tunnel layer may also be U-shaped.

Abstract: Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.

Abstract: Magneto-resistive devices with lower power consumption and higher stability are provided. The magneto-resistive devices may include a pinned layer, a free layer and an insulating layer between the pinned layer and the free layer. The pinned layer, the free layer and the insulating layer may constitute a magnetic tunnel junction. The free layer may include a first magnetic layer and a second magnetic layer that has a Curie temperature lower than a Curie temperature of the first magnetic layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: an Nth metal layer; a bottom electrode over the Nth metal layer; a seed layer over the bottom electrode; a magnetic tunneling junction (MTJ) over the seed layer; a top electrode over the MTJ; and an (N+1)th metal layer over the top electrode; wherein the seed layer has a thickness greater than about one-third of a thickness of the MTJ. Another semiconductor structure is also disclosed. The semiconductor structure includes: a bottom electrode; a seed layer over the bottom electrode; a magnetic tunneling junction (MTJ) over the seed layer; and a top electrode over the MTJ; wherein from a cross-sectional view, the seed layer and the MTJ together have a substantial trapezoidal or rectangular shape, and a slope turning point of a sidewall of the substantial trapezoidal or rectangular shape is at a sidewall of the seed layer. An associated manufacturing method is also disclosed.

Abstract: Thermal-spin-torque (TST) in a magnetic tunnel junction (MTJ) is demonstrated by generating large temperature gradients across ultrathin MgO tunnel barriers, with this TST being significant enough to considerably affect the magnitude of the switching field of the MTJ. The origin of the TST is attributed to an asymmetry of the tunneling conductance across the zero-bias voltage of the MTJ. Through magneto-Seebeck voltage measurements, it is estimated that the charge-current that would be generated due to the temperature gradient would give rise to spin-transfer-torque (STT) that is a thousand times too small to account for the observed changes in switching fields, indicating the presence of large TST.

Abstract: A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

Abstract: According to one embodiment, there is provided a magnetoresistive element, including a lower electrode having crystallinity on a substrate, a first conductive layer including an amorphous state on the lower electrode, a buffer layer on the first conductive layer, and an MTJ element on the buffer layer.

Abstract: According to one embodiment, a magnetic memory element includes a first magnetic layer, a second magnetic layer, a nonmagnetic layer disposed between the first magnetic layer and the second magnetic layer, an electrode disposed on a side surface of the first magnetic layer, and a first insulation layer disposed between the first magnetic layer and the electrode, and including a first region with a first film thickness and a second region with a second film thickness which is less than the first film thickness.

Abstract: A device and a method of forming a device are disclosed. The method includes providing a substrate defined with first and second functional regions and first and second non-functional regions. The first non-functional region corresponds to a proximate memory region which is proximate to and surrounds the first functional region and the second non-functional region corresponds to an external logic circuit region which surrounds at least the second functional region. A magnetic memory element is formed in the first functional region and a logic element is formed in the second functional region. A plurality of magnetism controllable dummy structures are formed in the proximate memory region and external logic circuit region. The magnetism controllable dummy structures provide uniform magnetic field to the magnetic memory element and prevents electrical-magnetic interaction between the magnetic memory and logic elements on the same substrate.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, an electrode provided on the substrate, a first insulating film surrounding a side surface of the electrode. The first insulating film contains oxygen. The magnetic memory further includes a second insulating film provided between the electrode and the first insulating film, and surrounding the side surface of the electrode. The second insulating film contains nitrogen. A magnetoresistance effect element is provided on the electrode.

Abstract: Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.

Abstract: An STTMRAM element includes a magnetic tunnel junction (MTJ) having a perpendicular magnetic orientation. The MTJ includes a barrier layer, a free layer formed on top of the barrier layer and having a magnetic orientation that is perpendicular and switchable relative to the magnetic orientation of the fixed layer. The magnetic orientation of the free layer switches when electrical current flows through the STTMRAM element. A switching-enhancing layer (SEL), separated from the free layer by a spacer layer, is formed on top of the free layer and has an in-plane magnetic orientation and generates magneto-static fields onto the free layer, causing the magnetic moments of the outer edges of the free layer to tilt with an in-plane component while minimally disturbing the magnetic moment at the center of the free layer to ease the switching of the free layer and to reduce the threshold voltage/current.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: A method for fabricating an STT-MRAM integrated circuit includes forming a fixed layer over a bottom electrode layer, forming a silicon oxide layer a hardmask layer over the fixed, and forming a trench within the silicon oxide and hardmask layers, thereby exposing an upper surface of the fixed layer and sidewalls of the silicon oxide and hardmask layer. The method further includes forming a conformal barrier layer along the sidewalls of the silicon oxide and hardmask layers and over the upper surface of the fixed layer, such that the conformal barrier layer comprises sidewall portions adjacent the sidewalls of the silicon oxide and hardmask layers and a central portion in between the sidewall portions and adjacent the upper surface of the fixed layer. The method further includes forming a free layer between the sidewall portions of the barrier layer and over the central portion of the barrier layer.

Abstract: A seed layer stack with a smooth top surface having a peak to peak roughness of about 0.5 nm over a range of 100 nm is formed by sputter depositing an X layer such as Mo on a Ni layer where the X layer has one or both of a larger bond energy and a greater atomic number than Ni. A (Ni/X)m laminate is formed and then an uppermost NiCr seed layer is deposited to enhance perpendicular magnetic anisotropy (PMA) in an overlying ferromagnetic layer. A <111> NiCr crystal structure promotes <111> texture in the ferromagnetic layer. X layers serve as a diffusion barrier to Ta migration from a bottom electrode and have good lattice matching with the adjoining Ni layer and uppermost NiCr layer. As a result of the smooth seed layer stack in a magnetic tunnel junction (MTJ), MTJ properties are improved and more reproducible.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: A gyrator for AC signals comprises a Hall effect material, means for coupling an alternating current (I1; I4) into the Hall effect material, means for permeating a Hall effect material with a magnetic field that is perpendicular to the plane or surface of the material, and means far converting a current (I3; I2), which was generated by the current I1 perpendicularly to the electric field generated by I1 in the Hall effect material, into an output voltage (U4; U1). A transformer is provided between at least one conductor loop (1a; 2a) made of a normal-conducting or semi-conducting material and at least one conductor loop (1; 2) made of the Hall effect material for coupling the current (I1; I4) into the Hall effect material and/or for converting the current (I3; I2) in the Hall effect material into the output voltage (U4; U1).

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.

Abstract: A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer. The upper ILD layer includes a plurality of ILD levels. A plurality of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. The plurality of MTJ stacks include a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer. The first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface. The plurality of MTJ stacks also include a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer.

Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on an upper surface of a wiring substrate, and a magnetic shield arranged above the upper surface of the wiring substrate to cover an upper side of the semiconductor element. The magnetic shield is formed from a soft magnetic material and includes inclined faces that are inclined straight with respect to the upper surface of the wiring substrate at a portion overlapped with the semiconductor element in a plan view.

Abstract: An apparatus according to one embodiment includes at least one write transducer, and a plurality of detector structures positioned in an array. Each of the detector structures includes a pair of conductive layers separated by an insulating material. None of the detector structures include an operable reader for reading data from a magnetic medium. A computer-implemented method according to one embodiment includes monitoring a resistance value of each of a plurality of detector structures positioned in an array, and detecting a change in a resistance value of at least one of the detector structures for identifying a defect on a magnetic medium. Each of the detector structures include a pair of conductive layers separated by an insulating material. None of the detector structures include an operable reader for reading data from a magnetic medium.

Abstract: Magnetoelectronic circuits include Hybrid Hall Effect devices implemented with Spin Transfer Torque write capability. The circuits include reconfigurable processing systems, logic circuits, non-volatile switches, memory cells, etc.

Abstract: Implementations disclosed herein allow a signal detected by a magnetoresistive (MR) sensor to be improved by providing for one or more alloyed layers that each includes a ferromagnetic material and a refractory material. The alloyed layers are provided adjacent to a shield element or between soft magnetic layers of the sensor stack.

Abstract: According to one embodiment, a magnetoresistive memory device includes a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, and a third magnetic layer provided on the first magnetic layer, which is opposite the nonmagnetic layer. The third magnetic layer includes a first magnetic material portion and a second magnetic material portion provided between the stacked layer structure and the first magnetic material portion. The saturation magnetization of the second magnetic material portion is smaller than that of the first magnetic material portion.

Abstract: Magnetic memory devices having an antiferromagnetic reference layer based on Co and Ir are provided. In one aspect, a magnetic memory device includes a reference magnetic layer having multiple Co-containing layers oriented in a stack, wherein adjacent Co-containing layers in the stack are separated by an Ir-containing layer such that the adjacent Co-containing layers in the stack are anti-parallel coupled by the Ir-containing layer therebetween; and a free magnetic layer separated from the reference magnetic layer by a barrier layer. A method of writing data to a magnetic random access memory device having at least one of the present magnetic memory cells is also provided.

Abstract: According to one embodiment, a magnetoresistive memory device, includes a metal buffer layer provided on a substrate, a crystalline metal nitride buffer layer provided on the metal buffer layer, and a magnetoresistive element provided on the metal nitride buffer layer. The metal nitride buffer layer and the metal buffer layer contain a same material.

Abstract: The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

Abstract: An object is to achieve miniaturization and an increase in performance of a magnetic sensor device, and the magnetic sensor according to the present invention has a magnetic film and a metal electrode to be electrically coupled to the magnetic film, the magnetic film and the metal electrode constituting a magnetic sensor portion. The metal electrode is formed with level difference portions, and the magnetic film is formed on the level difference portions and sidewalls that connect the level difference portions.

Abstract: An electronic device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance variable element interposed between the first electrode and the second electrode, and a conductor arranged at least one of a first side and a second side of the resistance variable element to apply an electric field to the resistance variable element while being spaced apart from the resistance variable element, the first side facing the second side.

Abstract: A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer.

Abstract: An apparatus is described having a select line and an interconnect with Spin Hall Effect (SHE) material. The interconnect is coupled to a write bit line. A transistor is coupled to the select line and the interconnect. The transistor is controllable by a word line. The apparatus also includes an MTJ device having a free magnetic layer coupled to the interconnect.

Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: Provided is an information storage element comprising a first layer, an insulation layer coupled to the first layer, and a second layer coupled to the insulation layer opposite the first layer. The first layer is capable of storing information according to a magnetization state of a magnetic material. The insulation layer includes a non-magnetic material. The second layer includes a fixed magnetization. In an embodiment, the first layer has a transverse length that is approximately 45 nm or less and a volume that is approximately 2,390 nm3 or less. In a further embodiment, the second layer includes MgO and is capable of allowing electrons passing through the second layer reach the first layer before the electrons enter a non-polarized state.

Abstract: A hard mask stack for etching a magnetic tunneling junction (MTJ) structure is described. The hard mask stack is formed on a stack of MTJ layers on a bottom electrode and comprises an electrode layer on the MTJ stack, a buffer metal layer on the electrode layer, a metal hard mask layer on the buffer metal layer, and a dielectric layer on the metal hard mask layer wherein a dielectric mask is defined in the dielectric layer by a photoresist mask, a metal hard mask is defined in the metal hard mask layer by the dielectric mask, a buffer metal mask is defined in the buffer metal layer by the metal hard mask, an electrode mask is defined in the electrode layer by the buffer metal mask, and the MTJ structure is defined by the electrode mask wherein the electrode mask remaining acts as a top electrode.

Abstract: A method of forming a magnetoresistive (MR) sensor with a composite tunnel barrier comprised primarily of magnesium oxynitride and having a MR ratio of at least 70%, resistance x area (RA) product <1 ohm-?m2, and fewer pinholes than a conventional MgO layer is disclosed. The method involves forming a Mg/MgON/Mg, Mg/MgON/MgN, MgN/MgON/MgN, or MgN/MgON/Mg intermediate tunnel barrier stack and then annealing to drive loosely bound oxygen into adjacent layers thereby forming MgO/MgON/Mg, MgO/MgON/MgON, MgON/MgON/MgON, and MgON/MgON/MgO composite tunnel barriers, respectively, wherein oxygen content in the middle MgON layer is greater than in upper and lower MgON layers. The MgON layer in the intermediate tunnel barrier may be formed by a sputtering process followed by a natural oxidation step and has a thickness greater than the Mg and MgN layers.

Abstract: A magnetoelectric device is provided. The magnetoelectric device includes a reference magnetic layer structure having a fixed magnetization orientation, and a synthetic antiferromagnetic layer structure including a free magnetic layer structure and a coupling magnetic layer structure antiferromagnetically coupled to each other, each of the free magnetic layer structure and the coupling magnetic layer structure having a magnetization orientation that is variable, wherein the reference magnetic layer structure and the synthetic antiferromagnetic layer structure are arranged one over the other. According to further embodiments of the present invention, a method for forming a magnetoelectric device and a writing method for a magnetoelectric device are also provided.

Abstract: The disclosed technology relates to a magnetic memory device. In one aspect, the device includes a first electrode comprising a conductive pillar formed over the substrate and elongated in a vertical direction crossing a lateral surface of the substrate. The device additionally includes a second electrode extending in a lateral direction crossing the first direction, where the second electrode intersects the first electrode. The device additionally includes a magnetic tunnel junction (MTJ) formed at an intersection between the first electrode and the second electrode, where the MTJ continuously surrounds the first electrode. The MTJ includes a reference layer continuously surrounding the pillar of the first electrode, a free layer continuously surrounding the free layer, and a dielectric tunnel barrier interposed between the reference layer and the free layer.

Abstract: Provided is a highly sensitive vertical Hall element without increasing a chip area. In the vertical Hall element, trenches each filled with an insulating film are formed between a first current supply end and voltage output ends, respectively, which enables the restriction of current flow into the voltage output ends to increase the ratio of a current component perpendicular to a substrate surface, resulting in enhanced sensitivity.

Abstract: A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.