Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate controlled transistors and methods of manufacture. The structure includes: an emitter region; a collector region; base regions on opposing sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, the body region being located between the base regions on opposing sides of the emitter region and the collector region, and the leg regions isolating the base regions from both the emitter region and the collector region.

Abstract: A mixer comprises a substrate of a first conductivity type; at least one minority carrier injector for injecting minority carriers in the substrate in reply to a first electrical signal applied to the at least one minority carrier injector; at least two substrate taps located in the substrate for providing a majority carrier current density with associated electric field in the substrate in reply to a second electrical signal applied to the at least two substrate taps. The majority carrier current density's associated electric field determines the drift direction of the injected minority carriers. The mixer further comprises at least two minority carrier collectors located in the substrate, for collecting minority carriers from the substrate. Each minority carrier collector is located adjacent to one of the at least two substrate taps.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract: Various embodiments of the present technology may comprise a method and apparatus for an analog-to digital converter (ADC). Methods and apparatus for an ADC according to various aspects of the present invention may operate in conjunction with a reference voltage that varies according to the frequency of a timing signal. By varying the reference voltage according to the frequency of the timing signal, the ADC generates a digital output having a substantially fixed voltage regardless of the frequency of the timing signal.

Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.

Abstract: A governing circuit for a magneto-transistor is disclosed. The magneto-transistor comprising a first and second collector. At least one emitter and at least one base. The governing circuit is configured to measure a first calibration current at the first collector of the magneto-transistor and a second calibration current at the second collector of the magneto-transistor, while a calibration base-emitter voltage is applied to the magneto-transistor. The magneto-transistor is also configured to measure a first measurement current at the first collector of the magneto-transistor and a second measurement current at the second collector of the magneto-transistor, while a measurement base-emitter voltage is applied to the magneto-transistor, wherein the measurement base-emitter voltage is different form the calibration base-emitter voltage and determine an output signal indicative of an applied magnetic field using the measured first and second measurement current and first and second calibration currents.

Abstract: A differential magnetic field sensor system (10) is provided, in which offset cancelling for differential semiconductor structures in magnetic field sensors arranged close to each other is realized. The system (10) comprises a first, a second and a third magnetic field sensor (100, 200, 300), each of which is layouted substantially identically and comprises a, preferably silicon-on-insulator (SOI), surface layer portion (102) provided as a surface portion on a, preferably SOI, wafer and having a surface (104).

Abstract: A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.

Abstract: A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

Abstract: A silicon-based thermal energy transfer apparatus that aids dissipation of thermal energy from a heat-generating device, such as an edge-emitting laser diode, is provided. In one aspect, the apparatus comprises a base portion and a support portion. The base portion is made of silicon and includes a first primary surface. The first primary surface includes at least first and second V-notch grooves thereon. The support portion is made of silicon and includes at least first and second edges that are interlockingly received in the first and second V-notch grooves when the support portion is mounted on the base portion.

Abstract: A spin-wave waveguide includes a ferromagnetic thin film resembling a wire in shape. A part of the ferromagnetic thin film, large in film thickness, is formed at one end of the ferromagnetic thin film, and a part of the ferromagnetic thin film, small in film thickness, and a part of the ferromagnetic thin film, large in film thickness, are alternately formed on the same plane, for at least not less than one cycle. A part of the ferromagnetic thin film, large in film thickness, is formed at the other end of the ferromagnetic thin film, wherein an insulating film, and an electrode film are stacked in this order on the ferromagnetic thin film in the part of the ferromagnetic thin film, large in film thickness.

Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.

Abstract: A method and structure for a three-axis magnetic field sensing device. An IC layer having first bond pads and second bond pads can be formed overlying a substrate/SOI member with a first, second, and third magnetic sensing element coupled the IC layer. One or more conductive cables can be formed to couple the first and second bond pads of the IC layer. A portion of the substrate member and IC layer can be removed to separate the first and second magnetic sensing elements on a first substrate member from the third sensing element on a second substrate member, and the third sensing element can be coupled to the side-wall of the first substrate member.

Abstract: According to one embodiment, a semiconductor storage device is disclosed. The device includes first magnetic layer, second magnetic layer, first nonmagnetic layer between them. The first magnetic layer includes a structure in which first magnetic material film, second magnetic material film, and nonmagnetic material film between the first and second magnetic material films are stacked. The first magnetic material film is nearest to the first nonmagnetic layer in the first magnetic layer. The nonmagnetic material film includes at least one of Ta, Zr, Nb, Mo, Ru, Ti, V, Cr, W, Hf. The second magnetic material film includes stacked materials, including first magnetic material nearest to the first nonmagnetic layer among the stacked materials, and second magnetic material which is same magnetic material as the first magnetic material and has smaller thickness than the first magnetic material.

Abstract: Orthogonal spin-torque bit cells whose spin torques from a perpendicular polarizer and an in-plane magnetized reference layer are constructively or destructively combined. An orthogonal spin-torque bit cell includes a perpendicular magnetized polarizing layer configured to provide a first spin-torque; an in-plane magnetized free layer and a reference layer configured to provide a second spin-torque. The first spin-torque and the second spin-torque combine and the combined first spin-torque and second spin-torque influences the magnetic state of the in-plane magnetized free layer. The in-plane magnetized free layer and the reference layer form a magnetic tunnel junction. The first spin-torque and second spin-torque can combine constructively to lower a switching current, increase a switching speed, and/or torque decrease an operating energy of the orthogonal spin-torque bit cell.

Abstract: Provided are magnetic memory devices with a perpendicular magnetic tunnel junction. The device includes a magnetic tunnel junction including a free layer structure, a pinned layer structure, and a tunnel barrier therebetween. The pinned layer structure may include a first magnetic layer having an intrinsic perpendicular magnetization property, a second magnetic layer having an intrinsic in-plane magnetization property, and an exchange coupling layer interposed between the first and second magnetic layers. The exchange coupling layer may have a thickness maximizing an antiferromagnetic exchange coupling between the first and second magnetic layers, and the second magnetic layer may exhibit a perpendicular magnetization direction, due at least in part to the antiferromagnetic exchange coupling with the first magnetic layer.

Abstract: A magnetic device includes a substrate, a sensing block and a repair layer. The substrate has a registration layer and a barrier layer disposed on the registration layer. The sensing block is patterned to distribute on the barrier layer. The repair layer is disposed substantially on the barrier layer, wherein the barrier layer is configured to have a tunneling effect when a bias voltage exists between the sensing block and the registration layer.

Abstract: The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base.

Abstract: A method for forming MRAM (magnetoresistive random access memory) devices is provided. A bottom electrode assembly is formed. A magnetic junction assembly is formed, comprising, depositing a magnetic junction assembly layer over the bottom electrode assembly, forming a patterned mask over the magnetic junction assembly layer, etching the magnetic junction assembly layer to form the magnetic junction assembly with gaps, gap filling the magnetic junction assembly, and planarizing the magnetic junction assembly. A top electrode assembly is formed.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.

Abstract: Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end.

Abstract: A magnetic memory element includes: a first magnetization free layer configured to be composed of ferromagnetic material with perpendicular magnetic anisotropy; a reference layer configured to be provided near the first magnetization free layer; a non-magnetic layer configured to be provided adjacent to the reference layer; and a step formation layer configured to be provided under the first magnetization free layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region configured to be connected with the first magnetization fixed region and the second magnetization fixed region. The first magnetization free layer has at least one of a step, a groove and a protrusion inside.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall.

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract: A method of manufacturing an integrated circuit having a substrate comprising a plurality of components and a metallization stack over the components, the metallization stack comprising a first sensing element and a second sensing element adjacent to the first sensing element.

Abstract: The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention.

Abstract: Magnetoresistive elements, and memory devices including the same, include a pinned layer having a fixed magnetization direction, a free layer corresponding to the pinned layer, and a protruding element protruding from the free layer and having a changeable magnetization direction. The free layer has a changeable magnetization direction. The protruding element is shaped in the form of a tube. The protruding element includes a first protruding portion and a second protruding portion protruding from ends of the free layer facing in different directions.

Abstract: A magnetic device includes a first electrode portion, a free layer portion arranged on the first electrode portion, the free layer portion including a magnetic insulating material, a reference layer portion contacting the free layer portion, the reference layer portion including a magnetic metallic layer, and a second electrode portion arranged on the reference layer portion.

Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

Abstract: A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.

Abstract: A memory element includes a layered structure: a memory layer having a changeable magnetization direction, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, including a first ferromagnetic layer having a magnetization direction that is inclined from a direction perpendicular to a film face, a bonding layer laminated on the first ferromagnetic layer, and a second ferromagnetic layer laminated on the bonding layer and bonded to the first ferromagnetic layer via the bonding layer, having a magnetization direction that is inclined from the direction perpendicular to the film face, a magnetization-fixed layer having a fixed magnetization direction, an intermediate layer that is provided between the memory layer and the magnetization-fixed layer, and is contacted with the first ferromagnetic layer, and a cap layer that is contacted with the second ferromagnetic layer.

Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?atan(?)) degrees.

Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.

Abstract: A method and structure for a three-axis magnetic field sensing device is provided. The device includes a substrate, an IC layer, and preferably three magnetic field sensors coupled to the IC layer. A nickel-iron magnetic field concentrator is also provided.

Abstract: According to one embodiment, a magnetic memory element includes a stacked body including first and second stacked units stacked with each other. The first stacked unit includes first and second ferromagnetic layers and a first nonmagnetic layer provided therebetween. The second stacked unit includes third and fourth ferromagnetic layers and a second nonmagnetic layer provided therebetween. Magnetization of the second and third ferromagnetic layers are variable. Magnetizations of the first and fourth ferromagnetic layers are fixed in a direction perpendicular to the layer surfaces. A cross-sectional area of the third ferromagnetic layer is smaller than a cross-sectional area of the first stacked unit when cut along a plane perpendicular to the stacking direction.

Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract: According to one embodiment, a magnetoresistive element includes the following configuration. A first magnetic layer has an invariable magnetization. A second magnetic layer has a variable magnetization. A nonmagnetic layer is provided between the first and the second magnetic layers. The first magnetic layer has a structure in which first, second and third magnetic material films and a nonmagnetic material film are stacked. The first magnetic material film is provided in contact with the nonmagnetic layer, the nonmagnetic material film is provided in contact with the first magnetic material film, the second magnetic material film is provided in contact with the nonmagnetic material film, and the third magnetic material film is provided in contact with the second magnetic material film. The second magnetic material film has a Co concentration higher than that of the first magnetic material film.

Abstract: A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

Abstract: A memory element includes a layered structure and a negative thermal expansion material layer. The layered structure includes a memory layer, a magnetization-fixed layer, and an intermediate layer. The memory layer has magnetization perpendicular to a film face in which a magnetization direction is changed depending on information, and includes a magnetic layer having a positive magnetostriction constant. The magnetization direction is changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer. The magnetization-fixed layer has magnetization perpendicular to a film face that becomes a base of the information stored in the memory layer. The intermediate layer is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

Abstract: A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 ? to 400 ?. The MTJ cell structure can have a top conducting layer over the sacrifice layer.

Abstract: According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.

Abstract: In one aspect of the present invention, the semiconductor device is a bipolar magnetic junction transistor (MJT), and includes a first non-magnetic semiconductor layer, a second non-magnetic semiconductor layer, and a magnetic semiconductor layer. The first non-magnetic semiconductor layer has majority charge carriers of a first polarity. The second non-magnetic semiconductor layer is disposed adjacent to the first non-magnetic semiconductor layer such that a first junction is formed at a first interface region between the first non-magnetic semiconductor layer and the second non-magnetic semiconductor layer. The magnetic semiconductor layer has majority charge carriers of the first polarity, and is disposed adjacent to the second non-magnetic semiconductor layer such that a second junction is formed at a second interface region between the second non-magnetic semiconductor layer and the magnetic semiconductor layer.

Abstract: A magnetic memory element includes: a first magnetization free layer; a non-magnetic layer; a reference layer; a first magnetization fixed layer group; and a first blocking layer. The first magnetization free layer is composed of ferromagnetic material with perpendicular magnetic anisotropy and includes a first magnetization fixed region, a second magnetization fixed region and a magnetization free region. The non-magnetic layer is provided near the first magnetization free layer. The reference layer is composed of ferromagnetic material and provided on the non-magnetic layer. The first magnetization fixed layer group is provided near the first magnetization fixed region. The first blocking layer is provided being sandwiched between the first magnetization fixed layer group and the first magnetization fixed region or in the first magnetization fixed layer group.

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material.

Abstract: A magnetic tunnel junction (MTJ) storage element may comprise a pinned layer stack and a first functional layer. The pinned layer stack is formed of a plurality of layers comprising a bottom pinned layer, a coupling layer, and a top pinned layer. The first functional layer is disposed in the bottom pinned layer or the top pinned layer.

Abstract: A method for manipulating domain pinning and reversal in a ferromagnetic material comprises applying an external magnetic field to a uniaxial ferromagnetic material comprising a plurality of magnetic domains, where each domain has an easy axis oriented along a predetermined direction. The external magnetic field is applied transverse to the predetermined direction and at a predetermined temperature. The strength of the magnetic field is varied at the predetermined temperature, thereby isothermally regulating pinning of the domains. A magnetic storage device for controlling domain dynamics includes a magnetic hard disk comprising a uniaxial ferromagnetic material, a magnetic recording head including a first magnet, and a second magnet. The ferromagnetic material includes a plurality of magnetic domains each having an easy axis oriented along a predetermined direction.

Abstract: A magnetic storage device stable in write characteristic is provided. A first nonmagnetic film is provided over a recording layer. A first ferromagnetic film is provided over the first nonmagnetic film and has a first magnetization and a first film thickness. A second nonmagnetic film is provided over the first ferromagnetic film. A second ferromagnetic film is provided over the second nonmagnetic film, is coupled in antiparallel with the first ferromagnetic film, and has a second magnetization and a second film thickness. An antiferromagnetic film is provided over the second ferromagnetic film. The sum of the product of the first magnetization and the first film thickness and the product of the second magnetization and the second film thickness is smaller than the product of the magnetization of the recording layer and the film thickness of the recording layer.