Abstract: Disclosed is a method of producing an LnCuOX single-crystal thin film (wherein Ln is at least one selected from the group consisting of lanthanide elements and yttrium, and X is at least one selected from the group consisting of S, Se and Te), which comprises the steps of growing a base thin film on a single-crystal substrate, depositing an amorphous or polycrystalline LnCuOX thin film on the base thin film to form a laminated film, and then annealing the laminated film at a high temperature of 500° C. or more.

Abstract: A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the at least one second memory elements.

Abstract: A method for improving the luminescent efficiency of semiconductor nanocrystals by surface treatment with a reducing agent to produce an improvement in luminescent efficiency and quantum efficiency without creating changes in the luminescent characteristics of the nanocrystals such as luminescence wavelengths and the distribution thereof.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: Processes for effecting thermal transfer of electroactive organic material are disclosed wherein unwanted portions of a layer of electroactive organic material supported by a donor element are removed or transferred from the layer by thermal transfer, particularly laser-induced thermal transfer, leaving a desired pattern of the electroactive organic material on the donor element. The electroactive organic material may be an organic material exhibiting electroluminescence, charge transport, charge injection, electrical conductivity, semiconductivity and/or exciton blocking. The layer of electroactive organic material may comprise more than one layer of different types of electroactive organic material. The exposure pattern is a negative image of the desired pattern. The electroactive organic material of the desired pattern is not, therefore, exposed to the heat which can cause decomposition.

Abstract: A resistance variable memory element and a method for forming the same. The memory element has an amorphous carbon layer between first and second electrodes. A metal-containing layer is formed between the amorphous carbon layer and the second electrode.

Abstract: The invention comprises a composite material comprising a host material in which are incorporated semiconductor nanocrystals. The host material is light-transmissive and/or light-emissive and is electrical chargetransporting thus permitting electrical charge transport to the core of the nanocrystals. The semiconductor nanocrystals emit and/or absorb light in the near infrared spectral range. The nanocrystals cause the composite material to emit/absorb energy in the near infrared (NIR) spectral range, and/or to have a modified dielectric constant, compared to the host material. The invention further comprises electro-optical devices composed of this composite material and a method of producing them. Specifically described are light emitting diodes that emit light in the NIR and photodetectors that absorb light in the same region.

Abstract: The present invention provides a semiconductor radiation detector and radiation detection apparatus capable of improving energy resolution and the semiconductor radiation detection apparatus includes a semiconductor radiation detector and a signal processing circuit which processes a radiation detection signal output from the semiconductor radiation detector. The semiconductor radiation detector is provided with anode electrodes A and cathode electrodes C disposed so as to face each other with semiconductor radiation detection elements placed in-between. The semiconductor radiation detection element is made up of a single crystal of thallous bromide containing trivalent thallium (e.g., tribromobis thallium). The semiconductor radiation detector containing such a semiconductor radiation detection element reduces lattice defects in the single crystal and thereby increases charge collection efficiency.

Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100?x composition.

Abstract: Briefly, in accordance with an embodiment of the invention, a lateral phase change memory and a method to manufacture a phase change memory is provided. The method may include forming a conductor material over a substrate and patterning the conductor material to form two electrodes from the conductor material, wherein the two electrodes are separated by a sub-lithographic distance. The method may further include forming a phase change material between the two electrodes.

Abstract: Storage cells for a phase change memory device and phase change memory devices are provided that include a first phase change material pattern and a first high-resist phase change material pattern on the first phase change material pattern. The first high-resist phase change material pattern has a higher resistance than the first phase change material pattern. Methods of fabricating such storage cells and/or memory devices are also provided.

Abstract: An ultra-high density data storage device using phase-change diode memory cells, and having a plurality of emitters for directing beams of directed energy, a layer for forming multiple data storage cells and a layered diode structure for detecting a memory or data state of the storage cells, wherein the device comprises a phase-change data storage layer capable of changing states in response to the beams from the emitters, comprising a material containing copper, indium and selenium. A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes, wherein the method comprises depositing a first diode layer of material on a substrate, and depositing a second diode layer of phase-change material on the first diode layer, the phase-change material containing copper, indium and selenium.

Abstract: The present invention relates to a non-volatile memory comprising: a first electrode (11); a second electrode (12); and a phase-change recording medium (14) sandwiched between the first electrode (11) and the second electrode (12), in which resistance value is varied by applying an electrical pulse across the first electrode (11) and the second electrode (12), at least one of the first electrode (11) and the second electrode (12) contains as a main ingredient at least one member selected from the group consisting of ruthenium, rhodium and osmium, and the phase-change recording medium (14) is formed of a phase-change material that contains chalcogen(s). This non-volatile memory exhibits improved durability and reliability by preventing deterioration of property (i.e., mutual impurity diffusion between the electrode and the phase-change recording medium) caused by application of current.

Abstract: A packaging fabrication for an organic electroluminescence panel is disclosed. The panel comprises a printed circuit board, one or a plurality of OEL panels and a plurality of bumps, wherein the OEL is provided with poly solder interconnections in area array. The printed circuit board is provided with a plurality of solder pads arranged with bumps. One or a plurality of OEL is arranged on the printed circuit board and the poly solder interconnections and bumps are used to electrically connect the OEL with the printed circuit board. Further, the excellent heat dissipation property of the low re-flow temperature of the poly solder interconnections and the ceramic printed circuit board provides packaging fabrication for low temperature low stress OEL.

Abstract: A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Abstract: High quality epitaxial layers of piezoelectric monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the piezoelectric monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying piezoelectric monocrystalline material layer.

Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

Abstract: An ultra-high density data storage device using phase-change diode memory cells, and having a plurality of emitters for directing beams of directed energy, a layer for forming multiple data storage cells and a layered diode structure for detecting a memory or data state of the storage cells, wherein the device comprises a phase-change data storage layer capable of changing states in response to the beams from the emitters, and a second layer forming one layer in the layered diode structure, the second layer comprising a material containing copper, indium and selenium. A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes, comprises depositing a first diode layer of CuInSe material on a substrate and depositing a second diode layer of phase-change material on the first diode layer.

Abstract: A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and system and devices for performing the method, semiconductor devices so produced, and machine readable media containing the method. One method disclosed includes forming a first layer, forming a second layer on the first layer, forming a third layer on the second layer, wherein the third layer is essentially transparent to irradiation, and irradiating the second layer through the third layer to cause the second layer to diffuse into the first layer thereby creating an integral layer of materials from the first and second layers.

Abstract: A memory may have access devices formed using a chalcogenide material. The access device does not induce a snapback voltage sufficient to cause read disturbs in the associated memory element being accessed. In the case of phase change memory elements, the snapback voltage may be less than the threshold voltage of the phase change memory element.

Abstract: An apparatus and method are disclosed for encapsulating an OLED device formed on a flexible substrate. The OLED device is moisture protected by an encapsulation which sandwiches the OLED device between two transparent dielectric metal oxide layers. The oxide layers are formed in a chamber which includes a plurality of processing stations for forming successive atomic layers of oxides along passes of the flexible substrate within the chamber.

Abstract: The present invention relates to a technique that can be used to reduce the sensitivity of integrated circuits to a failure mechanism to which some integrated circuits (ICs) are susceptible, known as latchup. The present invention relates to a scheme for suppressing latchup sensitivity by a step to be performed after the IC has been manufactured, rather than being a step in the normal production process. The process involves exposing silicon, either in wafer or die form, to energetic ions, such as protons (hydrogen nuclei) or heavier nuclei (e.g. argon, copper, gold, etc.), having energy sufficient to penetrate the silicon from the back of the wafer or die to within a well-defined distance from the surface of the silicon on which the integrated circuit has been formed (the front surface).

Abstract: A microelectronic programmable structure suitable for storing information and a method of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: A method produces a thermoelectric layer structure on a substrate and the thermoelectric layer structure has at least one electrically anisotropically conductive V-VI layer, in particular a (Bi, Sb)2 (Te, Se)3 layer. The V-VI layer is formed by use of a seed layer or by a structure formed in the substrate, and disposed relative to the substrate such that an angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. The orientation can also be effected by an electric field. Components are formed of the thermoelectric layer structure in which the angle between the direction of the highest conductivity of the V-VI layer and the substrate is greater than 0°. As a result, the known anisotropy of the V-VI materials can advantageously be used for the construction of components.

Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a silver layer over a chalcogenide glass layer. Processing the silver layer via heat treating, light irradiation, or a combination of both to form a layer comprising silver interstitially formed in a chalcogenide glass layer; silver-selenide formed in a layer comprising silver interstitially formed in a chalcogenide glass layer; or a silver doped chalcogenide glass layer having silver-selenide formed therein.

Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line. By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced.

Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line. By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced.

Abstract: A thin-film flexible solar cell built on a plastic substrate comprises a cadmium telluride p-type layer and a cadmium sulfide n-type layer sputter deposited onto a plastic substrate at a temperature sufficiently low to avoid damaging or melting the plastic and to minimize crystallization of the cadmium telluride. A transparent conductive oxide layer overlaid by a bus bar network is deposited over the n-type layer. A back contact layer of conductive metal is deposited underneath the p-type layer and completes the current collection circuit. The semiconductor layers may be amorphous or polycrystalline in structure.

Abstract: Selenium (or tellurium or sulfur) is doped as an n-type dopant by homogeneous doping or planar doping in a compound semiconductor epitaxial wafer to form a selenium-doped layer. Thus, an epitaxial wafer having high carrier density can be prepared. The use of this epitaxial wafer can lower parasitic resistance and can provide HEMT having high gm. Further, the lowered resistance can significantly increase the freedom of device design.

Abstract: An element structure is provided in which film formation irregularities and deterioration of an organic compound layer formed on an electrode are prevented in an active matrix light emitting device. After forming an insulating film so as to cover edge portions of a conductor which becomes a light emitting element electrode, polishing is performed using a CMP (chemical mechanical polishing) method in the present invention, thus forming a structure in which surfaces of a first electrode and a leveled insulating layer are coplanar. The film formation irregularities in the organic compound layer formed on the electrode can thus be prevented, and electric field concentration from the edge portions of the electrode can be prevented.

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening and a conductor core filling the channel opening. A via stop layer is formed over the channel dielectric layer to have a hydrogen concentration below 15 atomic % and a via dielectric layer is formed over the via stop layer and has a via opening. A second channel dielectric layer over the via dielectric layer has a second channel opening. A second conductor core, filling the second channel opening and the via opening, is connected to the semiconductor device.

Abstract: An ingot plate (10) of cleaveable thermoelectric material has a layered structure having substantially parallel cleavage planes. Substantially all of the cleavage planes are disposed at a less cleavage angle with respect to the upper and lower faces (11, 12) of the plate. The ingot plate can be successfully cut into bars (20) along cutting planes generally perpendicular to the cleavage planes without causing substantial interlayer fracture. Electrodes (25) are formed on the opposite sides of the bar which are defined by the cutting planes. The bar is in use to be cut into a number of discrete chips (30) with one of the electrodes fixed on a substrate. Since the cutting is made along planes again generally perpendicular to the cleavage planes of the bar, the bar can be successfully cut into the corresponding chips without causing any substantial fracture.

Abstract: A thin film transistor where source and drain electrodes are film laminates including at least two layers. A first layer film of the laminate, which is formed to a thickness of 10 to 700 .ANG. is in ohmic contact with underlying semiconductor film. A second layer film, formed on the first layer film has a thickness of more than about 2000 .ANG. and is a material having a sufficient adhesion strength even when formed at a temperature which is less than the temperature corresponding to the materials vapor pressure. Further, the materials used for the source and drain electrodes can be formed into thin films by ordinary sputtering or vacuum deposition techniques, low in cost, and readily available.

Abstract: A transistor structure includes an insulated conductive gate spacer or a conductive layer under a nonconductive spacer, together forming a composite spacer, which contacted and driven separately from the conventional gate of the transistor. The gate spacer, conductive layer of a composite spacer or a portion or portions thereof serve as a control or controls for the transistors taking the form of a second gate or second and third gates for the transistors. The transistors may be used throughout an integrated circuit or it may be preferred to use the improved transistor only in critical speed paths of an integrated circuit. Delays within circuits including the improved transistors are reduced since the drain voltage can be higher than VCC and the BVDSS and subthreshold voltage are substantially higher than standard LDD transistors.

Abstract: A multilayer plate for X-ray imaging is provided, which includes a substrate, a biasing electrode and a selenium-based membrane sandwiched between the substrate and the biasing electrode. The selenium-based membrane comprises a thick photoconductive layer of doped amorphous selenium and one or two thin buffer layers. One of the buffer layers is an amorphous arsenic triselenide layer positioned between the photoconductive layer and the substrate, and the other buffer layer is a unipolar conducting layer of alkali doped selenium positioned between the photoconductive layer and the biasing electrode. Preferably both layers are included. A method of producing such multilayer plates is also disclosed.

Abstract: This invention relates to a semiconductor device comprising at least one p-n junction. The junction is formed from a "p" semiconductor contacting an "n" semiconductor. Said device characterized in that at least one of said "p" or "n" semiconductor is a nanoporous crystalline semiconducting material. These nanoporous materials have an intracrystalline nanopore system whose pores are crystallographically regular and have an average pore diameter of about 2.5 to about 30 .ANG.. Additionally, they have a band gap of greater than 0 to about 5 eV which band gap can be modified by removing a portion of the templating agent from the pore system of the materials. The materials which have these properties include, metal polychalcogenide compounds, metal sulfides and selenides, metal oxides, and metal oxysulfides. These materials can be used in a large variety of semiconducting devices such as light emitting diodes, bipolar transistors, etc. A process for preparing these nanoporous materials is also presented.

Abstract: There is provided by this invention logic and memory elements of atomic or near-atomic scale useful in computer central processing units. These elements consist of two quantum dots having opposite states and a third quantum dot situated between the two quantum dots and in physical contact with them. The third quantam dot is of a material which makes the opposite states of the first two quantum dots energetically favorable. In particular, there is provided by the invention a spin flip-flop suitable for use as electronic logic and memory in a quantum computer. The spin flip-flop is designed to have two highly stable states, encoded entirely in the arrangement of electronic spins in the structure. Switching between the two states is accomplished by fast electromagnetic pulsing generally and by optical pulsing in the case of the spin flip-flop.

Abstract: Chalcopyrite compound semiconductor thin films represented by I-III-VI.sub.2-x V.sub.x or I-III-VI.sub.2-x VII.sub.x, and semiconductor devices having a I-III-VI.sub.2 /I-III-VI.sub.2-x V.sub.x or I-III-VI.sub.2 /I-III-VI.sub.2-x VII.sub.x chalcopyrite homojunction are provided. Such chalcopyrite compound semiconductor thin films are produced by radiating molecular beams or ion beams of the I, III, VI, and V or VII group elements simultaneously, or by doping I-III-VI.sub.2 chalcopyrite thin films with VII-group atoms after the formation thereof. Pollution-free solar cells are also provided, which are formed by the steps of forming a structure of a lower electrode, a chalcopyrite semiconductor thin film, and an upper electrode and radiating accelerated ion beams of a V, VII, or VIII group element thereto.

Abstract: Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.

Abstract: A superlattice comprising alternating layers of (PbTeSe).sub.m and (BiSb).sub.n (where m and n are the number of PbTeSe and BiSb monolayers per superlattice period, respectively) having engineered electronic structures for improved thermoelectric cooling materials (and other uses) may be grown by molecular beam epitaxial growth. Preferably, for short periods, n+m<50. However, superlattice films with 10,000 or more such small periods may be grown. For example, the superlattice may comprise alternating layers of (PbTe.sub.1-z Se.sub.z).sub.m and (Bi.sub.x Sb.sub.1-x).sub.n. According to a preferred embodiment, the superlattice comprises a plurality of layers comprising m layers of PbTe.sub.0.8 Se.sub.0.2 and n layers of Bi.sub.0.9 Sb.sub.0.1, where m and n are preferably between 2 and 20.

Abstract: A camera device having favorable multiplication characteristics (quantum efficiency) as well as improved sensitivity in a visible light region (especially the region on the red side) and a method of manufacturing the same are provided. The camera device includes a hole injection stop layer, a first photoelectric converting layer including selenium, a second photoelectric converting layer having spectral sensitivity characteristics which are different from those of the first photoelectric converting layer, a third photoelectric converting layer including selenium, and an electron injection stop layer. As a result, it is possible to improve multiplication characteristics (quantum efficiency) and to improve the sensitivity in the visible light region (especially the region on the red side) simultaneously.

Abstract: There is interposed a buffer film composed of IIa group fluoride and having characteristics of orientation to a surface direction (111), in which mismatching in lattice constant with a crystal element of a semiconductor substrate is large and mismatching in lattice constant with IV-VI group compound ferroelectric substance is small, between the semiconductor substrate having a surface direction (100) and a ferroelectric gate film comprising the IV-VI group compound ferroelectric substance and having characteristics of polarization to the surface direction (111). Since the buffer film is an orientation film in the direction of (111) without influenced by a crystal element of the semiconductor substrate serving as a base material, the ferroelectric gate film can be oriented in the direction of (111) which is the same as the direction of polarization of the ferroelectric substance.

Abstract: Herein disclosed is a CMOSFET, in which an n-channel MISFET Qn has a gate electrode 11n made of n-type polycrystalline silicon, in which a p-channel MISFET Qp has a gate electrode 11p made of p-type polycrystalline silicon, In which the n-channel MISFET Qn and the p-channel MISFET Qp have their respective channel regions formed with heavily doped impurity layers 12p and 12n having the conductivity types identical to those of their wells 3 and 2, and in which the individual heavily doped impurity layers 12p and 12n have their respective surfaces formed with counter-doped layers 13n and 13p having the opposite conductivity types.