With Housing Or Encapsulation Patents (Class 257/433)
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Patent number: 10672428Abstract: A method to record data in a solid substrate comprises modulating a polarization angle of a coherent optical pulsetrain, and, while the polarization angle is being modulated, focusing the coherent optical pulsetrain on a locus moving through the solid substrate at a relative velocity. Here the relative velocity, a width of the locus in a direction of the relative velocity, and a rate of modulation of the polarization angle are such that the substrate receives within the width of the locus two or more pulses of the optical pulsetrain differing in polarization angle. In this manner, the two or more pulses record, in different portions of the substrate within the width of the locus, two or more different symbols.Type: GrantFiled: May 9, 2019Date of Patent: June 2, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Richard John Black, Patrick Neil Anderson, Rokas Drevinskas, Austin Nicholas Donnelly, Hugh David Paul Williams
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Patent number: 10629518Abstract: Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.Type: GrantFiled: August 29, 2018Date of Patent: April 21, 2020Assignee: NXP USA, Inc.Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Vikas Shilimkar, Ramanujam Srinidhi Embar
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Patent number: 10623613Abstract: A camera module with excellent strength is provided. A camera module includes a housing to which a lens unit is attached and a substrate having a certain positional relationship with the lens unit and supported by the housing, where the housing includes an adhesive agent pool provided to a first main plane of the substrate with a certain opposing space and an open end of an adhesive agent path including the opposing space that is provided to a side of a second main plane of the substrate.Type: GrantFiled: June 26, 2018Date of Patent: April 14, 2020Assignee: SMK CorporationInventors: Taku Akaiwa, Nobuyuki Mano
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Patent number: 10620764Abstract: The present disclosure relates to a color filter substrate, a fabrication method thereof, and a display panel. The color filter substrate includes: a substrate including a first surface and a second surface opposite to each other; a color filter film disposed on the first surface of the substrate; and a force sensitive film disposed on the second surface of the substrate. Further, the force sensitive film is configured to act as a conductor when no pressure is applied and as a non-conductor when under pressure.Type: GrantFiled: June 20, 2018Date of Patent: April 14, 2020Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Dongling Sun, Xiaobin Yin, Zhengwei Zhu, Wencheng Hu
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Patent number: 10617397Abstract: A sample capture and transport unit comprises a housing defining a substrate chamber for containing a sample-capture substrate. The housing comprises at least a first part and a second part which are movable relative to one another ? i) from a first closed configuration in which the substrate chamber is inaccessible; ? ii) to a first open configuration in which access to the substrate chamber is enabled to allow capturing of a skin-print on a sample-capture substrate contained within the substrate chamber; and subsequently ? iii) into a second closed configuration in which the substrate chamber is again inaccessible. The unit further comprises a retaining mechanism for retaining it in the second closed configuration. The retaining mechanism is disablable to permit movement of the unit out of the second closed configuration. A sample can be obtained at a first location, secured for transport and analysed at a second location.Type: GrantFiled: August 22, 2014Date of Patent: April 14, 2020Assignee: INTELLIGENT FINGERPRINTING LIMITEDInventors: Mark Hudson, Nicholas Earl, Daniel Peterson Godfrey, John Dunton
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Patent number: 10624204Abstract: An optical module includes a conductor plate including a first through hole, a signal lead terminal fixed to the first through hole, and a wiring circuit board. The wiring circuit board includes a signal strip conductor member and a land on a first surface and a ground conductor layer and a second through hole on a second surface, the land surrounds the second through hole and is in contact with the signal strip conductor member, the signal lead terminal and the land are physically connected to each other through a solder and thus the signal lead terminal and the signal strip conductor member are electrically connected to each other, and at least a part of the land spreads outwardly, in a plan view, from not only a portion in contact with the signal strip conductor member but also an outer edge of the first through hole.Type: GrantFiled: August 24, 2018Date of Patent: April 14, 2020Assignee: Lumentum Japan, Inc.Inventors: Daisuke Noguchi, Hiroshi Yamamoto
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Patent number: 10497731Abstract: A photoelectric conversion device includes a semiconductor substrate having a photoelectric conversion unit, a magnetic layer arranged over an opposite side to a light-receiving face of the semiconductor substrate, and an infrared ray absorbing layer arranged between the semiconductor substrate and the magnetic layer.Type: GrantFiled: February 5, 2018Date of Patent: December 3, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Yuichi Kazue, Takahiro Hachisu
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Patent number: 10490583Abstract: A packaging structure and a packaging method are provided. The packaging structure includes: a chip unit, where a first surface of the chip unit includes a sensing region; and an upper cover plate structure, where a first surface of the upper cover plate structure is provided with a groove structure, the first surface of the chip unit is attached with the first surface of the upper cover plate structure, the sensing region is located within a cavity surrounded by the groove structure and the first surface of the chip unit, the upper cover plate structure further includes a second surface opposite to the first surface, and an area of the second surface of the upper cover plate structure is less than an area of the first surface of the upper cover plate structure.Type: GrantFiled: August 5, 2016Date of Patent: November 26, 2019Assignee: China Wafer Level CSP Co., Ltd.Inventors: Zhiqi Wang, Fangyuan Hong
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Patent number: 10459241Abstract: Imaging apparatus and methods using diffraction-based illumination are disclosed. An example apparatus includes a diffraction grating to redirect light from a light source toward a sample to thereby illuminate the sample. The example apparatus also includes an image sensor to detect a diffraction pattern created by the illuminated sample.Type: GrantFiled: April 30, 2014Date of Patent: October 29, 2019Assignee: Hewlett-Packard Development Company, L.P.Inventors: Charles M Santori, Alexander Govyadinov
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Patent number: 10461116Abstract: The present invention provides a semiconductor packaging method and semiconductor device based on a molding process. In the packaging method, first, at least a portion of a compensation part is kept on at least a portion of a bonding region formed between a first adjoining surface of a semiconductor element and a second adjoining surface of a packaging component, to form a semi-finished product of a semiconductor device; then, during hardening of the packaging component, the compensation part is caused to undergo different degrees of deformation at different positions to compensate for a difference between a magnitude of deformation of the packaging component and a magnitude of deformation of the semiconductor element, so as to package the semiconductor element to form the semiconductor device. By means of the method, undesirable phenomena such as cracking and deformation of the surface of the semiconductor element can be avoided.Type: GrantFiled: April 6, 2018Date of Patent: October 29, 2019Assignee: NINGBO SUNNY OPOTECH CO., LTD.Inventors: Mingzhu Wang, Bojie Zhao, Takehiko Tanaka, Zhenyu Chen, Heng Jiang, Nan Guo
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Patent number: 10418294Abstract: A described example includes: a die with an active surface; a cap mounted over a portion of the active surface of the die; and mold compound covering the cap and covering portions of the die, the cap excluding the mold compound from contact with the portion of the active surface of the die.Type: GrantFiled: May 15, 2018Date of Patent: September 17, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Laura May Antoinette Dela Paz Clemente, Jerry Gomez Cayabyab
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Patent number: 10378736Abstract: An LED bracket, LED bracket array, LED device and LED display screen are disclosed. The LED bracket includes a PCB circuit substrate and an insulating material. The PCB circuit substrate includes at least two electrically insulated electrode regions. Each electrode region includes a top electrode region, a side electrode region and a bottom electrode region. The side electrode region connects the top electrode region and the bottom electrode region into an integrated structure. The side electrode region is a side surface sunk from outside to an inner part of the PCB circuit substrate. The insulating material is filled in the side electrode region. An upper end surface and a lower end surface of the insulating material do not exceed an upper surface and a lower surface of the PCB circuit substrate. A thickness of the insulating material is less than a thickness of the PCB circuit substrate.Type: GrantFiled: October 31, 2017Date of Patent: August 13, 2019Assignee: Foshan NationStar Optoelectronics Co., Ltd.Inventors: Chuanbiao Liu, Feng Gu, Yuanbin Lin, Xiangling Luo, Xiaofeng Liu, Xi Zheng, Yan Liu
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Patent number: 10347774Abstract: A problem addressed by an embodiment of the present invention lies in providing a UBM structure which includes thin layers and can prevent diffusion of solder into an electrode. The UBM structure according to an embodiment of the present invention includes: a first UBM layer on an electrode, a second UBM layer on the first UBM layer, and a passivated metal layer between the first UBM layer and the second UBM layer. The passivated metal layer functions as a barrier layer with respect to solder diffusion.Type: GrantFiled: February 25, 2015Date of Patent: July 9, 2019Assignee: SIEMENS AKTIENGESELLSCHAFTInventors: Noriyuki Kishi, Tatsuhiro Koizumi, Hiroyuki Shiraki, Mitsuru Tamashiro, Masaya Yamamoto
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Patent number: 10304815Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: GrantFiled: November 3, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 10298818Abstract: A camera for a vision system for a vehicle includes an imager chip having an at least partially light transmitting substrate having a photosensor array disposed at a second surface of the at least partially light transmitting substrate so as to sense light that passes through the at least partially light transmitting substrate. The imager chip includes electrically conductive pads disposed at the second surface of the at least partially light transmitting substrate. A circuit element includes circuitry disposed at least at a third surface thereof. The imager chip is mounted at the circuit element with the second surface of the at least partially light transmitting substrate opposing the third surface of the circuit element. Electrical connection between the electrically conductive pads and the circuitry of the circuit element is made when mounting the imager chip at the circuit element.Type: GrantFiled: March 22, 2016Date of Patent: May 21, 2019Assignee: MAGNA ELECTRONICS INC.Inventor: Christopher L. Van Dan Elzen
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Imaging device, optical device, electronic device, vehicle, and production method for imaging device
Patent number: 10288985Abstract: An imaging device having a lens group; a lens barrel holding the lens group; a base member holding the lens barrel; an imaging element; a fixed plate arranged facing at least part of the base member in a state in which the imaging element is fixed; and a pressing member for attaching, to the base member, the fixed plate in a state in which the fixed plate is temporarily fixed to the base member in a state in which fixed plate is movable in a direction intersecting the axial line of the lens group, relative to the base member.Type: GrantFiled: August 26, 2015Date of Patent: May 14, 2019Assignee: Nidec Copal CorporationInventors: Yuta Nakamura, Ryo Kikuta -
Patent number: 10276506Abstract: A semiconductor device including an integrated circuit, a protection layer, and a conductive via is provided. The integrated circuit includes at least one conductive pad. The protection layer covers the integrated circuit. The protection layer includes a contact opening, and the conductive pad is exposed by the contact opening of the protection layer. The conductive via is embedded in the contact opening of the protection layer, and the conductive via is electrically connected to the conductive pad through the contact opening. A method of fabricating the above-mentioned semiconductor device and an integrated fan-out package including the above-mentioned semiconductor device are also provided.Type: GrantFiled: July 21, 2016Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Yen Chiu, Ching-Fu Chang, Hsin-Chieh Huang
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Patent number: 10269852Abstract: A device includes a first integrated circuit containing a photodiode and a first metal interconnect structure connected to the photodiode, and a second integrated circuit containing a transistor and a second metal interconnect structure connected to the transistor. The first integrated circuit and the second integrated circuit are connected together through the first metal interconnect structure and the second metal interconnect structure. Since no transistor is present around the photodiode, the photodiode has an increased photosensitive area and an improved fill factor, resulting in an increase of the quantum efficiency, higher integration and lower consumption of the image sensor.Type: GrantFiled: June 26, 2015Date of Patent: April 23, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATIONInventors: Jerry Liu, Phil Wu, Herb He Huang
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Patent number: 10217879Abstract: The present invention provides an optical semiconductor device in which damage of a lens when being mounted and mounting displacement due to suction failures of a chip can be suppressed. An optical semiconductor device according to an embodiment includes: a semiconductor substrate having a first surface and a second surface facing the first surface; an electrode formed over the first surface of the semiconductor substrate; an optical element that is electrically coupled to the electrode and is formed in the semiconductor substrate; and a lens arranged on the second surface side of the optical element. A concave part is formed in the second surface of the semiconductor substrate, and the lens is arranged at the bottom of the concave part. A top part on the second surface side of the lens is located on the first surface side relative to the second surface located around the concave part.Type: GrantFiled: December 14, 2016Date of Patent: February 26, 2019Assignee: Renesas Electronics CorporationInventor: Yoshito Taniguchi
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Patent number: 10211249Abstract: An x-ray detector includes a substrate including an electrically conductive connection between a read-out contact in the region of the top side of the substrate and an input of a pre-amplifier in an active layer of an integrated circuit. A first electrically conductive connection is provided between the read-out contact and a second electrically conductive connection. A surface of a first light protection is relatively larger than a surface of a light-permeable region of the first light protection. The second electrically conductive connection is provided within a second projection of the surface of the light-permeable region along the surface normal and below the second light protection. A third electrically conductive connection between the second electrically conductive connection and the pre-amplifier is provided below the second light protection. The input of the pre-amplifier is protected against direct incidence of light.Type: GrantFiled: June 3, 2016Date of Patent: February 19, 2019Assignee: SIEMENS HEALTHCARE GMBHInventors: Martin Groepl, Edgar Goederer, Thomas Suttorp
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Patent number: 10197750Abstract: A light guiding structure is provided. The structure includes an anodized aluminum oxide (AAO) layer and a fluoropolymer layer located immediately adjacent to a surface of the AAO layer. Light propagates through the AAO layer in a direction substantially parallel to the fluoropolymer layer. An optoelectronic device can be coupled to a surface of the AAO layer, and emit/sense light propagating through the AAO layer. Solutions for fabricating the light guiding structure are also described.Type: GrantFiled: December 26, 2017Date of Patent: February 5, 2019Assignee: Sensor Electronic Technology, Inc.Inventors: Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Patent number: 10183858Abstract: The present disclosure provides a semiconductor structure includes a sensing element configured to receive a signal from a sensing target, a molding surrounding the sensing element, a through via in the molding, a front side redistribution layer disposed at a front side of the sensing element and electrically connected thereto, and a back side redistribution layer disposed at a back side of the sensing element, the front side redistribution layer and the back side redistribution layer are electrically connected by the through via. The present disclosure also provides a method for manufacturing the semiconductor structure described herein.Type: GrantFiled: March 10, 2017Date of Patent: January 22, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Albert Wan, Yu-Sheng Hsieh, Chao-Wen Shih, Shou Zen Chang, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 10177098Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.Type: GrantFiled: January 19, 2017Date of Patent: January 8, 2019Assignee: STMicroelectronics (Grenoble 2) SASInventors: Karine Saxod, Marika Sorrieul
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Patent number: 10170440Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad, and a second bonding pad on a top surface of the stacking structure, wherein a shortest distance between the first bonding pad and the second bonding pad is less than 150 ?m; a carrier comprising a connecting surface; a third bonding pad and a fourth bonding pad on the connecting surface of the carrier; and a conductive connecting layer comprising a current conductive area between the first bonding pad and the third bonding pad and between the second bonding pad and the fourth bonding pad.Type: GrantFiled: March 15, 2017Date of Patent: January 1, 2019Assignee: EPISTAR CORPORATIONInventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
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Patent number: 10157274Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.Type: GrantFiled: February 23, 2018Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 10156717Abstract: In an electro-optical device, light is incident on a mirror by penetrating a cover, and the light reflected by the mirror is emitted by penetrating the cover. Here, the cover includes a first light-transmitting plate and a second light-transmitting plate facing the first light-transmitting plate, and a gap which is open toward both sides in a first direction is provided between the first light-transmitting plate and the second light-transmitting plate due to a spacer.Type: GrantFiled: November 10, 2016Date of Patent: December 18, 2018Assignee: SEIKO EPSON CORPORATIONInventor: Yasuo Yamasaki
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Patent number: 10153235Abstract: The present disclosure relates to an image sensor device including: a fan-out semiconductor package including a first semiconductor chip having an active surface on which a connection pad is disposed, a first connection member disposed on the active surface and including a redistribution layer electrically connected to the connection pad of the first semiconductor chip, and a sealing material disposed on the first connection member and sealing at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the first connection member and electrically connected to the first connection member; and a third semiconductor chip disposed on the second semiconductor chip and electrically connected to the second semiconductor chip, in which at least one of the second semiconductor chip or the third semiconductor chip may be an image sensor. The present disclosure also relates to an image sensor module including the image sensor device.Type: GrantFiled: August 21, 2017Date of Patent: December 11, 2018Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Dae Kwon Jung, Bang Chul Ko, Chul Choi, Jung Hyun Cho, Joo Hwan Jung, Yong Ho Baek, Seung Eun Lee
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Patent number: 10141286Abstract: Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.Type: GrantFiled: April 27, 2017Date of Patent: November 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Il Lee, Cha-Jea Jo, Ji-Hwang Kim
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Patent number: 10134957Abstract: A surface-mountable optoelectronic semiconductor component is specified. The surface-mountable optoelectronic semiconductor component includes an optoelectronic semiconductor chip, a radiation-transmissive growth substrate, a housing body and an electrically conductive connection. The housing body is arranged at least in places between a side surface of the growth substrate and the electrically conductive connection. The housing body completely covers all of the side surfaces of the growth substrate, and the housing body has, on a surface facing away from the side surface of the growth substrate, traces of material removal or traces of a form tool.Type: GrantFiled: July 16, 2014Date of Patent: November 20, 2018Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventor: Norwin von Malm
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Patent number: 10134961Abstract: Submount based surface mount design (SMD) light emitter components and related methods are disclosed. In one aspect, a method of providing a submount based light emitter component can include providing a ceramic based submount, providing at least one light emitter chip on the submount, providing at least one electrical contact on a portion of the submount, and providing a non-ceramic based reflector cavity on a portion of the submount.Type: GrantFiled: March 13, 2013Date of Patent: November 20, 2018Assignee: Cree, Inc.Inventors: Jesse Colin Reiherzer, Christopher P. Hussell
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Patent number: 10129452Abstract: A camera module and an array camera module based on an integral packing process are disclosed. The camera module or each of the camera module units of the array camera module includes a circuit board, an integral base, a photosensitive element operatively connected to the circuit board, a lens, a light filter holder installed at the integral base and a light filter installed at the light filter holder. The light filter is not required to be directly installed to the integral base, so that the light filter is protected and the requiring area of the light filter is reduced.Type: GrantFiled: June 19, 2017Date of Patent: November 13, 2018Assignee: Ningbo Sunny Opotech Co., Ltd.Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Nan Guo, Takehiko Tanaka
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Patent number: 10083939Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.Type: GrantFiled: January 31, 2017Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-kyoung Seo, Cha-jea Jo, Soo-hyun Ha
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Patent number: 10084135Abstract: An illumination device includes a substrate, a light emitting structure, a sealant, and a laminating board is provided. The light emitting structure includes a first electrode layer, a light emitting layer and a second electrode layer stacked on the substrate sequentially. The sealant covers the light emitting structure. The laminating board is attached to the substrate. The sealant is located between the laminating board and the substrate. The laminating board includes a carrier body, a metal layer and a plurality of pads. The metal layer is exposed at a first surface of the carrier body, is in contact with the sealant and shields an area of the light emitting layer of the light emitting structure. The pads are exposed at the first surface of the carrier body and electrically connected to the first electrode layer and the second electrode layer. The metal layer is electrically isolated from the pads.Type: GrantFiled: November 24, 2015Date of Patent: September 25, 2018Assignee: Industrial Technology Research InstituteInventors: Hsuan-Yu Lin, Hsin-Chu Chen, Wen-Hong Liu, Chao-Feng Sung, Chun-Ting Liu, Je-Ping Hu, Wen-Yung Yeh
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Patent number: 10079198Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.Type: GrantFiled: May 31, 2017Date of Patent: September 18, 2018Assignee: STMicroelectronics, Inc.Inventors: Aaron Cadag, Ernesto Antilano, Jr., Ela Mia Cadag
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Patent number: 10078007Abstract: An infrared sensor includes an infrared detecting device, a lens, a member, a gap and a spacer. The lens is disposed above the infrared detecting device. The member forms an external surface and includes a first opening having a maximum internal diameter. The gap is disposed between the member and the lens. The spacer is disposed between the member and the lens so as to form the gap, and that is directly contact with lens. The spacer has a circular inner periphery, in planar view, which has a larger internal diameter than the maximum internal diameter of the first opening of the member.Type: GrantFiled: January 11, 2017Date of Patent: September 18, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takafumi Okudo, Takahiro Miyatake, Yoshiharu Sanagawa, Masao Kirihara, Yoichi Nishijima, Takanori Aketa, Ryo Tomoida
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Patent number: 10060820Abstract: Suspending a microelectromechanical system (MEMS) pressure sensing element inside a cavity using spring-like corrugations or serpentine crenellations, reduces thermally-mismatched mechanical stress on the sensing element. Overlaying the spring-like structures and the sensing element with a gel further reduces thermally-mismatched stress and vibrational dynamic stress.Type: GrantFiled: July 13, 2016Date of Patent: August 28, 2018Assignee: Continental Automotive Systems, Inc.Inventors: Shiuh-Hui Steven Chen, Jen-Huang Albert Chiou, Robert C. Kosberg, Daniel Roy Empen
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Patent number: 10020343Abstract: Systems and methods may be provided for fabricating infrared focal plane arrays. The methods include providing a device wafer, applying a coating to the device wafer, mounting the device wafer to a first carrier wafer, thinning the device wafer while the device wafer is mounted to the first carrier wafer, releasing the device wafer from the first carrier wafer, singulating the device wafer into individual dies, each die having an infrared focal plane array, and hybridizing the individual dies to a read out integrated circuit.Type: GrantFiled: September 23, 2016Date of Patent: July 10, 2018Assignee: FLIR Systems, Inc.Inventors: Edward K. Huang, Andrew D. Hood, Bryan Gall, Paula Heu, Richard E. Bornfreund
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Patent number: 9991621Abstract: An optoelectronic arrangement includes a first circuit board, a second circuit board, and an optoelectronic semiconductor chip arranged on the first circuit board, wherein a first electrical contact surface and a second electrical contact surface are formed on a surface of the first circuit board, a first mating contact surface and a second mating contact surface are formed on a surface of the second circuit board, and the first circuit board and the second circuit board connect to one another such that the surface of the first circuit board faces toward the surface of the second circuit board, and the first mating contact surface electrically conductively connects to the first contact surface and the second mating contact surface electrically conductively connects to the second contact surface.Type: GrantFiled: May 15, 2014Date of Patent: June 5, 2018Assignee: OSRAM Opto Semiconductors GmbHInventors: Konrad Wagner, Jürgen Holz
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Patent number: 9972729Abstract: A p? type semiconductor substrate 20 has a first principal surface 20a and a second principal surface 20b opposed to each other and includes a photosensitive region 21. The photosensitive region 21 is composed of an n+ type impurity region 23, a p+ type impurity region 25, and a region to be depleted with application of a bias voltage in the p? type semiconductor substrate 20. An irregular asperity 10 is formed in the second principal surface 20b of the p? type semiconductor substrate 20. An accumulation layer 37 is formed on the second principal surface 20b side of the p? type semiconductor substrate 20 and a region in the accumulation layer 37 opposed to the photosensitive region 21 is optically exposed.Type: GrantFiled: February 16, 2017Date of Patent: May 15, 2018Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Kazuhisa Yamamura, Akira Sakamoto, Terumasa Nagano, Yoshitaka Ishikawa, Satoshi Kawai
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Patent number: 9955055Abstract: An array imaging module includes at least two optical lenses and a molded photosensitive assembly, wherein the molded photosensitive assembly includes at least two photosensitive units, a circuit board that electrically couples to the photosensitive units, and a molded base having at least two optical windows. The molded base is integrally coupled at the circuit board at a peripheral portion thereof, wherein the photosensitive units are aligned with the optical windows respectively. The optical lenses are located along two photosensitive paths of the photosensitive units respectively, such that each of the optical windows forms a light channel through the corresponding photosensitive unit and the corresponding optical lens.Type: GrantFiled: March 15, 2017Date of Patent: April 24, 2018Assignee: Ningbo Sunny Opotech Co., Ltd.Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Takehiko Tanaka, Nan Guo, Zhen Huang, Duanliang Cheng, Liang Ding, Feifan Chen, Heng Jiang
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Patent number: 9910147Abstract: A radar antenna is provided. The radar antenna includes a radar case having a front side and a rear side, a signal processor provided inside the radar case and configured to perform signal processing on a reception signal that is received by an EM radiator configured to transceive an electromagnetic wave, and a wireless LAN antenna fixed inside the radar case, having a horizontal directivity, and configured to transmit the reception signal processed by the signal processor to an external terminal device, the wireless LAN antenna being oriented such that a direction of the horizontal directivity of the wireless LAN antenna is in parallel to the front-and-rear directions of the radar case.Type: GrantFiled: February 4, 2015Date of Patent: March 6, 2018Assignee: Furuno Electric Co., Ltd.Inventors: Koji Atsumi, Dai Takemoto, Tetsuya Miyagawa
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Patent number: 9911726Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.Type: GrantFiled: June 16, 2017Date of Patent: March 6, 2018Assignee: International Business Machines CorporationInventor: Philip G. Emma
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Patent number: 9904776Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.Type: GrantFiled: July 1, 2016Date of Patent: February 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 9892304Abstract: A fingerprint identification device includes a fingerprint identification controller and a fingerprint identification sensor. The fingerprint identification sensor includes a substrate having a top surface, a bottom surface opposite to the top surface, and a side surface coupled between the top surface and the bottom surface. Sensor electrodes are arranged on the top surface, electrical leads couple the sensor electrodes and the fingerprint identification controller. The coupling leads extend from the top surface along the side surface to the bottom surface.Type: GrantFiled: October 22, 2015Date of Patent: February 13, 2018Assignees: INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITEDInventors: Chun-Te Chang, Chia-Chun Tai, Wei-Chung Chuang, Yen-Heng Huang
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Patent number: 9874486Abstract: Systems and methods for packaging a MEMS device are provided. Embodiments herein avoid the use of a metal housing enclosing the MEMS device or die pad of the MEMS device. Instead, a metal port is mounted directly to the MEMS device using a ceramic carrier. In preferred embodiments, the ceramic carrier is soldered, brazed, welded or eutectic bonded to the metal port.Type: GrantFiled: January 5, 2016Date of Patent: January 23, 2018Assignee: DUNAN SENSING, LLCInventors: Gary Winzeler, Danny Do, Cuong D. Nguyen, Emir Vukotic
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Patent number: 9846067Abstract: A flow sensor structure seals the surface of an electric control circuit and part of a semiconductor device via a manufacturing method that prevents occurrence of flash or chip crack when clamping the semiconductor device via a mold. The flow sensor structure includes a semiconductor device having an air flow sensing unit and a diaphragm, and a board or lead frame having an electric control circuit for controlling the semiconductor device, wherein a surface of the electric control circuit and part of a surface of the semiconductor device is covered with resin while having the air flow sensing unit portion exposed. The flow sensor structure may include surfaces of a resin mold, a board or a pre-mold component surrounding the semiconductor device that are continuously not in contact with three walls of the semiconductor device orthogonal to a side on which the air flow sensing unit portion is disposed.Type: GrantFiled: January 26, 2015Date of Patent: December 19, 2017Assignee: Hitachi Automotive Systems, Ltd.Inventors: Tsutomu Kono, Yuuki Okamoto, Takeshi Morino, Keiji Hanzawa
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Patent number: 9838579Abstract: A method for producing a camera includes: mounting an image sensor on a circuit carrier and contacting with a power device for recording image signals of the image sensor; measuring an objective while ascertaining a tilting angle of its optical axis in terms of an amount and azimuth; providing an objective holder having a tube and locating pins; placing the objective holder with its locating pins on at least one of the circuit carrier and the image sensor; inserting the objective in a specified rotational position or at an azimuth angle into the tube as a function of the ascertained tilting angle; and adjusting the focus. An axis of symmetry of the tube of the objective holder has a counter-tilting angle with respect to a surface normal of the image sensor, which is the opposite of the ascertained tilting angle or the image shell tilting of the objective.Type: GrantFiled: June 16, 2015Date of Patent: December 5, 2017Assignee: ROBERT BOSCH GMBHInventor: Martin Reiche
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Patent number: 9806056Abstract: Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.Type: GrantFiled: February 15, 2016Date of Patent: October 31, 2017Assignee: Infineon Technologies AGInventors: Ulrich Wachter, Dominic Maier, Thomas Kilger
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Patent number: 9791990Abstract: Embodiments of the disclosure generally provide an integrated control system having an integrated controller that is configured to provide both display updating signals to a display device and a capacitive sensing signal to a sensor electrode that is disposed within the integrated input device. The internal and/or external signal routing configurations described herein can be adapted to reduce signal routing complexity typically found in conventional devices and reduce the effect of electrical interference created by the capacitive coupling formed between the display routing, capacitive sensing routing and/or other components within the integrated control system. Embodiments can also be used to reduce electromagnetic interference (EMI) on the display and touch sensing signals received, transmitted and processed within the integrated control system.Type: GrantFiled: March 14, 2016Date of Patent: October 17, 2017Assignee: SYNAPTICS INCORPORATEDInventor: Christopher A. Ludden
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Patent number: 9780135Abstract: An image pickup device and a method of the same are described herein. By way of first example, the image pickup device includes a seal member having a first surface, the first surface of the seal member including a concave portion, and an optical device coupled to a second surface of the seal member, the second surface of the seal member being opposite from the first surface of the seal member. By way of a second example, the image pickup device includes a seal member having a first surface, the first surface being a polished surface, and an optical device coupled to a second surface of the seal member, the second surface of the seal member being opposite from the first surface of the seal member.Type: GrantFiled: January 4, 2013Date of Patent: October 3, 2017Assignee: Sony CorporationInventors: Masaya Nagata, Taizo Takachi