With Specific Isolation Means In Integrated Circuit Patents (Class 257/446)
  • Patent number: 8674417
    Abstract: A solid-state imaging device including: a substrate; a light-receiving part; a second-conductivity-type isolation layer; a detection transistor; and a reset transistor.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: March 18, 2014
    Assignee: Sony Corporation
    Inventor: Isao Hirota
  • Patent number: 8659109
    Abstract: An image sensor including a plurality of pixels each including a charge collection region including an N-type region bounded by P-type regions and having an overlying P-type layer; and an insulated gate electrode positioned over the P-type layer and arranged to receive a gate voltage for conveying charges stored in the charge collection region through the P-type layer.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: February 25, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: François Roy
  • Patent number: 8643034
    Abstract: An optoelectronic semiconductor body comprises a semiconductor layer sequence which is subdivided into at least two electrically isolated subsegments. The semiconductor layer sequence has an active layer in each subarea. Furthermore, at least three electrical contact pads are provided. A first line level makes contact with a first of the at least two subsegments and with the first contact pad. A second line level makes contact with the second of the at least two subsegments and with a second contact pad. A third line level connects the two subsegments to one another and makes contact with the third contact pad. Furthermore, the line levels are each arranged opposite a first main face, wherein the first main face is intended to emit electromagnetic radiation that is produced.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: February 4, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Karl Engl, Frank Singer, Patrick Rode, Lutz Hoeppel, Martin Strassburg
  • Patent number: 8614113
    Abstract: An image sensor and a method for fabricating the image sensor are provided. The method for fabricating the image sensor includes forming a first insulating layer on a semiconductor epitaxial layer having multiple pixel regions; patterning a portion of the semiconductor epitaxial layer and the first insulating layer in a boundary region between the pixel regions to form a trench; forming a buried insulating layer on the first insulating layer, filling the trench, the buried insulating layer having a planar top surface; forming a second insulating layer on the buried insulating layer; forming a first mask pattern on the second insulating layer, the first mask pattern defining an opening overlapping the trench; and performing an ion implantation process using the first mask pattern as an ion implantation mask to form a first type potential barrier region in a bottom of the trench.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Jin Ahn, Duck-Hyung Lee, Jong-Cheol Shin, Chang-Rok Moon, Sang-Jun Choi, Eun-Kyung Park
  • Patent number: 8604408
    Abstract: A solid-state imaging device includes: a pixel having a photodiode and a pixel transistor; a first isolation region using a semiconductor region containing impurities formed between neighboring photodiodes; and a second isolation region using an semiconductor region containing impurities formed between the photodiode and the pixel transistor, wherein an impurity concentration of the first isolation region is different from an impurity concentration of the second isolation region.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: December 10, 2013
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Fumihiko Koga, Toshifumi Wakano, Takashi Nagano
  • Publication number: 20130320473
    Abstract: A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.
    Type: Application
    Filed: June 27, 2013
    Publication date: December 5, 2013
    Inventor: Keiji Mabuchi
  • Patent number: 8592934
    Abstract: On the front side of an n-type semiconductor substrate 5, p-type regions 7 are two-dimensionally arranged in an array. A high-concentration n-type region 9 and a p-type region 11 are disposed between the p-type regions 7 adjacent each other. The high-concentration n-type region 9 is formed by diffusing an n-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 as seen from the front side. The p-type region 11 is formed by diffusing a p-type impurity from the front side of the substrate 5 so as to surround the p-type region 7 and high-concentration n-type region 9 as seen from the front side. Formed on the front side of the n-type semiconductor substrate 5 are an electrode 15 electrically connected to the p-type region 7 and an electrode 19 electrically connected to the high-concentration n-type region 9 and the p-type region 11.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: November 26, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Tatsumi Yamanaka
  • Publication number: 20130299935
    Abstract: A method for manufacturing an image sensor may include at least one of the following steps. Forming at least one device isolation layer that passes through an epitaxial layer in a semiconductor substrate to isolate pixel regions. Forming a light-receiving element in each pixel region. The method may include forming a transistor in the active region of the semiconductor substrate partitioned by the device isolation layer.
    Type: Application
    Filed: January 28, 2013
    Publication date: November 14, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventor: Jin Youn CHO
  • Patent number: 8581108
    Abstract: The present invention is a method for providing an integrated circuit assembly, the integrated circuit assembly including an integrated circuit and a substrate. The method includes mounting the integrated circuit to the substrate. The method further includes, during assembly of the integrated circuit assembly, applying a low processing temperature, at least near-hermetic, glass-based coating directly to the integrated circuit and a localized interconnect interface, the interface being configured for connecting the integrated circuit to at least one of the substrate and a second integrated circuit of the assembly. The method further includes curing the coating. Further, the integrated circuit may be a device which is available for at least one of sale, lease and license to a general public, such as a Commercial off the Shelf (COTS) device. Still further, the coating may promote corrosion resistance and reliability of the integrated circuit assembly.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: November 12, 2013
    Assignee: Rockwell Collins, Inc.
    Inventors: Alan P. Boone, Nathan P. Lower, Ross K. Wilcoxon
  • Patent number: 8574945
    Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Delfo Nunziato Sanfilippo, Emilio Antonio Sciacca, Piero Giorgio Fallica, Salvatore Antonio Lombardo
  • Patent number: 8570418
    Abstract: A photoelectric conversion apparatus (100) comprises: multiple photoelectric converting units (PD) disposed in a semiconductor substrate; (SB) and isolation portions (103,104,105,106) disposed in the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 29, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takanori Watanabe
  • Patent number: 8558340
    Abstract: Disclosed herein is a semiconductor device including an element isolation region configured to be formed on a semiconductor substrate, wherein the element isolation region is formed of a multistep trench in which trenches having different diameters are stacked and diameter of an opening part of the lower trench is smaller than diameter of a bottom of the upper trench.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: October 15, 2013
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami
  • Patent number: 8558319
    Abstract: A semiconductor memory device includes a substrate and a plurality of rows of memory cells. The substrate comprises a plurality of isolation structures and a plurality of active regions. Each of the active regions is spaced apart from another active region by one of the isolation structures. In a cross-section of the substrate between two rows of memory cells in a direction parallel to the two rows of memory cells, a maximum height of each isolation structure with respect to a bottom of the substrate is lower than or equal to minimum heights of active regions adjacent thereto.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: October 15, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Lo-Yueh Lin
  • Publication number: 20130264673
    Abstract: A solid-state imaging device with a semiconductor substrate; a pixel formation region in the substrate and including a pixel made of a photoelectric conversion element; and an element isolation portion in the substrate and including an element isolation insulating layer and an impurity element isolation region. The element isolation insulating layer is positioned in a surface of the substrate. The impurity element isolation region is positioned under the element isolation insulating layer and within the substrate. The impurity element isolation region has at least a portion with a width that is narrower than that of the element isolation insulating layer. The photoelectric conversion element extends to a position under the element isolation insulating layer of the element isolation portion.
    Type: Application
    Filed: June 6, 2013
    Publication date: October 10, 2013
    Inventor: Ikuo Yoshihara
  • Publication number: 20130249041
    Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.
    Type: Application
    Filed: May 10, 2013
    Publication date: September 26, 2013
    Inventors: Jen-Cheng Liu, Ching-Hung Cheng, Chien-Hsien Tseng, Chia-Hao Hsu, Feng-Jia Shiu, Shou-Gwo Wuu
  • Publication number: 20130241023
    Abstract: A method for manufacturing a solid-state image pickup device is provided. In this method, a pixel isolation member is formed in a semiconductor substrate including pixels, and the thickness of the substrate is reduced by CMP. For forming the pixel isolation member, a first pixel isolation member is formed by implanting impurity ions in a region of the substrate so that the pixels are disposed between portions of the region when viewed from a surface of the substrate. A second isolation member is also formed by forming a trench in a region of the substrate different from the first pixel isolation member so that the pixels are disposed between portions of the region, and then filling the trench with an electroconductive material harder to polish by CMP than the substrate. The CMP is performed on the rear side of the substrate using the second pixel isolation member as a stopper.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 19, 2013
    Applicant: SONY CORPORATION
    Inventors: KENICHI NISHIZAWA, HIROSHI TAKAHASHI
  • Patent number: 8519506
    Abstract: A galvanic isolation integrated circuit system includes a semiconductor substrate; a layer of thermally conductive material, e.g., CVD nano- or poly-diamond thin film or boron nitride CVD thin film, formed over the semiconductor substrate; a first integrated circuit structure formed over the layer of thermally conductive material; a second integrated circuit structure formed over the layer of thermally conductive material, the second integrated circuit structure being spaced apart from the first integrated circuit structure; and a galvanic isolation structure formed over the layer of thermally conductive material between the first and second integrated circuit structures and connected to the first integrated circuit structure and the second integrated circuit structure.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 27, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Ann Gabrys
  • Patent number: 8513759
    Abstract: A photodiode array for near infrared rays that includes photodiodes having a uniform size and a uniform shape, has high selectivity for the wavelength of received light between the photodiodes, and has high sensitivity with the aid of a high-quality semiconducting crystal containing a large amount of nitrogen, a method for manufacturing the photodiode array, and an optical measurement system are provided. The steps of forming a mask layer 2 having a plurality of openings on a first-conductive-type or semi-insulating semiconductor substrate 1, the openings being arranged in one dimension or two dimensions, and selectively growing a plurality of semiconductor layers 3a, 3b, and 3c including an absorption layer 3b in the openings are included.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: August 20, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai
  • Patent number: 8507962
    Abstract: Pixel sensor cells, e.g., CMOS optical imagers, methods of manufacturing and design structures are provided with isolation structures that prevent carrier drift to diffusion regions. The pixel sensor cell includes a photosensitive region and a gate adjacent to the photosensitive region. The pixel sensor cell further includes a diffusion region adjacent to the gate. The pixel sensor cell further includes an isolation region located below a channel region of the gate and about the photosensitive region, which prevents electrons collected in the photosensitive region to drift to the diffusion region.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Mark D. Jaffe
  • Patent number: 8476102
    Abstract: A method for manufacturing a solid state image pickup device including a first active region provided with a first conversion unit, a second active region provided with a second conversion unit, and a third active region adjoining the first and the second active regions with a field region therebetween and being provided with a pixel transistor, the method including the steps of ion-implanting first conductivity type impurity ions to form a semiconductor region serving as a potential barrier against the signal carriers at a predetermined depth in the third active region and ion-implanting second conductivity type impurity ions into the third active region with energy lower than the above-described ion-implantation energy.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: July 2, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideaki Takada, Toru Koizumi, Yasuo Yamazaki, Tatsuya Ryoki
  • Publication number: 20130153976
    Abstract: Provided is a solid-state imaging apparatus including: a plurality of photoelectric conversion units; an element isolation unit that performs element isolation between the plurality of photoelectric conversion units; and a diffusion prevention unit that prevents diffusion of a dark current component generated on an interfacial surface of the element isolation unit to a region surrounding the dark current component generation region.
    Type: Application
    Filed: November 29, 2012
    Publication date: June 20, 2013
    Applicant: SONY CORPORATION
    Inventor: Sony Corporation
  • Publication number: 20130140666
    Abstract: A method of preparing self-aligned isolation regions between two neighboring sensor elements on a substrate. The method includes patterning an oxide layer to form an opening between the two neighboring sensor elements on the substrate. The method further includes performing a first implant to form a deep doped region between the two neighboring sensor elements and starting at a distance below a top surface of the substrate. The method further includes performing a second implant to form a shallow doped region between the two neighboring sensor elements, wherein a bottom portion of the shallow doped region overlaps with a top portion of the deep doped region.
    Type: Application
    Filed: January 8, 2013
    Publication date: June 6, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi FU, Kai TZENG, Wen-Chen LU
  • Patent number: 8441091
    Abstract: A photodiode assembly includes a semiconductor substrate, a photodiode cell, a ground diffusion region, and a guard band. The photodiode cell includes a first volume of the substrate doped with a first type of dopant. The diffusion region includes a second volume of the substrate that is doped with a second, opposite type of dopant. The guard band is disposed in the substrate and at least partially extends around an outer periphery of the photodiode cell. The guard band includes a third volume of the substrate that is doped with the first type of dopant. At least one of the ground diffusion region or the guard band is conductively coupled with a ground reference to conduct one or more of electrons or holes that drift from the photodiode cell through the substrate. The guard band is disposed closer to the photodiode cell than the ground diffusion region.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: May 14, 2013
    Assignee: General Electric Company
    Inventors: Gregory Scott Zeman, Jeffrey Kautzer, Faisal Saeed
  • Patent number: 8415725
    Abstract: A solid-state imaging device including: a substrate; a light-receiving part; a second-conductivity-type isolation layer; a detection transistor; and a reset transistor.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: April 9, 2013
    Assignee: Sony Corporation
    Inventor: Isao Hirota
  • Patent number: 8389322
    Abstract: A theme is to prevent the generation of noise due to damage in a photodetecting portion in a mounting process in a photodiode array, a method of manufacturing the same, and a radiation detector. In a photodiode array, wherein a plurality of photodiodes (4) are formed in array form on a surface at a side of an n-type silicon substrate (3) onto which light to be detected is made incident and penetrating wirings (8), which pass through from the incidence surface side to the back surface side, are formed for the photodiodes (4), the photodiode array (1) is arranged with a transparent resin film (6), which covers the formed regions of the photodiodes (4) and transmits the light to be detected, provided at the incidence surface side.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: March 5, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Katsumi Shibayama
  • Publication number: 20130049157
    Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor substrate of a first conductive type having a diffusion layer region provided on a surface thereof, a diffusion layer of the first conductive type for a pixel separation whose bottom portion is formed at the deepest position of the diffusion layer region in a pixel region, and a first deep diffusion layer of the first conductive type provided at the deepest position of the diffusion layer region in a first peripheral logic region for electrically connecting the semiconductor substrate and the first peripheral logic region and having a first concentration gradient equal to that of the diffusion layer for pixel separation.
    Type: Application
    Filed: October 24, 2012
    Publication date: February 28, 2013
    Inventor: Hidetoshi KOIKE
  • Patent number: 8384177
    Abstract: A semiconductor device has an active region formed on a semiconductor substrate, a trench-type element isolation region formed on the semiconductor substrate, and a diffusion region in which fluorine is diffused that surrounds the element isolation region and is formed on the semiconductor substrate so as not to contact the active region.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: February 26, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuyuki Endo
  • Patent number: 8368161
    Abstract: A solid-state image capturing device includes, in a semiconductor substrate, a photoelectric conversion section which performs photoelectric conversion on incident light to obtain signal charges; a pixel transistor section which outputs the signal charges generated in the photoelectric conversion section; a peripheral circuit section which is formed in the periphery of a pixel section including the photoelectric conversion section and the pixel transistor section; and isolation areas which electrically separate the photoelectric conversion section, the pixel transistor section, and the peripheral circuit section from each other. The isolation areas in the periphery of the pixel transistor section each have an insulating section formed higher than a surface of the semiconductor substrate. A first gate electrode of a transistor of the pixel transistor section is formed between the insulating sections and on the semiconductor substrate with a gate insulating film interposed therebetween.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: February 5, 2013
    Assignee: Sony Corporation
    Inventors: Fumihiko Koga, Yoshiharu Kudoh
  • Patent number: 8354294
    Abstract: A method, apparatus and material produced thereby in an amorphous or crystalline form having multiple elements with a uniform molecular distribution of elements at the molecular level.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: January 15, 2013
    Inventors: L. Pierre de Rochemont, Alexander J. Kovacs
  • Patent number: 8344244
    Abstract: A solar cell includes a p-type semiconductor substance, and an n-type semiconductor substance. The p-type semiconductor substance and the n-type semiconductor substance form a pn junction or a pin junction, and the p-type semiconductor substance or the n-type semiconductor substance includes a structure film having a plurality of carbon nanotubes electrically connected to each other.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: January 1, 2013
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Kei Shimotani, Chikara Manabe, Takashi Morikawa
  • Patent number: 8338902
    Abstract: An uncooled infrared image sensor according to an embodiments includes: a plurality of pixel cells formed in a first region on a semiconductor substrate; a reference pixel cell formed in a second region on the semiconductor substrate and corresponding to each row or each column of the pixel cells; a supporting unit formed for each of the pixel cell and supporting a corresponding pixel cell; and an interconnect unit formed for each reference pixel cell. Each of the pixel cells includes: a first infrared absorption film and a first heat sensitive element. The reference pixel cell includes: a second infrared absorption film and a second heat sensitive element, the second heat sensitive element having the same characteristics as characteristics of the first heat sensitive element. The third and fourth interconnects of the interconnect unit have the same electrical resistance as electrical resistance of the first and second interconnects of the supporting unit.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Honam Kwon, Hideyuki Funaki, Hiroto Honda, Hitoshi Yagi, Ikuo Fujiwara, Masaki Atsuta, Kazuhiro Suzuki, Keita Sasaki, Koichi Ishii
  • Publication number: 20120306041
    Abstract: In a method of manufacturing a detection device including pixels on a substrate, each pixel including a switch element and a conversion element including an impurity semiconductor layer on an electrode, which is disposed above the switch element and isolated per pixel, the switch element and the electrode being connected in a contact hole formed in a protection layer and an interlayer insulating layer, which are disposed between the switch elements and the electrodes, the method includes forming insulating members over the interlayer insulating layer between the electrodes in contact with the interlayer insulating layer, forming an impurity semiconductor film covering the insulating members and the electrodes, and forming a coating layer covering an area of the protection layer where an orthographically-projected image of a portion of the electrode is positioned, the portion including a level difference within the contact hole.
    Type: Application
    Filed: May 22, 2012
    Publication date: December 6, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kentaro Fujiyoshi, Chiori Mochizuki, Minoru Watanabe, Masato Ofuji, Keigo Yokoyama, Jun Kawanabe, Hiroshi Wayama
  • Publication number: 20120273914
    Abstract: Provided is a method of fabricating an image sensor device. The method includes providing a device substrate having a front side and a back side. The method includes forming first and second radiation-sensing regions in the device substrate, the first and second radiation-sensing regions being separated by an isolation structure. The method also includes forming a transparent layer over the back side of the device substrate. The method further includes forming an opening in the transparent layer, the opening being aligned with the isolation structure. The method also includes filling the opening with an opaque material.
    Type: Application
    Filed: July 10, 2012
    Publication date: November 1, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Patent number: 8274127
    Abstract: A photodiode array includes a substrate of a common read-out control circuit; and a plurality of photodiodes arrayed on the substrate and each including an absorption layer, and a pair of a first conductive-side electrode and a second conductive-side electrode. In this photodiode array, each of the photodiodes is isolated from adjacent photodiodes, the first conductive-side electrodes are provided on first conductivity-type regions and electrically connected in common across all the photodiodes, and the second conductive-side electrodes are provided on second conductivity-type regions and individually electrically connected to read-out electrodes of the read-out control circuit.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Youichi Nagai, Yasuhiro Iguchi
  • Publication number: 20120223405
    Abstract: A solid-state imaging device includes a substrate, a photoelectric conversion section, a first impurity layer having a carrier polarity of a second conductivity type, a charge-to-voltage converting section, an amplifying section, and a second impurity layer having a carrier polarity of the second conductivity type. The second impurity layer is disposed in a region between the photoelectric conversion section and the amplifying section. The second impurity concentration of the second P-type impurity layer is made higher than the first impurity concentration of the first impurity layer.
    Type: Application
    Filed: February 14, 2012
    Publication date: September 6, 2012
    Applicant: Sony Corporation
    Inventors: Kazuki Nomoto, Kaneyoshi Takeshita, Hiroyuki Ohri
  • Patent number: 8253178
    Abstract: An example complementary metal oxide semiconductor (CMOS) image sensor includes an epitaxial layer, an array of pixels, and a trench capacitor. The array of pixels are formed on a front side of the epitaxial layer in an pixel array area of the image sensor. The array of pixels includes one or more shallow trench isolation structures disposed between adjacent pixels for isolating the pixels in the pixel array area. The trench capacitor is formed on the front side of the epitaxial layer in a peripheral circuitry area of the image sensor.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: August 28, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Rongsheng Yang, Zhiqiang Lin
  • Patent number: 8237206
    Abstract: A CMOS image sensor, in which an implantation process is performed on substrate under isolation structures each disposed between two adjacent photosensor cell structures. The implantation process is a destructive implantation to form lattice effects/trap centers. No defect repair process is carried out after the implantation process is performed. The implants can reside at the isolation structures or in the substrate under the isolation structures. Dark leakage and crosstalk are thus suppressed.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: August 7, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Hsin-Ping Wu
  • Publication number: 20120153423
    Abstract: The present invention relates to a silicon photomultiplier with trench isolation for maintaining the photon detection efficiency high while increasing the dynamic range, by reducing the degradation of the effective fill factor that follows the increase of cell number density intended for a dynamic range enhancement.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 21, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Joon Sung LEE
  • Patent number: 8203196
    Abstract: Disclosed is an image sensor. The image sensor includes a substrate having photodiodes therein; a dielectric layer on the substrate; a passivation layer on the dielectric layer exposing the dielectric layer in a region corresponding to a first color filter; and a color filter layer on the exposed dielectric layer and the passivation layer.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: June 19, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Keun Hyuk Lim
  • Publication number: 20120146174
    Abstract: A photodiode assembly includes a semiconductor substrate, a photodiode cell, a ground diffusion region, and a guard band. The photodiode cell includes a first volume of the substrate doped with a first type of dopant. The diffusion region includes a second volume of the substrate that is doped with a second, opposite type of dopant. The guard band is disposed in the substrate and at least partially extends around an outer periphery of the photodiode cell. The guard band includes a third volume of the substrate that is doped with the first type of dopant. At least one of the ground diffusion region or the guard band is conductively coupled with a ground reference to conduct one or more of electrons or holes that drift from the photodiode cell through the substrate. The guard band is disposed closer to the photodiode cell than the ground diffusion region.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 14, 2012
    Applicant: General Electric Company
    Inventors: Gregory Scott Zeman, Jeffrey Kautzer, Faisal Saeed
  • Patent number: 8193479
    Abstract: An image sensor formed in a semiconductor stack of a lower region of a first conductivity type and of an upper region of a second conductivity type, including: a photodiode formed of a first portion of the stack; a read area formed of a second portion of the stack; a trench with insulated walls filled with a conductive material, the trench surrounding the photodiode and the read area and being interrupted, all along its height, on a portion facing the photodiode and the read area; and first connection mechanism associated with the conductive material of the trench and capable of being connected to a reference bias voltage.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: June 5, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: François Roy, Benoît Ramadout
  • Publication number: 20120104533
    Abstract: Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk) so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.
    Type: Application
    Filed: January 12, 2012
    Publication date: May 3, 2012
    Applicant: Sony Corporation
    Inventor: Kiyoshi Hirata
  • Patent number: 8143687
    Abstract: A broadband radiation detector includes a first layer having a first type of electrical conductivity type. A second layer has a second type of electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region. A third layer has the second type of electrical conductivity type and an energy bandgap responsive to radiation in a second spectral region comprising longer wavelengths than the wavelengths of the first spectral region. The broadband radiation detector further includes a plurality of internal regions. Each internal region may be disposed at least partially within the third layer and each internal region may include a refractive index that is different from a refractive index of the third layer. The plurality of internal regions may be arranged according to a regularly repeating pattern.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 27, 2012
    Assignee: Raytheon Company
    Inventors: Justin G. A. Wehner, Scott M. Johnson
  • Patent number: 8129809
    Abstract: Disclosed are an image sensor and a manufacturing method thereof. The image sensor includes a circuit layer on a first surface of a semiconductor substrate, a metal interconnection layer on the circuit layer, trenches formed in a second surface of the semiconductor substrate along a boundary of a pixel, and a light blocking layer in the trenches. The backside illumination type image sensor according to the embodiment has a light blocking structure at a rear surface of the semiconductor substrate, thereby improving sensing efficiency while inhibiting interference between adjacent pixels.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: March 6, 2012
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Hoon Jang
  • Patent number: 8129812
    Abstract: In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a bottom portion and first and second trench sidewalls. At least one trench sidewall is adjacent a doped region. The at least one sidewall adjacent a doped region has a higher impurity dopant concentration than impurity doped regions surrounding the at least one trench isolation region.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: March 6, 2012
    Assignee: Aptina Imaging Corporation
    Inventor: Joohyun Jin
  • Patent number: 8120130
    Abstract: It is an object of the present invention to provide a solid-state imaging device that can achieve a high sensitivity, finer pixels for increasing the number of pixels, a high-speed operation, and high image quality, and a method for manufacturing the same. There are provided a plurality of photoelectric conversion portions arranged in a matrix on a substrate, a vertical transfer channel arranged between vertical columns of the photoelectric conversion portions, a plurality of vertical transfer electrodes for transferring a charge of the photoelectric conversion portions to the vertical transfer channel, a light-shielding film that is laminated on the vertical transfer electrodes via a first insulating film and has a plurality of window portions, each defining a light-receiving portion of each of the photoelectric conversion portions, and a shunt wiring that is arranged in a region overlapping the vertical transfer channel and is insulated from the light-shielding film by a second insulating film.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: February 21, 2012
    Assignee: Panasonic Corporation
    Inventor: Toshihiro Kuriyama
  • Patent number: 8120023
    Abstract: The present invention is directed to novel front side illuminated, back side contact photodiodes and arrays thereof. In one embodiment, the photodiode has a substrate with at least a first and a second side and a plurality of electrical contacts physically confined to the second side. The electrical contacts are in electrical communication with the first side through a doped region of a first type and a doped region of a second type, each of the regions substantially extending from the first side through to the second side. In another embodiment, the photodiode comprises a wafer with at least a first and a second side; and a plurality of electrical contacts physically confined to the second side, where the electrical contacts are in electrical communication with the first side through a diffusion of a p+ region through the wafer and a diffusion of an n+ region through the wafer.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: February 21, 2012
    Assignee: UDT Sensors, Inc.
    Inventors: Peter Steven Bui, Narayan Dass Taneja
  • Patent number: 8115268
    Abstract: Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: February 14, 2012
    Assignee: Sony Corporation
    Inventor: Kiyoshi Hirata
  • Patent number: 8115242
    Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: February 14, 2012
    Assignee: Foveon, Inc.
    Inventor: Richard B. Merrill
  • Patent number: 8110886
    Abstract: A semiconductor circuit in a semiconductor body and a wafer bonding method for connecting the semiconductor circuit to another substrate, in which a diode is realized in a laminar structure. The semiconductor circuit is connected to the terminals of the diode by means of feedthroughs that extend through the semiconductor body.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: February 7, 2012
    Assignee: austriamicrosystems AG
    Inventors: Gerald Meinhardt, Franz Schrank, Verena Vescoli