Abstract: An imaging device comprises pixels. The pixel includes first semiconductor regions of a first conductivity type provided in a surface part of a semiconductor substrate and a second semiconductor region of a second conductivity type provided in the surface part of the semiconductor substrate between the first semiconductor regions. The pixel includes: a light-receiving unit in which photodiodes each configured between the second semiconductor region and one of the first semiconductor regions; quenching circuits, each connected to a corresponding one of the first semiconductor regions; and a counter unit connected to each of connection nodes between the first semiconductor regions and the quenching circuits and counts a pulse generated in response to a photon being incident on the light-receiving unit. The second semiconductor region is provided across a deeper part of the semiconductor substrate than the first semiconductor regions.

Abstract: Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.

Abstract: A photosensitive device, a manufacturing method thereof, a detection substrate and an array substrate are provided. The photosensitive device is formed on a substrate, and it includes a photosensitive element and a thin film transistor. The photosensitive element includes a first electrode layer on the substrate; a second electrode layer on a side of the first electrode layer distal to the substrate; and a photoelectric conversion layer between the first electrode layer and the second electrode layer. The thin film transistor is electrically connected to the photosensitive element, and it includes a first gate electrode on the substrate; an active layer on a side of the first gate electrode distal to the substrate; and a second gate electrode on a side of the active layer distal to the substrate. The first electrode layer and the second gate electrode are located in the same layer.

Abstract: A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

Abstract: An integrated circuit system, structure and/or component is provided that includes an integrated electrical power source in a form of a unique, environmentally-friendly energy harvesting element or component. The energy harvesting component provides a mechanism for generating autonomous renewable energy, or a renewable energy supplement, in the integrated circuit system, structure and/or component. The energy harvesting element includes a first conductor layer, a low work function layer, a dielectric layer, and a second conductor layer that are particularly configured to promote electron migration from the low work function layer, through the dielectric layer, to the facing surface of the second conductor layer in a manner that develops an electric potential between the first conductor layer and the second conductor layer. An energy harvesting component includes a plurality of energy harvesting elements electrically connected to one another to increase a power output of the electric harvesting component.

Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.

Abstract: A planar Hall effect element be formed upon or can include a P-type substrate. The planar Hall effect element can also include a Hall plate region. The Hall plate region can include a first portion of an N-type layer disposed over the P-type substrate. The first portion of the N-type layer can include a top surface distal from the P-type substrate, and a continuous N-type outer boundary intersecting the top surface of the Hall plate region. The planar Hail effect element can also include an isolation region having a continuous outer boundary and having a continuous inner boundary, the continuous inner boundary in contact with all of the outer boundary of the Hall plate region, the P-type substrate and the first portion of the N-type layer not forming a P/N junction.

Abstract: This disclosure describes an electric-field imaging system and method of use. In accordance with implementations of the electric-field imaging system, a fluid sample can be placed on top of a pixel-based impedance sensor. An image of the target analytes can be created immediately afterwards. From this image, computer imaging algorithms can determine attributes (e.g., size, type, morphology, volume, distribution, number, concentration, or motility, etc.) of the target analytes.

Abstract: A chemically-sensitive field effect transistor is disclosed herein. The chemically-sensitive field effect transistor comprises a CMOS structure comprising a conductive source and a conductive drain, a channel and an analyte-sensitive dielectric layer. The channel extends from the conductive source to the conductive drain. The channel is composed of a one-dimensional transistor material or a two-dimensional transistor material. The analyte-sensitive dielectric layer is disposed over the channel. An I-V curve or an I-Vg curve is shifted in response to a chemical reaction occurring on or near the chemically-sensitive field effect transistor.

Abstract: A photoelectric conversion device includes a photoelectric conversion unit which includes a phototransistor having a collector region, an emitter region, and a base region to generate an output current according to an intensity of incident light to the phototransistor, and a base potential setting unit which is configured to set up a base potential of the phototransistor so that the output current from the photoelectric conversion unit is equal to a predetermined current value.

Abstract: According to embodiments of the present disclosure, a dynamic photodiode may include a substrate, a first doped region, a second doped region, a first resettable doped region between the first doped region and the second doped region, and a first light absorbing region between the first doped region and the second doped region. The first doped region may include a first contact that receives a first voltage. The second doped region may include a second contact that receives a second voltage. The first resettable doped region may include a first resettable contact that receives a reset voltage or is set as an open circuit. The first light absorbing region may generate first electron-hole pairs in the substrate when the first resettable contact is set as an open circuit, and the first electron-hole pairs may be removed from the substrate when the first resettable contact receives the reset voltage.

Abstract: According to embodiments of the present invention, an optical device is provided. The optical device includes a waveguide structure including a floating gate, and an optical waveguide arranged spaced apart from the floating gate, wherein the optical waveguide overlaps with the floating gate, a carrier injection portion arranged spaced apart from the floating gate, and an electrode arrangement, wherein, in response to a first voltage difference applied to the electrode arrangement, the optical device is configured to inject charge carriers from the carrier injection portion to the floating gate to cause a change in refractive index of the waveguide structure, and wherein, in response to a second voltage difference applied to the electrode arrangement, the optical device is configured to drive the charge carriers from the floating gate to the optical waveguide to deplete the charge carriers.

Abstract: A method for analyzing concentration of a cardiovascular disease (CVD) biomarker in a liquid sample includes: applying the liquid sample to a biosensor, the biosensor including a transistor having a drain, a source, and a gate terminal disposed between the gate and the source, and a reactive electrode spaced apart from the gate terminal of the transistor and having a receptor immobilized thereon for specific binding with the CVD biomarker, the liquid sample being in contact with the gate terminal and the reactive electrode; applying a voltage pulse between the reactive electrode and the source, the voltage pulse having a pulse width; monitoring a response current in response to the voltage pulse; and analyzing the response current.

Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.

Abstract: A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit. The solid-state image pickup apparatus further includes a light shielding member including a first part and a second part, wherein the first part is disposed over the charge storage unit and at least over the first gate electrode or the second gate electrode, and the second part is disposed between the first gate electrode and the second gate electrode such that the second part extends from the first part toward a surface of the semiconductor substrate.

Abstract: An image sensor includes a photodiode disposed in a first semiconductor material and a floating diffusion disposed proximate to the photodiode in the first semiconductor material. A source follower transistor is disposed in part in a second semiconductor material and includes: a first doped region, a third doped region, and a second doped region with an opposite polarity as the first doped region and the third doped region, and a gate electrode coupled to the floating diffusion and disposed in the first semiconductor material and aligned with the second doped region in the second semiconductor material of the source follower transistor.

Abstract: The present disclosure provides an image sensor. An image sensor may include: a transfer gate formed over a first substrate, and having a through-hole; a column-shaped epitaxial body having a first portion filled in the through-hole and a second portion formed over the transfer gate; a photoelectric conversion element formed in the second portion of the epitaxial body; and a floating diffusion region formed in the first substrate, and contacting the first portion of the epitaxial body.

Abstract: Device structures and fabrication methods for a device structure. One or more trench isolation regions are formed in a substrate to surround a device region. A base layer is formed on the device region. First and second emitter fingers are formed on the base layer. A portion of the device region extending from the first emitter finger to the second emitter finger is free of dielectric material.

Abstract: A field effect transistor photodetector that can operate in room temperature includes a source electrode, a drain electrode, a channel to allow an electric current to flow between the drain and source electrodes, and a gate electrode to receive a bias voltage for controlling the current in the channel. The photodetector includes a light-absorbing material that absorbs light and traps electric charges. The light-absorbing material is configured to generate one or more charges upon absorbing light having a wavelength within a specified range and to hold the one or more charges. The one or more charges held in the light-absorbing material reduces the current flowing through the channel.

Abstract: An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.

Abstract: A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section.

Abstract: A monolithic photo detector device disposed on a bulk substrate, comprising a photo detector disposed integrated in the bulk substrate including: (1) a p-type doped impurity region extending along a first direction in the major surface of the substrate and receiving a first voltage, (2) first and second gates being spaced apart from each other and extending in the first direction over the major surface of the substrate, wherein the gates receives a second voltage, (3) an n-type doped impurity region, extending along the first direction in the major surface of the substrate and receiving a third voltage; and (4) a light absorbing region, disposed between the second doped impurity region and the first gate. The device also includes control circuitry, integrated in the substrate to generate the first, second and third voltages that control an operating state of the detector.

Abstract: An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.

Abstract: A phototransistor includes a first emitter region, a first base region having at least a portion exposed to a light-receiving side, and a first collector region in this order from the light-receiving side in a depth direction. The first collector region includes a second collector region and a third collector region that is in contact with a downstream side of the second collector region in the depth direction and has a resistance lower than that of the second collector region. The phototransistor further includes a first region that is spaced away from the first base region at an outer side of the first base region on a light-receiving side surface thereof, the first region having a conductivity type opposite to that of the first collector region.

Abstract: The present disclosure relates to a solid-state imaging device, a driving method for the same, and an electronic appliance, and an object is to provide a solid-state imaging device that can achieve the pixel miniaturization and the global shutter function with higher sensitivity and saturated charge amount. Another object is to provide an electronic appliance including the solid-state imaging device. In a solid-state imaging device 1 having the global shutter function, a first charge accumulation unit 18 and a second charge accumulation unit 25 are stacked in the depth direction of a substrate 12, and the transfer of the signal charges from the first charge accumulation unit 12 to the second charge accumulation unit 25 is conducted by a vertical first transfer transistor Tr1. Thus, the pixel miniaturization can be achieved.

Abstract: A method of generating a pixel array layout for an image sensor (wherein the image sensor includes a plurality of unit pixels, and each of the plurality of unit pixels includes a plurality of transistors) includes forming each unit pixel to include a shallow trench isolation (STI). The STI is between a deep trench isolation (DTI) area and one of a p-well region and source and drain regions of each transistor. The p-well region is below a gate of each of the transistors, and the DTI area is filled with at least two materials.

Abstract: A simple SCM (Self Cascode MOSFET) structure to generate a sub-1V reference voltage in the SCM intermediate node. The structure requires only 2 transistors to create a temperature-compensated reference voltage. When sized correctly, the transistors in the SCM will operate both at weak, moderate or strong inversion, and in the saturation region or saturation and triode regions, providing good correspondence and low part to part variation. The following proposal innovates by operating with supply voltages on a broad variation range, from 3.6V through below 1V (sub-1V operation), with bias currents in the range of tens of nA (nano Amperes) and temperature variation smaller than ±1% from ?40° C. through 85° C. This is an extremely low cost implementation (in terms of area and complexity), compatible with standard CMOS manufacturing processes, and very robust (in terms of fab-to-fab transference, technology mapping, and also well controlled part-to-part variation).

Abstract: A field effect transistor photodetector that can operate in room temperature includes a source electrode, a drain electrode, a channel to allow an electric current to flow between the drain and source electrodes, and a gate electrode to receive a bias voltage for controlling the current in the channel. The photodetector includes a light-absorbing material that absorbs light and traps electric charges. The light-absorbing material is configured to generate one or more charges upon absorbing light having a wavelength within a specified range and to hold the one or more charges. The one or more charges held in the light-absorbing material reduces the current flowing through the channel.

Abstract: A solid-state imaging device according to an embodiment includes photoelectric conversion devices, a dopant layer, a low concentration region, and a transistor. The photoelectric conversion devices are disposed on a semiconductor layer. The dopant layer is disposed on a layer same as the semiconductor layer where photoelectric conversion devices are arrayed, and includes dopant having a conductivity type reverse to a charge accumulating region of the photoelectric conversion device. The low concentration region is disposed inside the dopant layer and has dopant concentration lower than the dopant layer. A transistor includes an active region disposed on the dopant layer.

Abstract: A solid-state imaging device includes a semiconductor region of p-type; a buried region of n-type, configured to serve as a photodiode together with the semiconductor region; a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region, having higher impurity concentration than the buried region; a read-out region of n-type, configured to accumulate charges, which are transferred from the buried region having higher impurity concentration than the buried region; and a potential gradient changing mechanism, configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region to the read-out region and a potential gradient of a potential profile from the buried region to the extraction region, so as to control the transferring/extraction of charges.

Abstract: A solid-state photodetector with variable spectral response that can produce a narrow or wide response spectrum of incident light. Some embodiments include a solid-state device structure that includes a first photodiode and a second photodiode that share a common anode region. Bias voltages applied to the first photodiode and/or the second photodiode may be used to control the thicknesses of depletion regions of the photodiodes and/or a common anode region to vary the spectral response of the photodetector. Thickness of the depletion regions and/or the common anode region may be controlled based on resistance between multiple contacts of the common anode region and/or capacitance of the depletion regions. Embodiments include control circuits and methods for determining spectral characteristics of incident light using the variable spectral response photodetector.

Abstract: According to one embodiment, an optical device includes a plurality of optical elements arrange in array. At least of the optical elements includes an optical layer constituted by a plurality of patterns. The plurality of patterns are formed by a layered body including metal layers and a dielectric layer interlayered between the metal layers, and formed as a plurality of regularly-arranged loop-like patterns with a density decreasing from the center toward the periphery of the loop.

Abstract: This invention has for purpose to provide a photosensor that is small in size and can obtain high-contrast image data and to provide a semiconductor device including the photosensor. In the photosensor including a light-receiving element, a transistor serving as a switching element, and a charge retention node electrically connected to the light-receiving element through the transistor, the reduction in charge held in the charge retention node is suppressed by extending the fall time of the input waveform of a driving pulse supplied to the transistor to turn off the transistor.

Abstract: This invention relates to field photodiodes based on PN junctions that suffer from dark current leakage. An NBL is added to prove a second PN junction with the anode. The second PN junction is reversed biased in order to remove dark current leakage. The present solution requires no additional masks or thin films steps relative to a conventional CMOS process flow.

Abstract: An image sensor includes first impurity regions formed in a substrate, second impurity regions formed in the first impurity regions, wherein the second impurity regions has a junction with the first impurity regions, recess patterns formed over the first impurity regions in contact with the second impurity regions, and transfer gates filling the recess patterns.

Abstract: A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

Abstract: A method for fabricating thin film solar cells for a concentrated photovoltaic system uses three shadow masks. The first mask, used to deposit a back contact layer, has multiple horizontal and vertical lines defining columns and rows of cells, and multiple tabs each located in a cell along a center of a vertical border. The second mask, used to deposit a CIGS absorption layer, a window layer and a transparent contact layer, is similar to the first mask except the tabs are located along the opposite vertical border of the cells. The third mask, used to deposit a metal grid layer, has multiple bus bar openings and finger openings. Each bus bar opening is located along a horizontal center line of a cell and overlaps the second tab of a neighboring cell. The cells in a horizontal row are connected in series, forming a linear solar receiver.

Abstract: A low noise infrared photo detector with a vertically integrated field effect transistor (FET) structure is formed without thermal diffusion. The FET structure includes a high sensitivity photo detector layer, a charge well layer, a transfer well layer, a charge transfer gate, and a drain electrode. In an embodiment, the photo detector layer and charge well are InGaAs and the other layers are InP layers.

Abstract: A semiconductor structure for photon detection, comprising a substrate composed of a semiconductor material having a first doping, a contact region fitted at the frontside of the substrate, a bias layer composed of a semiconductor material having a second doping, which is arranged on the backside of the substrate at a distance from the contact region, wherein the contact region at least partly lies opposite the bias layer, such that an overlap region is present in a lateral direction, a guard ring, which is arranged at the frontside of the substrate and surrounds the contact region, wherein a reverse voltage can be applied between the contact region and the guard ring. In order to enable more cost-effective production, the overlap region has a lateral extent amounting to at least one quarter of the distance between contact region and bias layer.

Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.

Abstract: An integrated circuit-solar cell device comprising a well region of a first dopant type, a solar cell including: (i) a first region disposed in or on the well region, wherein the first region is of the first dopant type, and (ii) a second region disposed outside the well region, wherein the second region is of a second dopant type. The device further includes an integrated circuit including: (i) a first transistor of a first type disposed in or on the well region, and (ii) a second transistor of a second type disposed in or on the first major surface of the substrate and outside the well region. Power management circuitry selectively and electrically couples the solar cell to the battery when the integrated circuit is in an inactive mode.

Abstract: An image sensor device is provided, including at least one transistor lying on a semiconductor-on-insulator substrate that includes a semi-conducting layer, in which a channel area of the transistor is disposed in a portion thereof, and an insulating layer separating the semi-conducting layer from a semi-conducting support layer, wherein the semi-conducting layer and the insulating layer extend beyond the channel area, and extend under at least a portion of source/drain regions of the transistor, wherein the semi-conducting support layer includes at least one photosensitive area including at least one P-doped region and at least one N-doped region forming a junction, the photosensitive area being disposed facing the transistor on a side of the channel area thereof and opposite a side of a gate electrode thereof, and wherein the insulating layer is configured to provide a capacitive coupling between the photosensitive area and the semi-conducting layer.

Abstract: The present invention provides a solid-state imaging element including: a silicon layer having a photodiode formed therein and a positive charge accumulation region formed on the surface thereof; and an optical waveguide formed above the photodiode to guide incident light into the photodiode, wherein an insulating layer is formed in the optical waveguide, and the insulating layer has a dielectric constant of 5 or greater and negative fixed charge.

Abstract: Embodiments relate to photo cell devices. In an embodiment, a photo cell device includes an array of transmission layers having different optical thicknesses and with photo diodes underneath. The transmission layers can include two different materials, such as a nitride and an oxide, that cover each diode with a different proportional area density in a damascene-like manner. Embodiments provide advantages over conventional devices, including that they can be integrated into a standard CMOS process and therefore simpler and less expensive to produce.

Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.

Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.

Abstract: A photoelectric conversion device includes a film that covers the photoelectric conversion part and a transfer gate electrode, wherein a first region having a refractive index lower than refractive indices of the film and the photoelectric conversion part, is provided between the film and the photoelectric conversion part, and a second region having a refractive index lower than the refractive indices of the transfer gate electrode and the film, is provided between the film and the top surface of the transfer gate electrode, and wherein T1<T2<?/2?T1 is satisfied, where an optical thickness of the first region is T1, an optical thickness of the second region is T2, and a wavelength of a light incident on the photoelectric conversion part is ?.

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract: An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.

Abstract: An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.