Including High Voltage Or High Power Devices Isolated From Low Voltage Or Low Power Devices In The Same Integrated Circuit Patents (Class 257/500)
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Patent number: 8030730Abstract: An N-layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N-layer, a trench isolation region is formed to surround the N-layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N-layer. Between trench isolation region and the N-layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N-layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.Type: GrantFiled: March 11, 2009Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Tetsuya Nitta, Takayuki Igarashi
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Patent number: 8030706Abstract: A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part.Type: GrantFiled: August 12, 2009Date of Patent: October 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Miho Watanabe, Masaru Izumisawa, Yasuto Sumi, Hiroshi Ohta, Wataru Sekine, Wataru Saito, Syotaro Ono, Nana Hatano
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Patent number: 8026570Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: GrantFiled: September 24, 2009Date of Patent: September 27, 2011Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
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Patent number: 8022476Abstract: A semiconductor device having both vertical and horizontal type gates and a method for fabricating the same for obtaining high integration of the semiconductor device and integration with other devices while also maximizing the breakdown voltage and operational speed and preventing damage to the semiconductor device.Type: GrantFiled: October 17, 2008Date of Patent: September 20, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Sung-Man Pang
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Patent number: 8013416Abstract: This semiconductor device includes a first device and a second device provided on a semiconductor substrate and having different breakdown voltages. More specifically, the semiconductor device includes a semiconductor substrate, a first region defined on the semiconductor substrate and having a first device formation region isolated by a device isolation portion formed by filling an insulator in a trench formed in the semiconductor substrate, a first device provided in the first device formation region, a second region defined on the semiconductor substrate separately from the first region and having a second device formation region, and a second device provided in the second device formation region and having a higher breakdown voltage than the first device, the second device having a drift drain structure in which a LOCOS oxide film thicker than a gate insulation film thereof is disposed at an edge of a gate electrode thereof.Type: GrantFiled: August 3, 2005Date of Patent: September 6, 2011Assignee: Rohm Co., Ltd.Inventor: Takamitsu Yamanaka
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Patent number: 8008146Abstract: A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method performs an oxidation process simultaneously on the wires to form a first gate oxide on the first wire and a second gate oxide on the second wire. The first gate oxide is thicker than the second gate oxide. The method also forms gate conductors over the first gate oxide and the second gate oxide, forms sidewall spacers on the gate conductors, and dopes portions of the first wire and the second wire not covered by the sidewall spacers and the gate conductors to form source and drain regions within the first wire and the second wire.Type: GrantFiled: December 4, 2009Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Andres Bryant, Guy Cohen, Jeffrey W. Sleight
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Publication number: 20110198704Abstract: A power switch with active snubber. In accordance with a first embodiment, an electronic circuit includes a first power semiconductor device and a second power semiconductor device coupled to the first power semiconductor device. The second power semiconductor device is configured to oppose ringing of the first power semiconductor device.Type: ApplicationFiled: July 1, 2010Publication date: August 18, 2011Applicant: VISHAY SILICONIXInventor: Kyle Terrill
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Patent number: 7994580Abstract: A semiconductor device and its method of manufacture are provided. Embodiments include forming a first doped region and a second doped region. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor. A gate-side boundary of the first doped region underlies part of the gate electrode. The second doped region is formed within the first doped region adjacent the gate electrode. A gate-side boundary of the second doped region is separated from a closest edge of a gate electrode spacer by a first distance. An isolation region-side boundary of the second doped region is separated from a closest edge of a nearest isolation region by a second distance.Type: GrantFiled: October 19, 2005Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: William Wei-Yuan Tien, Fu-Hsin Chen, Jui-Wen Lin, You-Kuo Wu
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Patent number: 7994603Abstract: Disclosed herein is a semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.Type: GrantFiled: July 7, 2008Date of Patent: August 9, 2011Assignee: Sony CorporationInventors: Junli Wang, Tomoyuki Hirano, Toyotaka Kataoka, Yoshiya Hagimoto
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Patent number: 7989896Abstract: A method of fabricating a semiconductor device according to one embodiment includes: laying out a first region, a second region, a third region and a fourth region on a semiconductor substrate by forming an element isolation region in the semiconductor substrate; forming a first insulating film on the first region and the second region; forming a first semiconductor film on the first insulating film; forming a second insulating film and an aluminum oxide film thereon on the fourth region after forming of the first semiconductor film; forming a third insulating film and a lanthanum oxide film thereon on the third region after forming of the first semiconductor film; forming a high dielectric constant film on the aluminum oxide film and the lanthanum oxide film; forming a metal film on the high dielectric constant film; forming a second semiconductor film on the first semiconductor film and the metal film; and patterning the first insulating film, the first semiconductor film, the second insulating film, the alType: GrantFiled: November 4, 2009Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tomonori Aoyama, Seiji Inumiya, Kazuaki Nakajima, Takashi Shimizu
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Publication number: 20110163391Abstract: This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.Type: ApplicationFiled: January 6, 2010Publication date: July 7, 2011Applicant: Fairchild Semiconductor CorporationInventors: Dan Kinzer, Yong Liu, Stephen Martin
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Patent number: 7972929Abstract: A method for manufacturing a semiconductor device includes forming an ONO layer in a memory region and forming several gate oxide layer patterns in a logic region, a nitride layer in the logic region can be used as a hard mask, enabling a reduction in the number of masks used. This results in improved manufacturing efficiency and reduced manufacturing costs of a SONOS semiconductor device.Type: GrantFiled: October 16, 2008Date of Patent: July 5, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: In-Kun Lee
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Patent number: 7968936Abstract: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process.Type: GrantFiled: December 31, 2007Date of Patent: June 28, 2011Assignee: Texas Instruments IncorporatedInventors: Marie Denison, Pinghai Hao
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Patent number: 7964933Abstract: A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.Type: GrantFiled: June 22, 2007Date of Patent: June 21, 2011Assignee: Diodes Inc.Inventors: Paul Chang, Geeng-Chuan Chern, Prognyan Ghosh, Wayne Y. W. Hsueh, Vladimir Rodov
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Publication number: 20110140227Abstract: A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines.Type: ApplicationFiled: December 14, 2009Publication date: June 16, 2011Inventors: Michael A. Smith, Vladimir Mikhalev, Kenneth Marr, Haitao Liu
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Patent number: 7960810Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.Type: GrantFiled: September 5, 2006Date of Patent: June 14, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chyi-Chyuan Huang, Shyh-An Lin, Chen-Fu Hsu
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Patent number: 7944016Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.Type: GrantFiled: August 29, 2007Date of Patent: May 17, 2011Assignee: Broadcom CorporationInventor: Wenkwei Lou
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Patent number: 7939907Abstract: High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an EBG (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the EBG layer from each other is disposed between the power layer for analog operation and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.Type: GrantFiled: May 30, 2007Date of Patent: May 10, 2011Assignee: Renesas Electronics CorporationInventors: Hideki Osaka, Yutaka Uematsu, Eiichi Suzuki
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Patent number: 7923805Abstract: Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.Type: GrantFiled: September 19, 2006Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: ChanSam Chang, Shigenobu Maeda, HeonJong Shin, ChangBong Oh
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Patent number: 7919813Abstract: Disclosed is a semiconductor device of n-type MOSFET structure, which comprises a semiconductor substrate having a device isolation region, diffusion regions formed in the semiconductor substrate, gate electrodes formed above the semiconductor substrate, and a F-containing NiSi layer formed on the diffusion regions and containing F atoms at a concentration of 3.0×1013 cm?2 or more in areal density, wherein a depth from the junction position formed between the diffusion region and the semiconductor substrate to the bottom of the F-containing NiSi layer is confined within the range of 20 to 100 nm, and the concentration of F atoms at an interface between the F-containing NiSi layer and the semiconductor substrate is 8.0×1018 cm?3 or more.Type: GrantFiled: October 23, 2009Date of Patent: April 5, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Masakatsu Tsuchiaki
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Patent number: 7910444Abstract: A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.Type: GrantFiled: October 27, 2009Date of Patent: March 22, 2011Assignee: STMicroelectronics S.r.l.Inventors: Giorgio Servalli, Giulio Albini, Carlo Cremonesi
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Patent number: 7906829Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface; a first insulation separation region disposed on the first surface of the semiconductor substrate; a second insulation separation region surrounded with the first insulation separation region and electrically isolated from the first insulation separation region; a semiconductor element disposed in the second insulation separation region; and an electrode connecting to the first insulation separation region for energizing and generating heat in the first insulation separation region. The first insulation separation region functions as a heater so that the semiconductor element in the second insulation separation region is locally heated.Type: GrantFiled: June 6, 2006Date of Patent: March 15, 2011Assignee: Denso CorporationInventor: Akira Tai
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Patent number: 7906828Abstract: A high-voltage integrated circuit includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region.Type: GrantFiled: March 4, 2009Date of Patent: March 15, 2011Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Sung-lyong Kim, Chang-ki Jeon
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Publication number: 20110057287Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.Type: ApplicationFiled: November 15, 2010Publication date: March 10, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Noriyuki MITSUHIRA, Takehiko NAKAHARA, Yasusuke SUZUKI, Jun SUMINO
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Publication number: 20110042726Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.Type: ApplicationFiled: August 20, 2009Publication date: February 24, 2011Applicant: Power Integrations, Inc.Inventors: Sujit Banerjee, Vijay Parthasarathy
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Patent number: 7893517Abstract: A semiconductor memory device includes a well layer having a first conductivity type and formed in a semiconductor substrate, a block layer formed in a trench and formed of an insulating layer, a gate electrode formed on the semiconductor substrate apart from the block layer, a first diffusion layer having a second conductivity type, formed on a surface of the semiconductor substrate, and having a high impurity concentration region to a first depth from the surface of the semiconductor substrate, a second diffusion layer having the second conductivity type, formed on the surface of the semiconductor substrate on a side of the block layer away from the gate electrode, having a high impurity concentration region to a second depth greater than the first depth from the surface of the semiconductor substrate, and electrically connected to the first diffusion layer, and a contact connected to the second diffusion layer.Type: GrantFiled: November 29, 2007Date of Patent: February 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Haruhiko Koyama
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Patent number: 7888768Abstract: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device.Type: GrantFiled: January 9, 2006Date of Patent: February 15, 2011Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Sung-lyong Kim, Chang-ki Jeon, Jong-jib Kim, Jong-tae Hwang
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Patent number: 7888703Abstract: An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.Type: GrantFiled: February 8, 2008Date of Patent: February 15, 2011Assignee: Infineon Technologies AGInventors: Sven Albers, Klaus Diefenbeck, Bernd Eisener, Gernot Langguth, Christian Lehrer, Karl-Heinz Malek, Eberhard Rohrer
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Publication number: 20110018068Abstract: An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, connected to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.Type: ApplicationFiled: July 20, 2010Publication date: January 27, 2011Applicant: STMICROELECTRONICS S.R.LInventors: Riccardo DEPETRO, Stefano MANZINI
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Patent number: 7875953Abstract: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.Type: GrantFiled: July 7, 2008Date of Patent: January 25, 2011Assignee: The Regents of the University of CaliforniaInventor: Ya-Hong Xie
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Patent number: 7867884Abstract: A wafer fabrication method includes a first step of forming a plurality of first channel regions in a first region on a surface of a water, a second step of forming a plurality of second channel regions having an impurity concentration different from an impurity concentration of the first channel regions, a third step of forming a plurality of third channel regions in a third region on the surface of the water, and a fourth step of forming a plurality of fourth channel regions having an impurity concentration different from an impurity concentration of the third channel regions in a fourth region, wherein the first region and the second region are divided by a first line segment on the wafer, and the third and fourth regions are divided by a second line segment intersecting with the first line segment on the wafer.Type: GrantFiled: April 15, 2008Date of Patent: January 11, 2011Assignee: Renesas Electronics CorporationInventors: Tomohiro Kamimura, Kou Sasaki, Tomoharu Inoue
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Publication number: 20100327342Abstract: In various embodiments, the invention relates to semiconductor structures, such as planar MOS structures, suitable as voltage clamp devices. Additional doped regions formed in the structures may improve over-voltage protection characteristics.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Inventors: Javier Salcedo, Alan Righter
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Patent number: 7859078Abstract: A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.Type: GrantFiled: March 30, 2009Date of Patent: December 28, 2010Assignee: Sharp Kabushiki KaishaInventor: Kazushige Hotta
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Patent number: 7855579Abstract: In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.Type: GrantFiled: November 9, 2006Date of Patent: December 21, 2010Assignee: Panasonic CorporationInventors: Kouji Fujiyama, Takahiro Nagatani, Atsushi Takahashi
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Publication number: 20100314709Abstract: A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level.Type: ApplicationFiled: June 10, 2010Publication date: December 16, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Da-Wei LAI, Jen-Chou TSENG, Chien-Yuan LEE
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Patent number: 7847365Abstract: A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.Type: GrantFiled: October 14, 2005Date of Patent: December 7, 2010Assignee: System General Corp.Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu Lin, Ta-yung Yang
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Patent number: 7838960Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.Type: GrantFiled: August 30, 2006Date of Patent: November 23, 2010Assignee: Seiko Epson CorporationInventors: Masaaki Abe, Hidehiko Yajima, Takemi Yonezawa, Fumikazu Komatsu, Mitsuaki Sawada
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Patent number: 7834575Abstract: An automotive drive system for a high voltage electric motor comprises a microcontroller and ECU powered by a low voltage (12 volt) bus net which controls the drives of a high voltage inverter powered by a 100 volt or higher source, which, in turn, drives the motor. To provide good electrical insulation between the low voltage and high voltage systems, the low voltage control signals are produced by a low voltage signal input chip which has a bottom electrode which produces a control potential responsive to the ECU output and a high voltage driver IC which drives the power devices of the high voltage inverter. The high voltage driver IC has a top electrode which drives the high voltage IC function. The bottom electrode of the LV input chip is coupled to the top electrode of the high voltage driver IC through an insulation layer, defining a capacitive coupler which defines an isolation barrier between the low voltage net and the high voltage system insulation.Type: GrantFiled: April 1, 2008Date of Patent: November 16, 2010Assignee: International Rectifier CorporationInventor: Henning M Hauenstein
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Patent number: 7834407Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.Type: GrantFiled: May 26, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Yoshito Nakazawa, Yuji Yatsuda
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Publication number: 20100283116Abstract: A semiconductor device includes a low-side circuit, high-side circuit, a virtual ground potential pad, a common ground potential pad and a diode, formed on a semiconductor substrate. The low-side circuit drives a low-side power transistor. The high-side circuit is provided at a high potential region, and drives a high-side power transistor. The virtual ground potential pad is arranged at the high potential region, and coupled to a connection node of both power transistors to supply a virtual ground potential to the high-side circuit. The common ground potential pad supplies a common ground potential to the low-side circuit and high-side circuit. The diode has its cathode connected to the virtual ground potential pad and its anode connected to the common ground potential pad.Type: ApplicationFiled: December 24, 2009Publication date: November 11, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Kazuhiro SHIMIZU
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Patent number: 7825488Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.Type: GrantFiled: May 31, 2006Date of Patent: November 2, 2010Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Patent number: 7824977Abstract: A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.Type: GrantFiled: March 27, 2007Date of Patent: November 2, 2010Assignee: Alpha & Omega Semiconductor, Ltd.Inventors: YongZhong Hu, Sung-Shan Tai
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Patent number: 7821077Abstract: The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.Type: GrantFiled: June 29, 2005Date of Patent: October 26, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Naoyoshi Tamura
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Patent number: 7816762Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.Type: GrantFiled: August 7, 2007Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Eric Thompson
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Patent number: 7816264Abstract: A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily.Type: GrantFiled: July 7, 2008Date of Patent: October 19, 2010Assignee: Disco CorporationInventors: Keiichi Kajiyama, Kazuhisa Arai
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Patent number: 7816757Abstract: High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an EBG (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the EBG layer from each other is disposed between the power layer for analog operation and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.Type: GrantFiled: May 30, 2007Date of Patent: October 19, 2010Assignee: Renesas Technology Corp.Inventors: Hideki Osaka, Yutaka Uematsu, Eiichi Suzuki
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Publication number: 20100253317Abstract: To include a first X decoder constituted by a transistor whose off-leakage current has a first temperature characteristic, a pre-decoder circuit and a peripheral circuit constituted by a transistor whose off-leakage current has a second temperature characteristic, a power supply control circuit that inactivates the X decoder when a temperature exceeds a first threshold during a standby state, and a power supply control circuit that inactivates the pre-decoder and the peripheral circuit when a temperature exceeds a second threshold during the standby state. According to the present invention, whether power supply control is performed on a plurality of circuit blocks is determined based on different temperatures, therefore optimum power supply control can be performed on each of circuit blocks.Type: ApplicationFiled: April 2, 2010Publication date: October 7, 2010Applicant: Elpida Memory, Inc.Inventors: Shinya OKUNO, Kiyohiro FURUTANI
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Patent number: 7808071Abstract: One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.Type: GrantFiled: July 2, 2008Date of Patent: October 5, 2010Assignee: Texas Instruments IncorporatedInventors: Binghua Hu, Mindricelu P. Eugen, Damien T. Gilmore, Bill A. Wofford
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Patent number: 7808070Abstract: A power semiconductor component is disclosed. One embodiment provides a semiconductor body, in which at least two vertical power semiconductor components are arranged. Each of the vertical power semiconductor components has a first load terminal arranged at a front side of the semiconductor body. Each of the vertical power semiconductor components has a second load terminal arranged at a rear side of the semiconductor body opposite the front side.Type: GrantFiled: August 15, 2007Date of Patent: October 5, 2010Assignee: Infineon Technologies AGInventor: Peter Kanschat
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Publication number: 20100244756Abstract: A high voltage integrated circuit contains a freewheeling diode embedded in a transistor. It further includes a control block controlling a high voltage transistor and a power block—including the high voltage transistor—isolated from the control block by a device isolation region. The high voltage transistor includes a semiconductor substrate of a first conductivity type, a epitaxial layer of a second conductivity type on the semiconductor substrate, a buried layer of the second conductivity type between the semiconductor substrate and the epitaxial layer, a collector region of the second conductivity type on the buried layer, a base region of the first conductivity type on the epitaxial layer, and an emitter region of the second conductivity type formed in the base region. The power block further includes a deep impurity region of the first conductivity type near the collector region to form a PN junction.Type: ApplicationFiled: June 7, 2010Publication date: September 30, 2010Inventors: Taeg-hyun Kang, Sung-son Yun