Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction.

Abstract: An organic electroluminescence device includes a first electrode, a second electrode located on a light extraction side and having a metal film, and an organic compound layer provided between the first electrode and the second electrode and including an emission layer. In addition, a first inorganic protective layer is in direct contact with the second electrode and has a specified thickness.

Abstract: An n well region and an n?region surrounding the n well region are provided in the surface layer of a p?silicon substrate. The n?region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p? opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p?opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.

Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.

Abstract: A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.

Abstract: A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is formed between the pull up electrode and the substrate. A movable gate has a first position and a second position. The movable gate is located in the gap between the pull up electrode and the substrate. The movable gate is in contact with the pull up electrode when the movable gate is in a first position and is in contact with the oxide to form a gate region when the movable gate is in the second position. The movable gate, in conjunction with the source region and the drain region and when the movable gate is in the second position, form a transistor that can be utilized as a non-volatile memory element.

Abstract: The semiconductor device includes: a semiconductor substrate; a pair of injection elements; an active barrier structure; and a p-type ground region. The semiconductor substrate has a main surface and a p-type region formed therein. The active barrier structure is arranged in a region sandwiched between the pair of injection elements over the main surface. The p-type ground region is a ground potential-applicable region which is formed closer to an end side of the main surface than the pair of injection elements and the active barrier structure, bypassing a region sandwiched between the pair of injection elements over the main surface, and which is electrically coupled to the p-type region. The p-type ground region is divided by a region adjacent to the region sandwiched between the pair of injection elements.

Abstract: A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.

Abstract: Provided is a semiconductor device showing stable high-frequency characteristics. A semiconductor device includes the following configuration. A diffusion region into which acceptors are introduced is formed in a silicon substrate. In addition, a non-diffusion region into which the acceptors are not introduced is disposed in the silicon substrate alternately with the diffusion region. In addition, a first insulating layer is provided so as to contact with the silicon substrate. Further, an interconnect is provided on the first insulating layer.

Abstract: A semiconductor device can include a transistor and an isolation region. The transistor is formed in a semiconductor substrate having a first conductivity type. The transistor includes a drift region extending from a drain region toward a source region and having a second conductivity type. The drift region includes a first resurf region near a working top surface and having the first conductivity type. The high voltage isolation island region includes a first well region laterally offset from the drift region. The first well region has the second conductivity type. An isolation region is located laterally between the drain region and the first well region. The isolation region comprises a portion of the semiconductor substrate extending to the top working surface.

Abstract: The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: The high voltage integrated circuit is disclosed. The high voltage integrated circuit comprises a low voltage control circuit, a floating circuit, a P substrate, a deep N well disposed in the substrate and a plurality of P wells disposed in the P substrate. The P wells and deep N well serve as the isolation structures. The low voltage control circuit is located outside the deep N well and the floating circuit is located inside the deep N well. The deep N well forms a high voltage junction barrier for isolating the control circuit from the floating circuit.

Abstract: An integrated circuit structure includes a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; and a deep well region substantially enclosed by the depletion region. The deep well region is of a second conductivity type opposite the first conductivity type, and includes a first portion directly over the deep well region and a second portion directly under the deep well region. A transmission line is directly over the depletion region.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: A semiconductor device 100 includes: a body region 105 of a first conductivity type placed on a principal surface of a substrate 101; a silicon carbide layer 102 including a drift region 107 of a second conductivity type; a channel layer 115 of the second conductivity type formed by silicon carbide and placed on the body region 105 and the drift region 107 on a surface of the silicon carbide layer 102; a gate insulating film 111 placed on the channel layer 115; a gate electrode 113 insulated from the silicon carbide layer 102 by the gate insulating film 111; a source electrode 116 provided on the silicon carbide layer 102; and a drain electrode 114 provided on a reverse surface of the substrate 101, wherein the source electrode 116 is in contact with the body region 105 and the channel layer 115; and a second conductivity type impurity concentration on a surface of the silicon carbide layer 102 that is in contact with the source electrode 116 is less than or equal to a second conductivity type impurity concen

Abstract: This specification discloses a semiconductor device having higher electric strength. The semiconductor device disclosed in this specification has a semiconductor element region, a peripheral termination region, a peripheral electrode, an insulating film, and an intermediate electrode. A semiconductor element is formed within the semiconductor element region. The peripheral termination region is formed around the semiconductor element region and formed of a single conductive type semiconductor. The semiconductor element region and the peripheral termination region are exposed at one surface of a semiconductor substrate. The peripheral electrode is formed on a surface of the peripheral termination region and along a circumference of the semiconductor substrate. The insulating film is formed on the surface of the peripheral termination region and between the semiconductor element region and the peripheral electrode. The intermediate electrode is formed on the insulating film.

Abstract: The method for producing a field effect transistor on a substrate comprising a support layer, a sacrificial layer and a semi-conducting layer comprises forming an active area in the semi-conducting layer. The active area is delineated by a closed peripheral insulation pattern and comprises an additional pattern made from insulating material. The method also comprises etching the insulating material of the additional pattern to access the sacrificial layer, etching the sacrificial layer resulting in formation of a first cavity, forming a dielectric layer on a top wall of the first cavity, and depositing an electrically conducting layer in the first cavity. The closed peripheral insulation pattern is formed through the semi-conducting layer and the sacrificial layer.

Abstract: A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer.

Abstract: A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. The first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second source electrode of the JFET respectively.

Abstract: According to one embodiment, a semiconductor device includes: a substrate in which, on a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type and a semiconductor layer of the second conductivity type are stacked; trench that define an element forming region in the substrate; element isolation insulation film formed in the trench; and a semiconductor element formed in the element forming region. The trench include first trench formed from the surface of the substrate to boundary depth and second trench formed from the boundary depth to the bottom and having a diameter smaller than that of the first trench. First diffusion layers connected to the buried layer are formed around the first or second trench according to inter-element breakdown voltage required of the semiconductor element.

Abstract: According to an embodiment, a power amplifier is provided with at least one first growth ring gate structure and multiple second growth ring gate structures. The first growth ring gate structure is bounded by a semiconductor layer and performs a power amplification operation. The multiple second growth ring gate structures are bounded by the semiconductor layer and are arranged adjacently around the first growth ring gate structure in a surrounding manner. When the first growth ring gate structure performs a power amplification operation, the multiple second growth ring gate structures are depleted by applying a reverse bias to the multiple second growth ring gate structures whereby the depleted multiple second growth ring gate structures isolate the first growth ring gate structure from a surrounding portion.

Abstract: A vertical semiconductor component having a semiconductor body, which has an inner region and an edge region that is arranged between the inner region and an edge of the semiconductor body. At least one semiconductor junction between a first semiconductor zone of a first conduction type, said first semiconductor zone being arranged in the region of a first side of the semiconductor body in the inner region, and a second semiconductor zone of the second conduction type, said second semiconductor zone adjoining the first semiconductor zone in the vertical direction.

Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

Abstract: A MOSFET driver compatible JFET device is disclosed. The JFET device can include a gate contact, a drain contact, and a source contact. The JFET device can further include a first gate region of semiconductor material adjacent the gate contact and a second region of semiconductor material adjacent the first gate region. The first gate region and the second gate region can form a first p-n junction between the first gate region and the second gate region. The JFET device can further include a channel region of semiconductor material adjacent the source contact. The channel region and the second gate region can form a second p-n junction between the second gate region and the channel region.

Abstract: A depletion transistor includes a source region and a drain region of a first conductivity type, a channel region of the first conductivity type arranged between the source region and the drain region and a first gate electrode arranged adjacent the channel region and dielectrically insulated from the channel region by a gate dielectric. The depletion transistor further includes a first discharge region of a second conductivity type arranged adjacent the gate dielectric and electrically coupled to a terminal for a reference potential. The depletion transistor can be included in a charging circuit.

Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.

Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.

Abstract: Disclosed herein is a semiconductor memory device including floating body cells. The semiconductor memory device includes memory cell active regions formed on a Silicon-On Isolator (SOI) semiconductor substrate, a plurality of floating body cell transistors formed in the memory cell active regions, and “inactive transistors” for providing cell isolation that are formed between the plurality of floating body cell transistors. Here, the inactive transistors for providing cell isolation are controlled so that they always are in an OFF state while the semiconductor memory device is operating.

Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: A MOSFET comprises a first semiconductor region having a first surface, a first insulation-filled trench region extending from the first surface into the first semiconductor region, and strips of semi-insulating material along the sidewalls of the first insulation-filled trench region. The strips of semi-insulating material are insulated from the first semiconductor region.

Abstract: A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer.

Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.

Abstract: This specification discloses a semiconductor device having higher electric strength. The semiconductor device disclosed in this specification has a semiconductor element region, a peripheral termination region, a peripheral electrode, an insulating film, and an intermediate electrode. A semiconductor element is formed within the semiconductor element region. The peripheral termination region is formed around the semiconductor element region and formed of a single conductive type semiconductor. The semiconductor element region and the peripheral termination region are exposed at one surface of a semiconductor substrate. The peripheral electrode is formed on a surface of the peripheral termination region and along a circumference of the semiconductor substrate. The insulating film is formed on the surface of the peripheral termination region and between the semiconductor element region and the peripheral electrode. The intermediate electrode is formed on the insulating film.

Abstract: In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device.

Abstract: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.

Abstract: An integrated circuit structure includes a semiconductor substrate of a first conductivity type; a depletion region in the semiconductor substrate; and a deep well region substantially enclosed by the depletion region. The deep well region is of a second conductivity type opposite the first conductivity type, and includes a first portion directly over the deep well region and a second portion directly under the deep well region. A transmission line is directly over the depletion region.

Abstract: A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily.

Abstract: A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

Abstract: A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.

Abstract: An off-current is reduced in an organic transistor, with which an organic transistor array is formed. A display apparatus is constructed using the organic transistor array. The organic transistor includes a substrate, a gate electrode, a separating electrode, a gate insulating film, a source electrode, a drain electrode, and an organic semiconductor layer. The organic transistor has a region in which the separating electrode and the organic semiconductor layer are laminated. A power supply is connected to the separating electrode.

Abstract: A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point.

Abstract: A semiconductor device, including: a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a trench formed in the semiconductor region; a trench diffusion layer of the first conductivity type formed along wall surfaces of the trench; and a buried conductor buried in the trench, wherein an insulation film is further disposed between the wall surfaces of the trench and the buried conductor.

Abstract: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.

Abstract: Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.