Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.

Abstract: Integrated circuitry includes a semiconductive substrate, an insulative material over the semiconductive substrate, and a series of alternating first and second conductive lines, the first and second lines being spaced and positioned laterally adjacent one another over the insulating layer. At least some of the laterally adjacent conductive lines may have different cross-sectional shapes in a direction perpendicular to the respective line. Alternatively, or in addition, individual second series conductive lines may be spaced from adjacent first series conductive lines a distance that is less than a minimum width of the first series lines.

Abstract: The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.

Abstract: In the semiconductor integrated circuit device, a first P+ type buried layer formed as an anode region and an N+ type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.

Abstract: The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Abstract: In a semiconductor device having an STI structure, a space is formed by causing a recession in an oxide film on a surface of a substrate with regard to a sidewall surface of a device isolation trench at an edge of the device isolation trench, and a Si film is formed so as to fill the trench. Further, the oxide film is removed from the surface of the substrate while leaving the Si film, and the trench is filled with an oxide film. Further, the Si film is oxidized to form an oxide film forming a part of the oxide film.

Abstract: A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.

Abstract: Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce parasitic transistor, the epitaxial layers and substrate are etched in a V-groove. Each etched region is dielectrically isolated by the poly-Si (42).

Abstract: Fault remediation functions are embodied in a semiconductor structure in which high quality epitaxial layers of monocrystalline materials are made to overlie monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Fault remediation is carried out in one instance by recognizing the presence of a fault and in another instance by providing fault correction.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The epitaxial monocrystalline material has an upper surface that is positioned coplanar with a surface of an adjacent layer carried by the substrate, thereby facilitating the fabrication of overlying layers that bridge the epitaxial monocrystalline material and the adjacent layer.

Abstract: The present invention provides semiconductor devices having at least one silicon region in a silicon carbide wafer in which is fabricated a low voltage semiconductor device such as for example, MOSFET devices, BiCMOS devices, Bipolar devices, etc., and on the same chip, at least one silicon carbide region in which is fabricated a high voltage (i.e., >1000V) semiconductor device using techniques well known in the art, such as for example, LDMOSFET, UMOSFET, DMOSFET, IGBT, MESFET, and JFET devices.

Abstract: A semiconductor integrated circuit device comprises an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed so as to surround a part of the substrate 1, in which a p−-type well is formed, a p−-type well 15-1 formed in the substrate 1, a p−-type well 15-2 formed in a part of the substrate 1, which is surrounded by the n-type well, an embedded n-type well 12-1 formed below the p−-type well 15-1, and an n-type well 12-2 which is formed below the p−-type well 15-2 and which is connected to the n-type well 8-2. Thus, it is possible to provide a semiconductor integrated circuit device capable of suppressing the increase of the number of photolithography steps and reducing the manufacturing costs.

Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.

Abstract: A method for fabricating a MIM capacitor of a MDL logic or analog circuit of a semiconductor device. A conductivity layer is formed on a semiconductor substrate having a first inter-level insulating layer. A capping metal layer having an etching rate higher than an oxide layer is formed on the conductivity layer. A lower electrode comprising a “conductivity layer/capping metal layer” deposition is formed by selectively etching the capping metal layer and the conductivity layer in order to expose a predetermined part of the surface of the first inter-level insulating layer. A second inter-level insulating layer is formed on the first inter-level insulating layer covering the lower electrode. A via hole is formed by selectively etching both the second inter-level insulating layer and the lower electrode thereby to expose a portion of the lower electrode so that a tapered capping metal layer remains along the lower edges of the via hole.

Abstract: In a semiconductor substrate, functional circuit structures and dummy structures are bounded by an insulation well that includes a buried diffusion region and a peripherally encompassing depth diffusion. A peripheral contact diffusion is additionally provided within a surface region defined by the depth diffusion.

Abstract: In a high breakdown voltage semiconductor device, a buried diffusion region is formed on a semiconductor substrate and an epitaxial layer is formed on the buried diffusion region and the substrate. The epitaxial layer includes a low breakdown voltage element region adjoined by a high breakdown voltage isolation region. A method for forming the high breakdown voltage isolation region complies with a Resurf condition by adjusting a thickness and an impurity concentration of the epitaxial layer.

Abstract: A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilcon film.

Abstract: An improved gas phase synthesized diamond, CBN, BCN, or CN thin film having a modified region in which strain, defects, color and the like are reduced and/or eliminated. The thin film can be formed on a substrate or be a free-standing thin film from which the substrate has been removed. The thin film can be stably and reproducibly modified to have an oriented polycrystal structure or a single crystal structure. The thin film is modified by being subjected to and heated by microwave irradiation in a controlled atmosphere. The thin film has a modified region in which a line width of the diamond spectrum evaluated by Raman spectroscopy of 0.1 microns or greater is substantially constant along a film thickness direction of the thin film, and the line width of the modified region is 85% or less of a maximum line width of the residual portion of the film thickness.

Abstract: A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate and isolation trenches are formed at both sides of the well region. A high density second conductive type buried layer is formed in the semiconductor substrate which is formed at the bottom of the isolation trench. The buried layer is formed in two regions surrounding respective bottoms of two adjacent isolation trenches. The two regions are electrically connected with each other and in direct contact with the well region. An extrinsic base region and a device isolation region are formed sequentially onto the semiconductor substrate using a nitration layer pattern as a mask, wherein the nitration layer pattern is formed on the surface of semiconductor substrate.

Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: A method of forming a nonvolatile semiconductor memory device of the present invention comprises: an isolation film formed on a semiconductor substrate of one conductivity type; a floating gate which is formed in an active region isolated by said isolation film so as to be disposed in a gap between adjacent isolation films and make each of end portions coincident with each end of said isolation film in a self-aligned manner; a tunnel oxide film which covers said floating gate; a control gate formed on said tunnel oxide film so as to comprise a region which overlaps said floating gate; a diffusion region of an opposite conductivity type and formed in a surface of the semiconductor substrate adjacent to said floating gate and the control gate.

Abstract: A totally self-aligned transistor with shallow trench isolation. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. Channel dopant deposited in the gate area is also self-aligned to the gate of the transistor.

Abstract: Prevents deterioration of the element characteristics of the gate voltage tolerance and the like which is caused by the metallic contaminants that are sealed in the element forming region at the time of applying a trench separator in a SOI substrate. Polysilicon 12 is formed on the side walls of the trench 5, and the metallic contaminants within the element forming region are collected in this polysilicon 12.

Abstract: According to the present invention, a semiconductor device, and method for producing the same, is provided comprising: a resistance component formed in a component active region enclosed by a component separating-insulating layer on a semiconductor base; one pair of first diffusion layers containing a high concentration of impurities which are provided at both ends of the component active region; silicide layer adhering to a first diffusion layer; second diffusion layer containing a low concentration of impurities which is provided in the component active region between the pair of first diffusion layers; wherein a first diffusion layer and silicide layer comprise the terminal areas of the resistance component, and the second diffusion layer comprises a resistance member area of the resistance component.

Abstract: A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.

Abstract: A semiconductor device includes a groove formed in a surface of a first semiconductor substrate of one conductivity type in order to partition and isolate first and second device regions. A first insulating film on the first semiconductor substrate of the first device region also contacts the groove. A second insulating film covers an inner wall of the groove. The first insulating film is thicker than the second film in order to increase the breakdown voltage and facilitate carrying a higher current. This thickness relationship also aids manufacturing.

Abstract: A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.

Abstract: A method of forming field oxide during the manufacture of a semiconductor device comprises the steps of providing a semiconductor wafer having a plurality of recesses or trenches therein. A layer of texturized polycrystalline silicon is formed within the recesses, which is subsequently oxidized to form field oxide. The instant method reduces stress imparted to the die as the texturized polycrystalline silicon has voids or holes which absorb the expanding volume as the silicon is oxidized to form field oxide.

Abstract: In a semiconductor device, first and second substrates are supported with respective first major surfaces in opposing, parallel and spaced relationship. A conductor layer of low resistivity material is provided on a selected one of the opposing and spaced major surfaces, in intimate contact and spaced from the opposed major surface of the other substrate. An active device is formed in the first substrate with a region electrically connected to the conductor layer. A contact region is exposed at the second major surface of the first substrate and extends through the first substrate and into electrical contact with the conductor layer.

Abstract: We have discovered advantageous substrates for III-V nitride semiconductors such as GaN. The substrate material is of the YbFe.sub.2 O.sub.4 or InFeO.sub.3 (ZnO).sub.n structure type and has general composition RAO.sub.3 (MO).sub.n, where R is one or more of Sc, In, Y and the lanthanides (atomic number 67-71); A is one or more of Fe(III), Ga, and Al; M is one or more of Mg, Mn, Fe(II), Co, Cu, Zn and Cd; and n is an integer.gtoreq.1, typically<9. Furthermore, the substrate material is selected to have a lattice constant that provides less than .+-.5% lattice mismatch with the III-V nitride semiconductor material that is to be deposited thereon. At least some of the substrate materials (e.g., ScMgAlO.sub.4) typically can be readily and relatively cheaply produced in single crystal form, are readily clearable on the basal plane, and do essentially not interact chemically with the III-V nitride under typical deposition conditions.

Abstract: In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.

Abstract: A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.

Abstract: A device isolation area structure in a semiconductor device is composed of two layers of a first device isolation film formed by selectively oxidizing a surface of a silicon substrate, and a second device isolation region formed in a single crystal silicon film covering the first device isolation film. A guard band region may be formed within the semiconductor substrate and immediately below the first device isolation film so as to be in contact with the first device isolation film. The device isolation area structure is suitable to high integration of the semiconductor device and provides less possibilities of occurrence of crystal defects.

Abstract: A bipolar transistor includes a substrate, an insulating layer formed on the substrate, and a semiconductor layer having a bottom surface and side surfaces surrounded by the insulating layer. The semiconductor layer includes a collector region formed in a first surface portion of the semiconductor layer, and a collector lead region having a concentration higher than that of the collector region. The collector read region includes a silicon single crystal layer formed in a second surface portion of the semiconductor layer, and a polysilicon layer having side surfaces surrounded by the silicon single crystal layer. A base region is formed on the collector region, and an emitter region is formed in the base region.

Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.

Abstract: A dielectric isolated substrate wherein a connecting polycrystalline silicon layer has smooth and flat surface on which a single crystal support is bonded and has a densified crystal structure, or is obtained by further heat treatment at 800.degree. C. or higher after deposition, or has no orientation as to growth direction of polycrystalline silicon, or a buffering layer is formed between a polycrystalline silicon layer and a single crystal support, is excellent in bonding between the single crystal support and the polycrystalline silicon layer by preventing voids at the bonded surface, while enhancing reliability.

Abstract: An integrated semiconductor circuit includes a substrate, an epitaxial layer having transistor base regions, a first and a second (11) insulating oxide layer, and a protective layer. The first oxide layer carries heavily doped polycrystalline layers, including an electric contact layer, a screening layer and a connecting layer. The connecting layer electrically connects the screening layer to the epitaxial layer, through the electric contact layer. The screening layer prevents the occurrence of inversion and parasite components in the epitaxial layer between the base regions. The polycrystalline layer arrangement is simple and can be produced in a common process step. The arrangement is able to withstand high temperatures and enables the second insulating layer to be readily applied.

Abstract: A method for fabricating an isolation region in a semiconductor substrate that produces neither a "bird's beak" nor a "bird's head". A smooth substrate surface is provided, which is preferable for multi-layered wiring. The packing density of devices in a bipolar IC circuit can be increased. A sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching. The inner surface of the isolation groove is coated by an insulating film. Then the groove is buried with polycrystalline semiconductor material. The polycrystalline material which is deposited on the surface of the substrate is etched off. At the same time the polycrystalline material in the groove is also etched to a specific depth from the surface. An insulating film is then deposited so as to again fill the groove. Then the substrate surface is polished or etched to provide a flat surface.