Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: Disclosed are an array substrate and a preparation method thereof, and a digital microfluidic chip. The preparation method includes: forming a plurality of photoelectric detection devices on a silicon-based substrate; transferring the photoelectric detection devices to a base substrate by adopting a micro transfer printing process; and forming a plurality of transparent driving electrodes on the base substrate, wherein the transparent driving electrodes are insulated from the photoelectric detection devices.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface of the substrate. The substrate has a through opening extending between the first surface of the substrate and the second surface of the substrate. The semiconductor device package also includes a conductive pad in the through opening and approximal to the second surface of the substrate. The conductive pad has a first surface and a second surface opposite to the first surface of the conductive pad. The semiconductor device package also includes a conductive pillar in contact with the first surface of the conductive pad. The second surface of the conductive pad protrudes from the second surface of the substrate. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

Abstract: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.

Abstract: Methods of enhancing selective deposition are described. In some embodiments, a passivation layer is deposited on a metal surface before deposition of a dielectric material. A block I molecule is deposited on a metal surface, and a block II molecule is reacted with the block I molecule to form a passivation layer.

Abstract: The present disclosure protects a flexible substrate and prevents the generation of a crack and the development of a crack inside a display device. A display device includes a display area and a frame region which is a non-display area provided outside the display area, and in the frame region, at least a flexible substrate and a moisture-proof layer are disposed in this order, and a metal oxide film is further provided between the flexible substrate and the moisture-proof layer.

Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

Abstract: A semiconductor device may include a first active component region (20) and a second active region (22) extending flat along a first lateral direction (L1) and a second lateral direction (L2) deviating from said first lateral direction. The semiconductor device may include a trench isolation structure (10, 10?) that electrically isolates the first active component region (20) from the second active region (22) along the first lateral direction (L1) and comprises at least one electrically conductive sidewall (14, 14?, 14?); said trench isolation structure (10) having a continuously extending insulating trench isolation base wall (30) and a plurality of spaced apart trench isolation portions (32a, 32b) with electrically conductive sidewall portions (14a, 14b) therebetween. The plurality of trench isolation portions (32a, 32b) and the electrically conductive sidewall portions (14a, 14b) are spaced (a, b) from the base wall (30).

Abstract: A flexible display substrate includes a flexible substrate and an insulation layer on the flexible substrate. The flexible substrate includes a display area and a non-display area surrounding the display area. A crack stopping component is on the insulation layer in the non-display area, and configured to stop a crack in the non-display area from extending to the display area.

Abstract: A semiconductor structure includes a first interconnect structure, a second interconnect structure, a molding, a first seal ring and a second seal ring. The molding surrounds the die. The molding and the die are disposed between the first interconnect structure and the second inter connect structure. The first seal ring is disposed in the first interconnect structure. The second seal ring is disposed in the second interconnect structure.

Abstract: A power semiconductor die has a semiconductor body, an insulation layer on the semiconductor body, a passivation structure arranged above the insulation layer so as to expose a first insulation layer subsection that extends to an edge of the power semiconductor die, and an interruption structure in the first insulation layer subsection.

Abstract: Chamferless via structures and methods of manufacture are provided. The structures include a conductive line and a set of chamferless wiring vias formed in a dielectric material with at least one of the vias in contact with the conductive line. The set of chamferless wiring vias is formed with at least a first subset of wiring vias of a first height and a second subset of wiring vias of a second height. The method includes filling trenches within a substrate with a conductive material to form a set of wiring vias with a first height. Next, a block mask is used over a capping material layer to expose a portion of the conductive material layer. The capping material and the conductive material of the set of wiring vias defined by the block mask are etched forming a subset of wiring vias of the second height.

Abstract: An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.

Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.

Abstract: Systems and methods for the design and use of a System-in-Package (SiP) device with a connection layout for minimizing a system Printed Circuit Board (PCB) using the SiP are provided.

Abstract: A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate has a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a patterned conductive layer in a level of the insulating layer. The patterned conductive layer includes conductors in and along the edge region. The edge region is partially exposed from the conductors, as viewed from a top-view perspective. The conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductors.

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

Abstract: To provide a semiconductor device, an image pickup device, and a method for manufacturing the semiconductor device that reduce wiring capacity by using gaps and maintain mechanical strength and reliability. A semiconductor device including: a multilayered wiring layer in which insulating layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through-hole that is provided to penetrate through at least one or more insulating layers from one surface of the multilayered wiring layer and has an inside covered with a protective side wall; and a gap that is provided in at least one or more insulating layers immediately below the through-hole.

Abstract: A saw bow is provided and designed such that the conductors of the saw bow will break at a predictable location when using modern dicing techniques. This results in a break in the circuit provided by the saw bow, with any exposed conductors not being on the die side. Further, by providing a known breaking point in the saw bow, modern dicing techniques such as plasma dicing can be used, thereby allowing for the saw lane to be made narrower, which will in turn increase the number of wafers that can be included on a wafer.

Abstract: Component surfaces are coated with thermally stable layers. In particular infrared mirror surfaces or surfaces of combustion chambers are coated with at least one layer consisting of thermally stable Al—Cr—O in such a manner that the absorption, reflection or transmission of infrared radiations (hereinafter also called thermal radiations) is influenced.

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

Abstract: A wafer-level packaging method includes providing a base substrate and providing first chips. A photolithographic bonding layer is formed on the base substrate or on the first chips. First vias are formed in the photolithographic bonding layer. The first chips are pre-bonded to the base substrate through a photolithographic bonding layer with each first chip corresponding to a first via. A thermal compression bonding process is used to bond the first chips to the base substrate such that an encapsulation material fills between adjacent first chips and covers the first chips and the base substrate. The base substrate is etched to form second vias through the base substrate with each second via connected to a first via to form a first conductive via. A first conductive plug is formed in the first conductive via to electrically connect to a corresponding first chip.

Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.

Abstract: A semiconductor device includes an integrated circuit and a guard ring. The integrated circuit includes a first circuit and a second circuit separated from the first circuit. The guard ring is disposed around the first circuit and between the first circuit and the second circuit. The guard ring includes an outer ring, an inner ring, and two connectors. The outer ring is disposed around the first circuit and has a first gap. The inner ring is disposed between the outer ring and the first circuit and has a second gap. The two connectors connect the outer ring and the inner ring. The outer ring, the inner ring, and the two connectors form a closed loop.

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.

Abstract: Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes an inductor included in an integrated circuit device, and a first oscillator and a second oscillator included in the integrated circuit device. The first oscillator includes a first terminal coupled to a conductive path of the inductor to provide a first signal. The second oscillator includes a second terminal coupled to the conductive path to provide a second signal. The first and second signals have different frequencies.

Abstract: Through-substrate vias (TSVs) extend through a high resistivity semiconductor substrate laterally spaced and isolated from an active device formed over the substrate by deep trench isolation (DTI) structures. The deep trench isolation structures may extend partially or entirely through the substrate, and may include an air gap. The deep trench isolation structures entirely surround the active device and the TSVs.

Abstract: According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

Abstract: A semiconductor device includes an annular seal ring formed in a seal ring region surrounding a circuit forming region. The seal ring includes a BOX layer, an n-type semiconductor layer, and an annular electrode portion comprised of multiple layers of wirings. The electrode portion is electrically connected with the n-type semiconductor layer through a plug electrode.

Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.

Abstract: A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance.

Abstract: A semiconductor device includes a high resistivity substrate, a transistor formed on the high resistivity substrate, and a deep trench device isolation region formed in the high resistivity substrate to surround the transistor. Particularly, the high resistivity substrate has a first conductive type, and a deep well region having a second conductive type is formed in the high resistivity substrate. Further, a low concentration well region having the first conductive type is formed on the deep well region, and the transistor is formed on the low concentration well region.

Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.

Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Abstract: A semiconductor device includes a high resistivity substrate, a first deep well region having a first conductive type and formed in the high resistivity substrate, a second deep well region having a second conductive type and formed on the first deep well region, a first well region having the first conductive type and formed on the second deep well region, and a transistor formed on the first well region.

Abstract: A method for forming a seal ring structure provides a semiconductor substrate having a first doping region formed over a top portion thereof. The method forms a plurality of patterned photoresist layers over the semiconductor substrate, encircling the semiconductor substrate, wherein each of the patterned photoresist layers has a plurality of parallel strip portions extending along a first direction and a plurality of bridge portions formed between the parallel strip portions, and then performs an etching process to a first doping region of the substrate. The method then removes the first doping region not covered by the patterned photoresist layers and forms a plurality of patterned first doping regions. The method then removes the patterned photoresist layers and forms an isolation region between and adjacent to the patterned first doping regions. Finally, the method forms a plurality of interconnect elements over the semiconductor substrate.

Abstract: A semiconductor die comprises a first active device, at least one of a second active device and a passive component, and electromagnetic shielding configured to at least partially electromagnetically isolate the first active device from the at least one of the second active device and the passive component. The electromagnetic shielding includes one of a grounded metal layer and via stack, and a grounded metal layer disposed one of above and below the first active device.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.

Abstract: Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors. Each of the decoupling capacitors may include a first capacitor metal wiring pattern connected to a high power supply line, a second capacitor metal wiring pattern spaced apart from the first capacitor metal wiring pattern and connected to a low power supply line, and a dielectric pattern between the first capacitor metal wiring pattern and the second capacitor metal wiring pattern.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include first redistribution layers and second redistribution layers electrically connected to the connection pads and formed of one or more layers, at least one of the first redistribution layers is disposed between a plurality of insulating layers of the first connection member, and at least one of the second redistribution layers includes sensor patterns recognizing a fingerprint.

Abstract: A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a seal ring area, forming a buried deep-well layer in the substrate of the seal ring area, forming a first well region and a second well region in the substrate above the buried deep-well layer with the first well region surrounding the device area and the second well region surrounding the first well region, forming a heavily doped region in the substrate above the buried deep-well layer and between the first well region and the second well region, and forming a seal ring structure connecting to the heavily doped region. The buried deep-well layer, the first well region, and the second well region all have a first doping type while the heavily doped region and the substrate have a second doping type.

Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Abstract: A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first metal pattern layer is embedded in the dielectric layer and directly below the bonding pad. The first metal pattern layer includes a first body portion and first island portions. The first body portion has first openings in a central region of the first body portion and second openings arranged along a peripheral region of the first body portion and surrounding the first openings. The first island portions are correspondingly disposed in the second openings and spaced apart from the first body portion. First interconnect structures are disposed in the dielectric layer and correspond to the first island portions, such that the bonding pad is electrically connected to the first island portions.

Abstract: According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to each other; an electrically insulating structure arranged in the first region of the carrier, wherein the second region of the carrier is free of the electrically insulating structure; a first electronic component arranged in the first region of the carrier over the electrically insulating structure; a second electronic component arranged in the second region of the carrier; wherein the electrically insulating structure includes one or more hollow chambers, wherein the sidewalls of the one or more hollow chambers are covered with an electrically insulating material.

Abstract: A semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, includes no portion provided between the interconnects, and is formed of a second insulating material different from the first insulating material.

Abstract: A method for processing a 3D semiconductor device, the method including: processing a first layer comprising first transistors, forming a first power distribution grid to provide power to the first transistors, processing a second layer overlying the first transistors and including second transistors, where the second layer includes a through layer via with diameter of less than 150 nm, forming a second power distribution grid overlaying the second transistors, where the first power distribution grid includes first power conductors and the second power distribution grid includes second power conductors, and where the second power conductors are substantially wider or thicker than the first power conductors, and where the device includes a plurality of vias to connect the second power distribution grid to the first power distribution grid.