Abstract: A semiconductor device includes a semiconductor substrate, an isolation film that is provided in one principal surface of the semiconductor substrate, wiring that is arranged on the isolation film, a diffusion layer that is formed inside the semiconductor substrate and located in the vicinity of the isolation film, and an insulating film that covers the diffusion layer over the one principal surface of the semiconductor substrate. The insulating film further covers a portion of the isolation film near to the diffusion layer and comes into contact with the side of the wiring near to the diffusion layer.

Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Abstract: Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.

Abstract: One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of LOCOS regions may be formed on opposite sides of a PFET gate and its corresponding channel, or one or more LOCOS regions may more fully surround, or even completely surround, the PFET channel. In addition, one or more slits may be formed in the LOCOS regions as appropriate to reduce or even completely neutralize the compressive strain in certain directions that would otherwise be applied without the slits. These techniques may be used in silicon-on-insulator (SOI) wafers with or without hybrid orientation technology (HOT) regions.

Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Abstract: Disclosed is a photodiode array which includes a plurality of p-i-n photodiodes arrayed on a semi-insulative semiconductor substrate, each photodiode including an n-type semiconductor layer grown on the substrate, an i-type semiconductor layer grown on the n-type semiconductor layer, a p-type semiconductor layer grown on the i-type semiconductor layer, an n-type electrode provided on the n-type semiconductor layer in a region exposed by partially removing the p-type semiconductor layer and the i-type semiconductor layer, and a p-type electrode provided on the p-type semiconductor layer. A trench is provided between the two adjacent photodiodes by partially removing the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer. Consequently, the size and pitch of the photodiodes can be decreased and crosstalk between the photodiodes can be reduced. Also disclosed is an optical receiver device including the photodiode array.

Abstract: Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided on the SiC substrate. The epitaxial SiC emitter region has a second conductivity type, different from the first conductivity type. The epitaxial SiC emitter region has first and second portions. The first portion is provided on the SiC substrate and the second portion is provided on the first portion. The second portion has a higher carrier concentration than the first portion. Related methods of fabricating BJTs are also provided herein.

Abstract: In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

Abstract: An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

Abstract: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

Abstract: In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The field plate (40) comprises a plurality of connection locations (47) and a plurality of electrical connectors (45) connecting said plurality of connection locations (47) to a potential.

Abstract: A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.

Abstract: Image sensors and methods of manufacturing an image sensor are disclosed. A disclosed photo diode may receive short wavelength light in its depletion region without exhibiting defective phenomenon such as noise and dark current. In the illustrated example, this performance is achieved by forming a trench type light-transmission layer to occupy a major surface of the photo diode so as to reduce the area available for defects on the surface of the semiconductor substrate. As a result of this reduction, the depletion region formed upon the operation of the sensor may extend toward the surface of the semiconductor substrate without concern for defects. The image sensor may be manufactured without forming a blocking layer in connection with a silicide layer.

Abstract: The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a peripheral portion. A plurality of parallel first isolation devices are positioned in the semiconductor substrate in the memory cell area. A second isolation device is positioned in the semiconductor substrate in the peripheral portion, and parallel with the first isolation device. A dummy buried doping region is positioned in the semiconductor substrate, and is positioned between the memory cell device and the peripheral portion and parallel with the second isolation device. An oxide area is formed on the dummy buried doping region. The dummy buried doping region and the oxide region can prevent poly string formation during subsequent processing.

Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

Abstract: A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically align to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.

Abstract: An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to electrically isolate the N type semiconductor layer. The metal layer which is located above the N type semiconductor layer and which forms a wire or a bonding pad is isolated from the N type semiconductor layer in which a diffusion layer or the like has been formed by an insulating film. An N type buried diffusion layer having an impurity concentration higher than that of the N type semiconductor layer is provided between the P type semiconductor substrate and the N type semiconductor layer. In addition, a P type semiconductor layer is formed by means of diffusion between the insulating film and the N type semiconductor layer plus the element isolation layer.

Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.

Abstract: Apart from a semiconductor substrate and a photosensitive region in the semiconductor substrate, which comprises a space charge zone region for generating a diffusion current portion and a diffusion region for generating a diffusion current portion, a photodiode includes an insulation means in the semiconductor substrate for at least partially confining the diffusion region against an adjacent surrounding region of the semiconductor substrate.

Abstract: An electric motor drive system is disclosed which includes a required number of motor driver circuits connected one to each motor armature coil. Fabricated in the form of an integrated circuit, each such motor driver circuit has a parasitic transistor unavoidably created between two neighboring transistors. The parasitic transistor would become conductive when the driver circuit output had a negative potential, adversely affecting the driver circuit operation. An additional transistor is provided in one embodiment of the invention in order to inhibit such action of the parasitic transistor. Becoming conductive when the driver circuit output goes negative, the additional transistor prevents conduction through the parasitic transistor. Another parasitic transistor is intentionally created in another embodiment for the same purpose.

Abstract: An electronic device including a new oxide layer and a method for manufacturing the same are provided. The electronic device of the present invention includes an oxide layer, which is formed of an oxide containing an element from group IIa, an element from group IIb and an element from group IIIb. For example, it can be applied to a solar cell including a back electrode serving as a first electrode layer, a transparent electrically conductive film serving as a second electrode layer having a light-transmitting property, and a semiconductor layer that is provided between the back electrode and the transparent electrically conductive film and functions as a light-absorption layer, and including an oxide layer provided between the semiconductor layer and the transparent electrically conductive film.

Abstract: A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2). The second diffusion region (6) is formed in a predetermined upper surface area of the epitaxial region (3). The second diffusion region (6) has a central portion (6a) and a peripheral portion (6b). The central portion (6a) is formed substantially at the center of the epitaxial region (3) and formed thicker than the peripheral portion (6b). The peripheral portion (6b) is formed in an annular shape so as to surround the central portion (6a). The drain region (7) is formed in an upper surface area of the central portion (6a) of the second diffusion region (6).

Abstract: An integrated circuit device comprising: a body of a first solid material having an upper surface and a major bottom surface; a pocket of a second solid material having a top surface and a side surface, and a bottom surface which contacts a selected portion of said upper surface on said body; said first and second solid materials being so selected as to form, where said pocket contacts said body at said selected portion of said upper surface, an electronic interfacial barrier which is substantially conductive under an applied bias of at least one selected polarity; and a solid electrically insulating region which meets said barrier and adjoins both said body and at least a line on said side surface of said pocket; wherein at least a part of said solid electrically insulating region comprises nitrogen located at least below the level of said electronic interfacial barrier.

Abstract: To isolate at least one electric or electronic element (16, 58), for example an interconnection integrated onto a semiconductor substrate (12), this device comprises at least one isolation means chosen from an isolating layer (84, 86, 90) extending in the substrate and an assembly whose height exceeds that of the element and which comprises, on either side of the element, at least two superposed conductors (60 62 64, 66 68 70), which are integrated into the substrate and extend along the element.

Abstract: A well structure in a high voltage device comprises a first well formed in a substrate, the first well having an opposite conductive type from the substrate; a second well isolated from the first well, the second well having the same conductive type as the substrate; a field stop implant region formed between the first well and the second well and spaced apart from each of the first well and the second well by a given distance, the field stop implant region having the same conductive type as the substrate; and a pick-up region overlapped on the field stop implant region, the pick-up region having the same conductive type as the field stop implant region.

Abstract: On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain field limiting layer and a source/drain region are formed. The one and another MOS transistors are connected in series through the source/drain region common to the two transistors. Accordingly, a semiconductor device can be provided in which increase in pattern layout area is suppressed when elements including a high-breakdown voltage MOS transistor are to be connected in series.

Abstract: A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

Abstract: A dielectric separation type semiconductor device having high voltage withstanding capability includes a primary dielectric layer (3-1) on a first surface of a semiconductor substrate (1), a first conductivity type first semiconductor layer (2) disposed oppositely to the substrate (1) with the primary dielectric layer (3-1) sandwiched, a first conductivity type second semiconductor layer (4) on the first semiconductor layer (2), a second conductivity type third semiconductor layer (5) surrounding peripherally the first semiconductor layer (2), a ring-like insulation film (9) surrounding peripherally the third semiconductor layer (5), a first electrode (6) on the second semiconductor layer (4), a second electrode (7) on the third semiconductor layer (5), a back-surface electrode (8) deposited on a second surface of the substrate (1), and a first auxiliary dielectric layer (3-2) disposed immediately below the second semiconductor layer (4), being junctioned to the second surface.

Abstract: A method for forming a FDSOI device with channel length less than 50 nm with good short channel control. The gate has a tapered polysilicon spacer and a dielectric spacer. A polysilicon gate feature is formed and dielectric sidewall spacers are formed thereon. The polysilicon gate feature is then etched to form tapered poly features separated by a gap. A gate dielectric is deposited at low temperature, then metal is deposited into the gap to form the metal gate.

Abstract: A fabricating system. A processing tool executes a film removal process on a wafer using a chemical mechanism. A metrology tool monitors surface characteristics of the wafer to obtain a measured film thickness thereof before and after a first removal process, wherein the first removal process lasts a first processing duration. The controller, coupled to the processing and metrology tools, determines whether the difference between the measured film thickness and a preset film thickness exceeds a preset value, and determines a second processing duration of a second removal process according to the measured and preset film thickness and the first processing duration.

Abstract: In a semiconductor device having a dual isolation structure, and a method of fabricating the same, an epitaxial layer is formed on the entire surface of the semiconductor device. A device region including the semiconductor device and the epitaxial layer is defined by a device isolation layer. The device isolation layer has a dual structure that includes a diffused isolation layer and a trench isolation layer. The diffused isolation layer is formed in the semiconductor substrate, and surrounds the base and the bottom sidewall of the device region, and the trench isolation layer surrounds the upper sidewall of the device region by vertically penetrating the epitaxial layer.

Abstract: An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region. In another embodiment a first device region, is formed on a semiconductor layer.

Abstract: A protection structure against electrostatic discharges for a semiconductor electronic device that is integrated inside a well is disclosed, wherein the well is formed on a SOI substrate and isolated dielectrically by a buried oxide layer and an isolation structure, which isolation structure includes in turn at least a dielectric trench filled with a filler material. Advantageously, the protection structure is formed at the isolation structure.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: An improved, surface-passivated and electrically isolated solid-state device (including integrated circuits) comprises a silicon wafer with a PN junction or other electronic rectifying barrier contained therein and thermally grown or ion-implanted oxide or nitride isolating grooves in-situ formed in the wafer to isolate it into a plurality of physically integral pockets for use as electrically separately operable components. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the PN junction or rectifying barrier. Through the unique oxide/nitride forming conditions and through curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.

Abstract: A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates a VCSEL with an MSM photodetector on a semi-insulating substrate. A second embodiment builds the layers of a p-i-n photodiode on top of layers forming a VCSEL using a standard VCSEL process. The p-i-n layers are etched away in areas where VCSELs are to be formed and left where the photodetectors are to be formed. The VCSELs underlying the photodetectors are inoperable, and serve to recirculate photons back into the photodetector not initially absorbed. The transmit and receive pairs are packaged in a single package for interface to multifiber ferrules. The distance between the devices is precisely defined photolithographically, thereby making alignment easier.

Abstract: A semiconductor structure containing a field oxide and a process for fabricating the semiconductor structure. The semiconductor structure includes a semiconductor substrate including an isolation region and an active region; a field oxide formed on the semiconductor substrate in the isolation region; a first pad layer formed on the semiconductor substrate in the active region; a second pad layer formed on the semiconductor substrate not covered by the first pad layer, wherein the second pad layer has a smaller thickness than the first pad layer; a mask layer formed on the first pad layer, wherein the mask layer has a larger width than the first pad layer to form a cavity beneath the mask layer and next to the first pad layer; and a mask filler filled in the cavity. By means of the local pad film thinning technique and by forming a mask filler to grow the field oxide layer, the bird's beak encroachment and the thinning effect of the field oxide layer can both be inhibited.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the-same. In one advantageous embodiment the semiconductor device includes a doped layer located over a semiconductor substrate and an isolation trench located in the doped layer. The isolation trench may further include a bottom surface and a sidewall. Additionally, the semiconductor device may include a dopant barrier layer located on the sidewall and a doped region located in the bottom surface.

Abstract: In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.

Abstract: A method for electrically determining in a semiconductor wafer the location of edges of a well that underlies an insulating layer that includes forming in the wafer before forming of the well and the insulating layer a plurality of conductive stripes will that pass under the future insulating layer and extend to varying distances under the insulating layer so as to include stripes that will penetrate an edge to be located so as to form a low resistance connection thereto and stripes that will fall short of an edge to be located. From the stripes of minimum penetration that make low resistance can be determined the location of the well edges.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.

Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a first gate electrode formed on the first insulating film; a second insulating film having a three-layered structure made by sequentially depositing a first kind of insulating layer, a second kind of insulating layer and a first kind of insulating layer on the first gate electrode; a second gate electrode formed on the second insulating film; a first plane including the side surface of the first gate electrode or the side surface of the second gate electrode; and a second plane including the side surface of the second kind of insulating layer, wherein distance between said first plane and said second plane does not exceed 5 nm.

Abstract: A hook switch circuit is shown wherein two high-voltage bipolar transistors, a PNP transistor Q1 and a NPN transistor Q2. that are connected in a regenerative feedback manner to form a bi-stable latch. The regenerative structure permits the use of low beta transistors that may be turned on with a low control current, but still conduct a sufficient off-hook current. Also shown is a polarity steering regenerative switch (MP1, MP2) that provides a power supply voltage from a telephone line pair and may be adapted for a polarity signal and can be combined with a current mirror (MP7) to produce a current signal proportional to the line voltage (LV1).

Abstract: A method of forming a via in an integrated circuit is provided. The method includes forming a stack including a first layer, a hard mask layer, and at least one intermediate layer disposed between the first layer and the hard mask layer. The first layer comprises a first metal line. The method further includes forming a channel in the hard mask layer. The channel has a first side and a second side opposite the first side. The method further includes forming a resist layer having an opening extending over both the first and second sides of the channel. The method further includes forming a metal line trench and a via opening aligned with the first and second sides of the channel. The method further includes filling the filling the metal line trench and the via opening with a conductive material to create a second metal line and a via connecting the second metal line with the first metal line.

Abstract: A solid state device comprises a solid state material substrate; two adjacent semiconductor pockets on the substrate; and a gate layer less than 10 Angstroms thick. The gate layer has at least an atomically smooth bottom major surface, and is perfectly bonded onto the substrate to bridge a gap between the two semiconductor pockets.

Abstract: A CMOS or NMOS device has one or more n-channel FETs disposed on a substrate, the device being resistant to total dose radiation failures, the device further including a negative voltage source, for applying a steady negative back bias to the substrate of the n-channel FETs to mitigate leakage currents in the device, thereby mitigating total dose radiation effects. A method for operating a CMOS or NMOS device to resist total dose radiation failures, the device having one or more n-channel FETs disposed on a substrate, has the steps: (a) disposing the CMOS or NMOS device in a radiation environment, the radiation environment delivering a dose on the order of tens or hundreds of krad (Si) over the period of use of the CMOS device; and (b) applying a negative back bias to the substrate of the NMOS FETs, at a voltage for mitigating leakage currents about the n-channel FETs.

Abstract: A double gate MOS transistor includes a substrate active region defined in a semiconductor substrate and a transistor active region located over the substrate active region and overlapped with the substrate active region. At least one semiconductor pillar penetrates the transistor active region and is in contact with the substrate active region. The semiconductor pillar supports the transistor active region so that the transistor active region is spaced apart from the substrate active region. At least one bottom gate electrode fills a space between the transistor active region and the substrate active region. The bottom gate electrode is insulated from the substrate active region, the transistor active region and the semiconductor pillar. At least one top gate electrode crosses over the transistor active region and has at least one end that is in contact with a sidewall of the bottom gate electrode.