Isolation By Region Of Intrinsic (undoped) Semiconductor Material (e.g., Including Region Physically Damaged By Proton Bombardment) Patents (Class 257/523)
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Patent number: 11538852Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.Type: GrantFiled: September 30, 2020Date of Patent: December 27, 2022Assignee: OSRAM Opto Semiconductors GmbHInventors: Tansen Varghese, Bruno Jentzsch, Laura Kreiner
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Patent number: 10283463Abstract: A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an insulator layer of the SOI substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode.Type: GrantFiled: April 11, 2017Date of Patent: May 7, 2019Assignee: International Business Machines CorporationInventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
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Patent number: 9171918Abstract: A semiconductor device includes an active device region formed in an epitaxial layer disposed on a semiconductor substrate and a buried electrode disposed below the active device region in a cavity formed within the semiconductor substrate. The buried electrode includes an electrically conductive material different than the material of the semiconductor substrate.Type: GrantFiled: July 16, 2014Date of Patent: October 27, 2015Assignee: Infineon Technologies Austria AGInventors: Carsten Ahrens, Johannes Baumgartl, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
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Patent number: 9029246Abstract: An embodiment is a method. A first III-V compound semiconductor is epitaxially grown in a trench on a substrate, and the epitaxial growth is performed in a chamber. The first III-V compound semiconductor has a first surface comprising a facet. After the epitaxial growth, the first surface of the first III-V compound semiconductor is etched to form an altered surface of the first III-V compound semiconductor. Etching the first surface is performed in the chamber in situ. A second III-V compound semiconductor is epitaxially grown on the altered surface of the first III-V compound semiconductor. The epitaxial growth of the first III-V compound semiconductor may be performed in a MOCVD chamber, and the etch may use an HCl gas. Structures resulting from methods are also disclosed.Type: GrantFiled: July 30, 2013Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Ku Chen, Hung-Ta Lin, Pang-Yen Tsai, Huicheng Chang
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Publication number: 20150102456Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler. The first cushion layer is peripherally enclosed by the semiconductor substrate, the second cushion layer is peripherally enclosed by the first cushion layer, and insulating filler is peripherally enclosed by the second cushion layer. A method for fabricating the semiconductor device is also provided herein.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Min LIN, Wei-Lun HONG, Ying-Tsung CHEN, Liang-Guang CHEN
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Patent number: 8729577Abstract: A light-emitting microelectronic device including a first N-type transistor (T1) and a second P-type transistor (T2), the respective gates of which are formed opposite one another, either side of an intrinsic semiconductor material region.Type: GrantFiled: November 7, 2012Date of Patent: May 20, 2014Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Laurent Grenouillet, Maud Vinet
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Patent number: 8587085Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.Type: GrantFiled: November 1, 2011Date of Patent: November 19, 2013Assignee: Renesas Electronics CorporationInventor: Katsuyuki Horita
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Patent number: 8518787Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.Type: GrantFiled: September 6, 2012Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Patent number: 8334451Abstract: A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel.Type: GrantFiled: October 4, 2004Date of Patent: December 18, 2012Assignee: IXYS CorporationInventors: Nestore Polce, Ronald P. Clark, Nathan Zommer
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Patent number: 8299566Abstract: A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.Type: GrantFiled: August 8, 2008Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Hanyi Ding, Alvin Jose Joseph, Anthony Kendall Stamper
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Patent number: 8159003Abstract: A III-nitride device having a support substrate that may include a first silicon body, a second silicon body, an insulation body interposed between the first and second silicon bodies, and a III-nitride body formed over the second silicon body.Type: GrantFiled: November 26, 2008Date of Patent: April 17, 2012Assignee: International Rectifier CorporationInventor: Michael A. Briere
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Patent number: 8106475Abstract: A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively. The coating-type oxide films are not buried in the second element isolation insulating trenches.Type: GrantFiled: June 20, 2008Date of Patent: January 31, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yoshinori Kitamura, Koichi Matsuno, Kazunori Nishikawa
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Patent number: 7977705Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.Type: GrantFiled: May 21, 2009Date of Patent: July 12, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bich-Yen Nguyen, Carlos Mazure
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Publication number: 20110089528Abstract: A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate.Type: ApplicationFiled: December 23, 2010Publication date: April 21, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Markus Zundel, Norbert Krischke
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Patent number: 7873245Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: GrantFiled: December 20, 2007Date of Patent: January 18, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Patent number: 7851884Abstract: A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.Type: GrantFiled: September 24, 2008Date of Patent: December 14, 2010Assignee: Renesas Electronics CorporationInventors: Shuji Asai, Akira Fujihara, Makoto Matsunoshita, Naoki Sakura, Seiji Ichikawa
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Patent number: 7801396Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: GrantFiled: December 20, 2007Date of Patent: September 21, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Patent number: 7791192Abstract: An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.Type: GrantFiled: January 27, 2006Date of Patent: September 7, 2010Assignee: Xilinx, Inc.Inventors: Mukul Joshi, Kumar Nagarajan
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Patent number: 7528033Abstract: A dummy gate may be formed over an isolation layer. A sidewall spacer may be formed next to the dummy gate. The dummy gate and the sidewall spacer may substantially cover or completely cover the edge of isolation layer that is adjacent to an active area of a silicon substrate. Damage to the isolation layer due to a contact hole etching may be prevented, even if there are misalignments.Type: GrantFiled: November 27, 2006Date of Patent: May 5, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Dae Kyeun Kim
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Publication number: 20080237785Abstract: A structure including at least two neighboring components, capable of operating at high frequencies, formed in a thin silicon substrate extending on a silicon support and separated therefrom by an insulating layer, the components being laterally separated by insulating regions. The silicon support has, at least in the vicinity of its portion in contact with the insulating layer, a resistivity greater than or equal to 1,000 ohms.cm.Type: ApplicationFiled: March 31, 2008Publication date: October 2, 2008Applicant: STMicroelectronics S.A.Inventors: Jean-Michel Simonnet, Andre Lhorte, Patrick Poveda
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Patent number: 7382015Abstract: A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.Type: GrantFiled: March 31, 2005Date of Patent: June 3, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Iguchi, Yoshiaki Himeno, Hiroaki Tsunoda
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Patent number: 7340121Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: GrantFiled: February 22, 2005Date of Patent: March 4, 2008Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Patent number: 7279770Abstract: A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is greater than the second width. A first insulating liner is formed along at least lateral sidewalls of the first portion. A spacer material is formed along at least lateral sidewalls of the insulating liner and filling the second portion. A filler material is over said spacer material and within the first portion. Methods for forming the structure are also provided.Type: GrantFiled: June 1, 2005Date of Patent: October 9, 2007Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 7205632Abstract: A microelectronics device including a semiconductor device located at least partially over a substrate, a bombarded area located at least partially over the substrate and adjacent the semiconductor device, and a bombarded attenuator interposing the semiconductor device and the bombarded area.Type: GrantFiled: April 5, 2004Date of Patent: April 17, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Denny D. Tang, Chao-Hsiung Wang
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Patent number: 7199441Abstract: An optical integrated circuit having optical devices is fabricated. These optical devices must be biased in the mutually opposite directions. If such an optical integrated circuit is fabricated using a conductive semiconductor substrate as conventionally, it is not possible to drive the devices by a single power supply since the substrate side is shared as a common polarity by the devices. The present invention realizes a structure where both anode and cathode of each device can be isolated electrically by conventional process technology and provides an optical integrated circuit which can be driven by a single power supply. An optical integrated circuit is formed on a semi-insulative or insulative substrate. A high resistivity region which extends at least from the active layer to the substrate and includes part of an optical waveguide between the devices is formed so as to electrically isolate the anode and cathode of each integrated device from the other device.Type: GrantFiled: August 11, 2004Date of Patent: April 3, 2007Assignees: Hitachi, Ltd., Opnext Japan, Inc.Inventors: Junichiro Shimizu, Shigeki Makino, Masahiro Aoki
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Patent number: 7196395Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.Type: GrantFiled: November 22, 2002Date of Patent: March 27, 2007Assignee: Renesas Technology CorporationInventors: Yukihiro Kumagai, Hideo Miura, Hiroyuki Ohta, Michihiro Mishima, Katsuyuki Nakanishi
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Patent number: 7115988Abstract: The present invention provides a heat spreader with a bypass capacitor to provide substantially instant power and/or to control simultaneous switching noise (SSN). The present invention also provides a semiconductor device package incorporating this heat spreader. In addition, fabrication methods for such heat spreaders and packages are provided. Generally, the heat spreaders and packages of the present invention include an embedded bypass capacitor that can provide decoupling capacitance in order to deliver near instant power to the die and/or minimize SSN. In a preferred embodiment, the embedded bypass capacitor is connected to terminals integrated with the heat spreader (e.g., lid; stiffener) and/or to a package plane (e.g., power plane or ground plane) in the package substrate for connection via the flip chip package's power delivery system to a power source and/or component.Type: GrantFiled: January 21, 2004Date of Patent: October 3, 2006Assignee: Altera CorporationInventor: Vincent Hool
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Patent number: 7112867Abstract: A high resistance region may be used to isolate the body of a first transistor from a body contact.Type: GrantFiled: December 5, 2003Date of Patent: September 26, 2006Assignee: Intel CorporationInventors: Ian Rippke, Stewart Taylor
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Patent number: 6949812Abstract: A semiconductor structure for high frequency operation has a substrate with a doped well formed therein and a buffer layer made of a substrate material covers the well. The buffer layer is made of an undoped material and is disposed on a top side of the well for inhibiting an outdiffusion of a dopant from the well. At least a portion of the substrate is not covered by the buffer layer.Type: GrantFiled: September 24, 2002Date of Patent: September 27, 2005Assignee: Infineon Technologies AGInventors: Reinhard Losehand, Hubert Werthmann
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Patent number: 6787877Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.Type: GrantFiled: December 27, 2002Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventor: Chris W. Hill
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Patent number: 6774454Abstract: A semiconductor and a method of manufacturing thereof form a region with a sufficient gettering effect. A p-type channel MOSFET and an n-type channel MOSFET are formed in an n-type semiconductor layer, which is isolated in a form of islands on an SOI substrate. A high-concentration impurity diffused region is formed in such a manner as to surround the p-type channel MOSFET and the n-type channel MOSFET. The high-concentration impurity diffused region has a surface concentration of between 1×1018 atom/cm3 and 5×1020 atom/cm3 for achieving a desired gettering effect.Type: GrantFiled: October 30, 2002Date of Patent: August 10, 2004Assignee: Fuji Electric Co., Ltd.Inventor: Atsuo Hirabayashi
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Patent number: 6774416Abstract: A small area cascode FET structure capable of operating at mm-wave frequenices cascades a common-source (CS) FET with a common gate (CG) FET, in a smaller physical area than conventional cascode FET structures. The small area of the cascode FET structure is partially achieved by using small source via grounds, requiring a thin gallium arsenide substrate (typically between 50 and 70 microns thick). The overall cascode area is reduced further, by having the two FETs share a common node. This common node is the output drain manifold of the CS FET, which is also an input source finger of the CG FET. In addition, small via grounds within the MIM capacitors and CS FET, which provide the ground connection to the gate manifolds of the CG FET, further reduce circuit area. Advantageously, the small area cascode FET can be applied to many different MMICs to reduce MMIC area requirements and cost.Type: GrantFiled: July 16, 2001Date of Patent: August 10, 2004Assignee: Nanowave, IncInventor: Stephen R. Nelson
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Publication number: 20040082140Abstract: A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial layer. An ion diffusion region with the first type conductivity is formed in the epitaxial layer and surrounds the sidewall and bottom of the deep trench. An undoped polysilicon layer fills the deep trench.Type: ApplicationFiled: January 30, 2003Publication date: April 29, 2004Inventors: Jia-Wei Yang, Chih-Cherng Liao
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Patent number: 6724020Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: GrantFiled: April 23, 2003Date of Patent: April 20, 2004Assignee: Renesas Technology CorporationInventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
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Patent number: 6661068Abstract: A semiconductor structure (1), comprising a isolation region (5) formed on a semiconductor material (10). A pillar (15) is formed in the semiconductor material under the isolation region, where the pillar is capped with a first dielectric material (20) to form a void (16).Type: GrantFiled: March 20, 2002Date of Patent: December 9, 2003Assignee: Semiconductor Components Industries LLCInventors: James A. Durham, Keith Kamekona, Brian Schoonover
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Patent number: 6646320Abstract: Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An “emitter window” is masked directly over the polysilicon trench fill. Heavily doped single emitter poly is deposited and masked over the entire active region. The standard emitter drive then diffuses dopant through the emitter window into the undoped trench poly fill to provide an ohmic contact between the emitter poly and the trench poly fill. Contact to the emitter poly is made from overlying metal.Type: GrantFiled: November 21, 2002Date of Patent: November 11, 2003Assignee: National Semiconductor CorporationInventor: Andrew Strachan
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Patent number: 6635537Abstract: A method of fabricating a gate oxide layer. A mask layer isformed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A portion of the mask layer is removed to expose the substrate at a top edge corner portion of the trench. An insulation layer is formed to fill the trench and covering the exposed substrate and the remaining mask layer. The insulation layer over the remaining mask layer is removed to expose the mask layer. The remaining mask layer is removed to expose the substrate. The exposed substrate is implanted with ions to reduce the oxidation rate. As a result, the substrate at the top edge corner portion of the trench covered with the insulation layer has an oxidation rate higher than the exposed substrate. The insulation layer over the surface level of the substrate is then removed to expose the substrate at the top edge corner portion of the trench.Type: GrantFiled: April 6, 2001Date of Patent: October 21, 2003Assignee: United Microelectronics Corp.Inventors: Tong-Hsin Lee, Shih-Chien Hsu, Chang-Chi Huang, Cheng-Tung Huang, Sheng-Hao Lin
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Publication number: 20030132502Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.Type: ApplicationFiled: December 27, 2002Publication date: July 17, 2003Inventor: Chris W. Hill
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Patent number: 6576937Abstract: A semiconductor device including a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.Type: GrantFiled: May 24, 2001Date of Patent: June 10, 2003Assignee: Hitachi, Ltd.Inventors: Hiroyuki Takazawa, Tohru Oka, Isao Ohbu, Yoshinori Imamura
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Publication number: 20030034544Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.Type: ApplicationFiled: April 10, 2002Publication date: February 20, 2003Inventors: Michael David May, Jonathan Edwards, David L. Waller
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Patent number: 6479880Abstract: An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory device. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.Type: GrantFiled: August 15, 2000Date of Patent: November 12, 2002Assignee: Micron Technology, Inc.Inventor: Fernando González
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Patent number: 6465867Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer, which has been implanted with a compounding material, lines the channel opening. A conductor core fills the opening over the barrier layer. The barrier layer having a dielectric layer proximate portion of a barrier compound varying into a conductor core proximate portion of a pure barrier material.Type: GrantFiled: February 21, 2001Date of Patent: October 15, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Joffre F. Bernard, Sergey D. Lopatin
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Patent number: 6459134Abstract: A semiconductor device with digital and analog circuits has a structure for preventing noise penetration from the digital circuit to the analog circuit. The semiconductor device has a semiconductor substrate, first and second wells independently formed at a surface of the semiconductor substrate, the digital circuit formed at a surface of the first well, and the analog circuit formed at a surface of the second well. The specific resistance of the semiconductor substrate is at least 1000 times as large as the specific resistance of the first well. A conductive guard-ring may be formed in the surface of an area that is between the digital circuit and the second well or between the first well and the second well.Type: GrantFiled: March 27, 2001Date of Patent: October 1, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuya Ohguro, Yoshiaki Toyoshima
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Patent number: 6414368Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.Type: GrantFiled: March 3, 1998Date of Patent: July 2, 2002Assignee: STMicroelectronics LimitedInventors: Michael David May, Jonathan Edwards, David L. Waller
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Patent number: 6404034Abstract: A CMOS circuit has all-around dielectrically insulated source-drain regions. Trenches are formed in the source-drain regions. The trenches are etched onto the mono-crystalline silicon and filled with undoped or very lightly doped silicon. The completely or nearly completely depleted silicon in the trenches represents a dielectrically insulating layer and insulates the source-drain regions towards the adjacent silicon substrate.Type: GrantFiled: July 21, 2000Date of Patent: June 11, 2002Assignee: Infineon Technologies AGInventors: Dietrich Widmann, Martin Kerber
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Patent number: 6388334Abstract: A circuit modification tool and method for a flip-chip IC permits access to circuit regions near the interconnects using an aperture formed through the circuit side. In one embodiment, an etching tool is adapted to remove substrate from the backside of the semiconductor devices and to form a via into the circuit side and beyond a first region in the circuitry. A depth indicating the location of the first region is determined, and a focused ion-beam generator is used to modify a second region in the circuit side using the via for access. After the modification, the first region is rebuilt using the via for access.Type: GrantFiled: July 27, 1999Date of Patent: May 14, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Jeffrey D. Birdsley
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Patent number: 6373099Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.Type: GrantFiled: February 18, 1999Date of Patent: April 16, 2002Assignee: Canon Kabushiki KaishaInventors: Shin Kikuchi, Hayao Ohzu, Shunsuke Inoue, Yoshio Nakamura, Takeshi Ichikawa, Osamu Ikeda
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Publication number: 20010045615Abstract: An integrated circuit is provided in which a relatively low band gap material is used as a semiconductor device layer and in which an underlying high (wide) band gap material is used as an insulating layer. The insulating material has a high thermal conductivity to allow heat dissipation in conjunction with dielectric isolation. The integrated circuit includes one or more semiconductor wells which are each surrounded on their sides by an insulating material. The bottom of the semiconductor wells are disposed atop the high band gap material which provides both electrical isolation and thermal conductivity. A semiconductor substrate may be provided to support the high band gap material. A layer of insulating material may also be provided between the high band gap material and the semiconductor substrate.Type: ApplicationFiled: July 18, 2001Publication date: November 29, 2001Applicant: International Rectifier CorporationInventor: Janardhanan S. Ajit
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Patent number: 6239472Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.Type: GrantFiled: September 1, 1998Date of Patent: May 29, 2001Assignee: Philips Electronics North America Corp.Inventor: Jayarama N. Shenoy
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Patent number: 6127716Abstract: On an n-type semiconductor substrate 41 doped in high density, a p-type semiconductor layer 2, an n-type semiconductor layer 4 doped in high density, which is a collector, a p-type semiconductor layer 6 doped in high density, which is a base, and the n-type semiconductor layer 7, which is an emitter, are sequentially stacked. To the collector layer, a collector electrode 12 is electrically connected, and to the base layer, a base electrode 11 is electrically connected, and to the emitter layer, an emitter electrode 9 is electrically connected, and thus a bipolar transistor is structured. On the bipolar transistor, an insulated isolation area 55 is formed with an opening therein, whose depth reaches the surface of the substrate, and a substrate electrode 48 is formed thereon. On the bipolar transistor and the insulated isolation area 55, an inter-layer dielectric layer 54 is formed having contact holes formed to upper parts of the emitter electrode 49 and to the substrate electrode 48.Type: GrantFiled: October 8, 1999Date of Patent: October 3, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kouhei Morizuka, Masayuki Sugiura