Abstract: In one implementation, a high power semiconductor package is configured as a buck converter including a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost.

Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.?doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.?doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.?doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.

Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

Abstract: An AND-type anti-fuse memory cell, and a memory array consisting of AND-type anti-fuse memory cells. Chains of AND type anti-fuse cells are connected in series with each other, and with a bitline contact, in order to minimize the area occupied by the memory array. Each AND type anti-fuse cell includes an access transistor serially connectable to the bitline or the access transistors of other AND type anti-fuse cells, and an anti-fuse device. The channel region of the access transistor is connected to the channel region of the anti-fuse device, and both channel regions are covered by the same wordline. The wordline is driven to a programming voltage level for programming the anti-fuse device, or to a read voltage level for reading the anti-fuse device.

Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.

Abstract: A semiconductor device has a programming circuit that includes an active device and a programmable electronic component. The programmable electronic component includes a carbon nanotube having a segment with an adjusted diameter. The programmable electronic component has a value that depends upon the adjusted diameter. The programming circuit also includes interconnects that couple the active device to the programmable electronic component. The active device is configured to control a current transmitted to the programmable electronic component.

Abstract: A semiconductor device includes a first metal wiring which is formed over substructure; a first contact plug which is coupled to the first metal wiring and passes through a first interlayer insulating film provided over the substructure; a second metal wiring which is provided over the first interlayer insulating film and is coupled to the first contact plug; a second contact plug which is coupled to the second metal wiring and passes through a second interlayer insulating film which is provided over the first interlayer insulating film; and a fuse pattern and a data read fuse pattern which are coupled to the second contact plug and provided over the second interlayer insulating film.

Abstract: A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. Numerous other aspects are provided.

Abstract: Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

Abstract: A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase in reliability and stability of the semiconductor device. A semiconductor device includes a line pattern formed over a semiconductor substrate, a device isolation film formed at a center part of the line pattern, a contact part formed at both sides of the line pattern, configured to include an oxide film formed over the line pattern, and a bit line formed at a bottom part between the line patterns, and connected to the contact part.

Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.

Abstract: A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.

Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.

Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.

Abstract: Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium material and a silicon material. The diodes further include an interface on the silicon material of ruthenium or ruthenium silicide. A ruthenium silicide interface may be a polycrystalline ruthenium silicide.

Abstract: A semiconductor device includes an antifuse element. The semiconductor device includes a first well of a first conductivity type disposed in a semiconductor substrate; a first insulating film on the first well; a first conductive film of the first conductivity type on the first insulating film; and an impurity-introduced region of the first conductivity type. The impurity-introduced region of the first conductivity type in the first well is higher in impurity concentration than the first well. The impurity-introduced region includes a first portion that faces toward the first conductive film through the first insulating film.

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract: An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.

Abstract: A semiconductor device and a method for programming the same are provided. The semiconductor device comprises: a semiconductor substrate with an interconnect formed therein; a Through-Silicon Via (TSV) penetrating through the semiconductor substrate; and a programmable device which can be switched between on and off states, the TSV being connected to the interconnect by the programmable device. The present invention is beneficial in improving flexibility of TSV application.

Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.

Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

Abstract: An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

Abstract: An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures.

Abstract: A method for programming an anti-fuse element in which the ratio between current values before and after writing is increased to ensure accuracy in making a judgment about how writing has been performed on the anti-fuse element. The method for programming the anti-fuse element as a transistor includes the steps of applying a prescribed gate voltage to a gate electrode to break down a gate dielectric film, and moving the silicide material of a silicide layer formed on a surface of at least one of a first impurity diffusion region and a second impurity diffusion region, into the gate dielectric film in order to couple the gate electrode with at least the one of the first impurity diffusion region and the second impurity diffusion region electrically through the silicide material.

Abstract: A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state.

Abstract: An antifuse is disclosed which has an electrically-insulating region sandwiched between two electrodes. The electrically-insulating region has a single layer of a non-hydrogenated silicon-rich (i.e. non-stoichiometric) silicon nitride SiNX with a nitrogen content X which is generally in the range of 0<X?1.2, and preferably 0.5?X?1.2. The breakdown voltage VBD for the antifuse can be defined to be as small as a few volts for CMOS applications by controlling the composition and thickness of the SiNX layer. The SiNX layer thickness can also be made sufficiently large so that Poole-Frenkel emission will be the primary electrical conduction mechanism in the antifuse. Different types of electrodes are disclosed including electrodes formed of titanium silicide, aluminum and silicon. Arrays of antifuses can also be formed.

Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

Abstract: A stacked semiconductor device includes a first semiconductor die that has a front side electrically coupled to a substrate pad, the substrate pad is connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first ESDs, and TSVs, and the TSVs are coupled to the first integrated circuit and the first ESDs. A second semiconductor die is stacked above the backside of the first semiconductor die, the second semiconductor die includes a second integrated circuit that is electrically connected to the TSVs and second ESDs, and the second ESDs is electrically disconnected from the TSVs. The TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die.

Abstract: An anti-fuse apparatus includes a substrate of a first conductivity type and a well region of a second conductivity type formed in the substrate. A junction between the well region and the substrate is characterized by a breakdown voltage higher than a predetermined voltage. The apparatus includes a contact region of the second conductivity type within the well region. The apparatus also includes a channel region and a drain region within the substrate. A gate dielectric layer overlies the channel region and the contact region. A first polysilicon gate, the drain region, and the well region are associated with an MOS transistor. The apparatus also includes a second polysilicon gate overlying the gate dielectric layer which overlies the contact region. The contact region is configured to receive a first supply voltage and the second polysilicon gate is configured to receive a second supply voltage.

Abstract: In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM antifuse stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM antifuse stack. Other aspects are provided.

Abstract: An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region.

Abstract: A memory cell is provided that includes a diode and a resistance-switching material layer coupled in series with the diode. The resistance-switching material layer: (a) has a dielectric constant in the range of about 5 to about 27, and (b) includes a material from the family consisting of XvOw, wherein X represents an element from the family consisting of Hf and Zr, and wherein the subscripts v and w have non-zero values that form a stable compound. Other aspects are also provided.

Abstract: Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

Abstract: One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides.

Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Abstract: An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after manufacture of a semiconductor device. An antenna, antifuse-type ROM, and a driver circuit are formed over an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit.

Abstract: A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.

Abstract: A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided.

Abstract: Provided is a semiconductor integrated circuit device including fuse elements for carrying out laser trimming processing, in which a space width between aluminum interconnects of the first layer to be connected to the adjacent fuse elements is set to less than twice of the thickness of the side wall of the metal interlayer insulating film of the first layer, thereby preventing exposure of the SOG layer having hygroscopic property. In addition, side spacers are provided to side surfaces of the aluminum interconnects of the first layer.

Abstract: Methods involve using a memory array having memory cells comprising a diode and an antifuse, in which the antifuse is made smaller and programmed at lower voltage by using an antifuse material having a higher dielectric constant and a higher acceleration factor than those of silicon dioxide, and in which the diode is made of a material having a lower band gap than that of silicon. Such memory arrays can be made to have long operating lifetimes by using the high acceleration factor and lower band gap materials. Antifuse materials having dielectric constants between 5 and 27, for example, hafnium silicon oxynitride or hafnium silicon oxide, are particularly effective. Diode materials with band gaps lower than that of silicon, such as germanium or a silicon-germanium alloy, are particularly effective.

Abstract: A semiconductor device (200) includes: an electrical fuse (100) including: a lower layer interconnect (120) formed on a substrate; a via (130) provided on the lower layer interconnect (120) so as to be connected to the lower layer interconnect (120); and an upper layer interconnect (110) provided on the via (130) so as to be connected to the via (130), the electrical fuse being cut, in a state after being cut, through formation of a flowing-out portion, the flowing-out portion being formed when an electrical conductor forming the upper layer interconnect (110) flows outside the upper layer interconnect (110); and a guard upper layer interconnect (152) (conductive heat-absorbing member) formed in at least the same layer as the upper layer interconnect (110), for absorbing heat generated in the upper layer interconnect (110).

Abstract: According to one embodiment, a resistance-change memory cell array in which a plurality of horizontal electrodes extending horizontally and a plurality of vertical electrodes extending vertically are arranged to configure a cross-point structure includes rectifying insulating films formed in contact with side surfaces of the vertical electrodes in facing regions between the horizontal electrodes and the vertical electrodes, variable resistance films formed in contact with side surfaces of the horizontal electrodes in the facing regions between the horizontal electrodes and the vertical electrodes, and conductive layers formed between the rectifying insulating films and the variable resistance films.

Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor.

Abstract: A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction.