Abstract: An integrated adjustable capacitor device and method for making such a device are provided. The adjustable capacitor includes an underlying electrode, a dielectric cavity, an upper electrode, and an etch cavity for removing sacrificial material from the dielectric cavity. The surface of the device is relatively flat due to epitaxal deposition of epi polysilicon and single crystal silicon. The adjustable capacitor system is capable of undergoing CMOS processes without requiring additional steps of covering the capacitor device to protect it and then removing the covering following the CMOS processes.

Abstract: A ferroelectric device includes a ferroelectric layer and an electrode. The ferroelectric material is made of a perovskite or a layered superlattice material. A superlattice generator metal oxide is deposited as a capping layer between said ferroelectric layer and said electrode to improve the residual polarization capacity of the ferroelectric layer.

Abstract: The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film.

Abstract: A semiconductor device with a transistor having a first impurity region, a second impurity region, and a gate electrode formed on a semiconductor substrate. The semiconductor device also includes a first insulating film covering the transistor, and a capacitor formed on the first insulating film. The capacitor includes a dielectric film formed of either ferroelectric material or high dielectric material, and an upper electrode and a lower electrode positioned to put the dielectric film therebetween. A second insulating film is formed on the capacitor, and a wiring layer is formed on the second insulating film. A nitride film covers the wiring layer and a first silicon oxide film formed on the nitride film includes nitrogen at least at the surface thereof.

Abstract: A silicon controlled rectifier (SCR) serving as an electrostatic discharge (ESD) protection device having a vertical zener junction for triggering breakdown. The SCR includes a p-doped substrate having an n-doped well, spaced-apart p+ and n+ doped regions for cathode connection formed within the n-doped well, and spaced-apart p+ and n+ doped regions for anode connection formed with the p-substrate external to the n-doped well. The SCR further includes a vertical zener junction situated between the anode n+ doped region and the n-well. The vertical zener junction has a p+ doped region sandwiched between two n+ doped regions. The n+ doped region of the vertical zener junction closest to the n-well may extend at least partially within the n-well, or be totally outside of the n-well.

Abstract: An integrated passive component device in which an anodized metal capacitor and a HTD capacitor are fabricated with a protective conductive metal layer disposed between the dielectric layer of the anodized metal capacitor and the dielectric layer of the HTD capacitor. The protective conductive metal layer helps to prevent process chemicals and conditions used to fabricate the dielectric layer of the HTD capacitor from adversely affecting the dielectric layer of the anodized metal capacitor. The anodized metal capacitor and the high temperature deposition capacitor are fabricated on the same substrate using only one masking operation.

Abstract: Implemented are a semiconductor device comprising a trench type capacitor having such a structure that a soft error tolerance is excellent, a contact resistance between an electrode and a metal wiring has a small value, a fringe capacitance on an end is reduced and area penalty is not increased, and a method for manufacturing the semiconductor device. The trench type capacitor is formed to have a bottom face in a BOX layer (2) without penetrating the BOX layer (2). Moreover, an end of the capacitor, that is, each of ends of a first electrode (6), a dielectric film (7) and a second electrode (8) is flattened. An insulating film (16) and a side wall (9) are formed to cover the ends of the first electrode (6), the dielectric film (7) and the second electrode (8). Furthermore, a contact plug (10) for connecting the second electrode (8) to a metal wiring (14a) provided as an upper layer is buried in a region surrounded by the side wall (9).

Abstract: Capacitance for MIM capacitors is increased by connecting another interdigitated pattern at the poly level in parallel with overlying patterns at the metal levels. The poly layout is optimized to maximize intralevel capacitive coupling through sidewall nitride.

Abstract: An integrated circuit capacitor containing a thin film of dielectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract: A semiconductor device includes a capacitor having a pair of electrodes opposite to each other through a dielectric layer, and an element other than the capacitor, both of which are formed on a semiconductor substrate. An ohmic electrode of the element and one of the electrodes of the capacitor are formed of the same metallic material.

Abstract: A thin film capacitor is provided with a thin film protection element to protect the capacitor from damage that can result due to the occurrence of an electrostatic discharge event. The thin film capacitor includes two conductive film portions forming capacitor plates and a dielectric film forming the capacitor dielectric. The protection element may take the form of a thin film diode or a series of thin film diodes connected electrically in parallel with the thin film capacitor. The whole device can be fabricated using a stoichiometric silicon nitride layer to produce the capacitor dielectric and a non-stoichiometric silicon rich silicon nitride layer to provide the diode semiconductor material. One diode is formed by one capacitor plate, the semiconductor layer and an upper diode contact.

Abstract: In a semiconductor device which has capacitors respectively connected to multiple input terminals, and in which the remaining terminals of the capacitors are commonly connected to a sense amplifier, the capacitors and the sense amplifier are formed by utilizing a semiconductor layer on an insulating surface, whereby high-speed, high-precision processing of signals having a large number of bits supplied from the multiple input terminals is realized by a small circuit scale.

Abstract: Conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define capacitors, each including a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the capacitors is electrically connected to a conductive plug and at least a second of the capacitors is not electrically connected to a conductive plug. A second insulating layer is formed on the first insulating layer, on the capacitors and on the first conductive patterns.

Abstract: An integrated circuit capacitor containing a thin film delectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

Abstract: A semiconductor device for preventing process-induced charging damages is disclosed. The semiconductor device comprises a semiconductor layer, at least one transistor comprising a source region, a drain region, a channel region, a gate oxide layer and a gate electrode, at least one parasitic capacitor comprising a conductive layer, a dummy conductive layer constituting a dummy pattern, and a dielectric layer interposed between the conductive layer and the dummy conductive layer, a first conductor connecting the gate electrode and the conductive layer, and a second conductor connecting the semiconductor layer and the dummy conductive layer. Furthermore, the dummy conductive layer can be a floating layer over the semiconductor layer. In such manner, the second conductor set forth is replaced by an interposed dielectric layer.

Abstract: A dummy pattern for use in a chemical mechanical polishing (CMP) process is disposed in a field dummy region within a p− well region, isolated by an isolating insulating film, wherein the p− well region has a potential fixed by a ground electrode. The dummy pattern includes a gate insulating film dummy pattern and a gate electrode dummy pattern, formed in the same layers as a gate insulating film and a gate electrode, respectively, of an NMOS transistor. The gate electrode dummy pattern is connected with a contact plug, which in turn is connected with a power supply electrode (Vcc) interconnection line. Thus, a decoupling condenser, formed of the field dummy region within the p− well, the gate insulating film dummy pattern and the gate electrode dummy pattern by utilizing the dummy patterns for use in the CMP process, is connected in parallel with a primary electronic circuit.

Abstract: To shorten the production process of the semiconductor device having the capacitance element. The pad oxide film (2) and the first polycrystalline silicon layer (3) are used as a stress buffering material at the time of formation of the element separation oxide film. These are not removed and used as the capacitance insulation film and a portion of the upper electrode of the capacitance element. Thereby, the removing process of the pad• polycrystalline silicon layer, and the dummy oxidation and its removing process in the conventional example, can be omitted and the process can be shortened. Further, a problem of the impurity enhanced oxidation at the time of formation of the capacitance insulation film can be solved.

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate on which an integrated circuit is formed, (b) a ground electrode formed on the semiconductor substrate, (c) a bonding wire through which the ground electrode is grounded, the bonding wire having inductance, and (d) a capacitor positioned in series with the inductance, the capacitor and the inductance cooperating with each other to form a resonance circuit at an operating frequency of the integrated circuit. For instance, the capacitor is comprised of a lower electrode formed on or above the semiconductor substrate, an insulating film covering the lower electrode therewith, and an upper electrode formed on the insulating film above the lower electrode. The provided semiconductor device reduces noises and saves power.

Abstract: A production of a capacitor includes the simultaneous production, in at least part of an intertrack insulating layer (3) associated with a given metallization level, on the one hand, of the two electrodes (50, 70) and of the dielectric layer (60) of the capacitor and, on the other hand, of a conducting trench (41) which laterally extends the lower electrode of the capacitor, is electrically isolated from the upper electrode and has a transverse dimension smaller than the transverse dimension of the capacitor, and the production, in the interlevel insulating layer (8) covering the intertrack insulating layer, of two conducting pads (80, 81) which come into contact with the upper electrode of the capacitor and with the conducting trench, respectively.

Abstract: An Metal Insulator Metal (MIM) capacitor having improved performance in a high frequency range. The MIM capacitor comprises: a lower electrode; a second insulating film formed on the lower electrode; a capacitor insulating film formed on a portion of the lower electrode; an upper electrode formed on the capacitor insulating film; a third insulating film formed on the second insulating film and the upper electrode; a first lead electrode which connects to a portion of the lower electrode; a second lead electrode which connects to a portion of the upper electrode. The first lead electrode is continuously formed such that the first electrode surrounds at least three sides of the capacitor insulating film, and the width H of the capacitor insulating film and maximum frequency F satisfy the formula: H<(A/F)½, where, A is a predetermined constant determined depending on a structure and manufacturing process of the MIM capacitor to obtain desired admittance characteristics.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.

Abstract: A semiconductor device including a capacitor element which has a high withstand voltage, a large capacitance, and little parasitic resistance and parasitic capacitance. On interlayer insulating films provided on a semiconductor device, there is formed a lower electrode of a capacitor element coated with an alumina thin film through use of a portion of a first metal layer to be used for forming a first wiring layer. An electrode to constitute a portion of an upper electrode of the capacitor element is formed from a second metal layer so as to come into contact with the alumina thin film provided on the surface of the lower electrode. On the electrode, an upper electrode of the capacitor element is formed through use of a portion of a third metal layer to be used for forming a second wiring layer. Further, an lead electrode connected to the lower electrode is formed through use of a portion of the third metal layer by removal of a portion of the alumina thin film provided on the surface of the lower electrode.

Abstract: An integrated passive device array structure with a value that is programmable during manufacturing. The device structure includes a substantially conductive first layer having a plurality of passive device array elements of the integrated passive device array structure disposed above the substantially conductive first layer. The device further includes an insulating layer formed above the plurality of passive device array elements. One or more vias are selectively formed in the insulating layer. The vias facilitate electrical connections between selected ones of the plurality of passive device array elements with a substantially conductive second layer subsequently deposited above the insulating layer.

Abstract: An integrated Voltage controlled oscillator (VCO) includes varactors and fixed capacitors formed in a “stacked” arrangement. Forming the VCO integrated circuit by “stacking” fixed capacitors upon underlying varactors frees up semiconductor surface area for use by other circuit components or permits the implementation of a smaller integrated circuit package. “Stacking” further permits a decrease in parasitic capacitance associated with interconnections between the fixed capacitors and other components of the VCO.

Abstract: A semiconductor integrated circuit having an MIS (metal-insulator silicon) capacitor. A first capacitor and a second capacitor are connected in series between a substrate terminal and the MIS capacitor. A power supply is connected between the first and second capacitors. This power supply controls the potential between the first and second capacitors to an arbitrary potential to prevent a digital signal transmitted to the substrate from entering to an external circuit connected with the MIS capacitor.

Abstract: A process for forming an isolated thin-film trench capacitor includes forming a first trench in a substrate and filling it with an electrically insulating material. A trench capacitor is formed in the first trench by forming first and second pluralities of conductive plates, such as polycrystalline silicon, separated by a layer of dielectric material. The first plurality of conductive plates are electrically connected together and the second plurality of conductive plates are electrically connected together. The dielectric material isolates the trench capacitor from the remainder of the chip. In one form, the trench capacitor comprises a plurality of second trenches in the electrically insulating material and the plurality of conductive plates are formed in the second trenches. In another form, a second trench is formed in the electrically insulating material and the trench capacitor is formed by interleaving conductive layers separated by dielectric material in the second trench.

Abstract: An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions.

Abstract: A programmable capacitor in an integrated circuit (IC) comprises a conductive line located parallel to an interconnect. When a bias voltage is applied to the conductive line, a parasitic capacitance is created between the interconnect and the conductive line. By properly sizing and locating the conductive line, a desired capacitance can be coupled to the interconnect. A bias control circuit can apply or remove the bias voltage from the conductive line, thereby enabling the capacitance to be coupled or decoupled, respectively, from the interconnect. Because of its simple construction, multiple capacitive structures can be formed around a single interconnect to provide capacitive adjustment capability. By changing the number of conductive lines to which the bias voltage is applied, the total capacitance provided by the multiple capacitive structures can be varied. A feedback loop can be incorporated to provide adjustment during IC operation.

Abstract: An IC module has one or more integrated circuits and a package surrounding them. The IC module is distinguished by one or more additional electronic components being accommodated inside the package, in the immediate vicinity of the integrated circuit.

Abstract: An improved RC network integrated circuit semiconductor device is disclosed which incorporates an improved method for fabrication. The new device and method includes the use of a tantalum nitride layer as the resistive material for the resistor and a protective metal layer formed between the resistive layer and a metal interconnect layer. The capacitor uses a metal electrode as one plate of the capacitor and a heavily doped semiconductor region as the other plate of the capacitor and separated from the one plate of the capacitor by a silicon nitride insulation layer.

Abstract: A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the circuit devices.

Abstract: A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend away from the capacitor dielectric (104). A first conductive structure (302) comprising a material with lower resistivity than the first capacitor plate (102) is electrically coupled to the first set of conductive posts (301). In a preferred embodiment, a second set of conductive posts (501) are electrically coupled to the second capacitor plate (106) and extend away from the capacitor dielectric (102). A second conductive structure (503) is electrically coupled to the second set of conductive posts (501).

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: On a substrate, there are provided a lower electrode, a capacitance insulating film, a passivation insulating film, and a first partial film of an upper electrode to be filled in a second aperture (capacitance determining aperture) formed in the passivation insulating film. The lower electrode, the capacitance insulating film, and the first partial film constitute a capacitance element. The upper electrode has the first partial film which is in contact with the capacitance insulating film and a second partial film which is not in contact with the capacitance insulating film. Since a second electrode wire consisting of a lower-layer film composed of titanium and an upper-layer film composed of an aluminum alloy film is in contact with the second partial film distinct from the first partial film of the upper electrode, titanium or the like encroaching from the second electrode wire can be prevented from diffusing into the capacitance insulating film.

Abstract: An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

Abstract: A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

Abstract: The present invention provides a method for fabricating a capacitor within a semiconductor device comprising the steps of forming openings in an oxide dielectric to reach a lower conductor layer which will serve as a lower conductor plate of the capacitor; depositing capacitor electrode material, such as tungsten to fill the openings to form a capacitor electrode and planarizing the filled openings using chemical/mechanical polish; depositing a selected oxide capacitor dielectric over the capacitor electrodes and patterning the capacitor dielectric with photoresist to leave dielectric covering the area of the capacitor electrodes; stripping away the photoresist; adding an upper conductor layer on top of the capacitor dielectric to serve as the top plate of the capacitor. The above steps may be repeated to form multiple layers of capacitors within the semiconductor device.

Abstract: A method for making metal capacitors for deep submicrometer processes for integrated circuits is described. The method provides metal capacitors with high capacitance per unit area, low voltage coefficients, and excellent capacitance distribution (uniformity) across the substrate. The method involves depositing a first insulating layer on a substrate having completed semiconductor devices. A first metal layer is deposited and patterned to form bottom electrodes and interconnecting metal lines. A thin capacitor dielectric layer is deposited, and a thin second metal or TiN layer is deposited and patterned to form the top electrodes. A thick second insulating layer is deposited and planarized, and an array of via holes are etched to the top electrodes to provide for low-resistance contacts and via holes for the interconnecting metal lines.

Abstract: The integrated circuit is provided with capacitors for smoothing the supply voltage. The capacitors are disposed below the supply interconnects which supply the integrated circuit with the supply voltage. This enables the integrated circuit to be accommodated on a minimal area.

Abstract: An integrated, interdigitated capacitor incorporates all layers of an I.C. fabrication process into its design to produce a multi-layer high-capacitance device. For example, a "two-metal, two-poly" CMOS fabrication process is used to produce a capacitor having five interdigitated conductive plates, which when interconnected produce a total capacitance at least twice as great as a conventional two-plate capacitor of the same area, while requiring no additional I.C. processing steps. The invention's conductive plates and interconnections are arranged so that interconnection traces stay within strict design limits intended to insure reliable connections, while keeping the area required for the interconnections small.

Abstract: A semiconductor device is provided with a multilayered interconnection and a capacitor dielectric element, in which the transistor in the device has a non-degraded characteristics and the degradation of the capacitor dielectric element is suppressed. The semiconductor device has wiring layers connecting to one another through contact holes in insulating layers. One of the insulating layers is formed so as to cover at least a part of the area above the transistor and so as not to cover the area above the capacitor dielectric element. Hydrogen generated by heat-treating the insulating layer is supplied to the transistor to recover the damage in it, while hydrogen is suppressed from arriving at the capacitor element so that the capacitor dielectric element does not degrade.

Abstract: The present invention provides, for use in an integrated circuit structure having a prior level that includes a foundation dielectric formed over a conductive polycrystalline material, a capacitor comprising first and second electrodes having a capacitor dielectric formed therebetween. The first electrode is formed immediately over the prior level and extends beyond a common area of the first and second electrodes and connects the capacitor to the prior level outside of the common area. The capacitor is free of a direct electrical contact with the prior level; that is, the capacitor is not connected to the prior level by a window or other interconnect structure that extends directly from the capacitor itself within the common area. Electrical connection of the capacitor to the prior level is made outside the common area of the capacitor.

Abstract: In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the sides of this gap and the opposing plate at least compensates, if not overcompensates, for the missing conductive material that would otherwise fill the gap and add to parallel capacitance. As a result, the capacitance of a storage device can be increased without taking up more die area. Alternatively, the size of a capacitor can be reduced with no decrease in capacitance. Various gap configurations and methods for providing them are also within the scope of the current invention.

Abstract: A semiconductor device includes a semiconductor substrate having a major surface; a first interlayer insulating film formed on the semiconductor substrate and having an opening defined therein so as to open at the major surface of the semiconductor substrate; a connecting member made of Si as a principal component and embedded in the opening; a lower capacitor electrode connected electrically with the major surface of the semiconductor substrate through the connecting member; a capacitor dielectric film formed on the lower capacitor electrode; an upper capacitor electrode formed on the capacitor dielectric film; and a second interlayer insulating film formed on the capacitor upper electrode. The lower capacitor electrode referred to above is made of a principal component selected from the group consisting of ruthenium and iridium and contains oxygen in a quantity of 0.001 to 0.1% by atom and/or at least one impurity element in a quantity of 0.1 to 5% by atom.

Abstract: For contacting a non-linear switching element (10), for example for use in a display device (1), a metallic layer (14) is provided on a layer of non-linear resistive material by means of a low-energetic deposition technique. This layer may function as a contact but also as a protective layer when a contact metallization (15) is provided at a later stage.

Abstract: An iridium layer (16) is formed on an inter-layer insulation film (12) and in an opening (14). The iridium layer (16) is constituted with a part to be a lower electrode (16a) of a capacitor and a part to be a wiring (16b) for coming into contact with a drain zone (6). On part of the lower electrode (16a) of the iridium layer (16) is formed a ferroelectric layer (18) made of PZT on which is further formed an iridium layer (20) as an upper electrode. Since the melting point of iridium is higher than that of aluminum, there is no possibility of iridium melting even if heat treatment is carried out after forming the iridium layer (16). Since reactivity between iridium and silicon is low, unnecessary silicon compound is not produced on the interface to provide favorable contact.