Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first doped portion and the second doped portion; a first barrier, which directly contacts the first doped portion; a second barrier, which directly contacts the second doped portion; a dielectric member, which is positioned between the first barrier and the second barrier and directly contacts each of the first barrier and the second barrier; a third barrier, which directly contacts the first doped portion; and a device component, wherein a portion of the device component is positioned between the dielectric member and the third barrier.

Abstract: A semiconductor device includes a drift region of a first conductivity type, a channel forming region of a second conductivity type that is selectively provided in a first main surface of the drift region, a first main electrode region of the first conductivity type that is selectively provided in an upper part of the channel forming region, a second main electrode region of the second conductivity type that is provided in a second main surface of the drift region, and a high-concentration region of the first conductivity type that is provided in a portion of the drift region below the channel forming region so as to be separated from the channel forming region. The high-concentration region has a higher impurity concentration than the drift region and the total amount of first-conductivity-type impurities in the high-concentration region is equal to or less than 2.0×1012 cm?2.

Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.

Abstract: Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed.

Abstract: A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.

Abstract: A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.

Abstract: A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K3 to form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K4 (phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.

Abstract: The high voltage integrated circuit is disclosed. The high voltage integrated circuit comprises a low voltage control circuit, a floating circuit, a P substrate, a deep N well disposed in the substrate and a plurality of P wells disposed in the P substrate. The P wells and deep N well serve as the isolation structures. The low voltage control circuit is located outside the deep N well and the floating circuit is located inside the deep N well. The deep N well forms a high voltage junction barrier for isolating the control circuit from the floating circuit.

Abstract: A depletion transistor includes a source region and a drain region of a first conductivity type, a channel region of the first conductivity type arranged between the source region and the drain region and a first gate electrode arranged adjacent the channel region and dielectrically insulated from the channel region by a gate dielectric. The depletion transistor further includes a first discharge region of a second conductivity type arranged adjacent the gate dielectric and electrically coupled to a terminal for a reference potential. The depletion transistor can be included in a charging circuit.

Abstract: An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second conductivity type opposite the first conductivity type. The depletion region includes a first portion directly over the deep well region and a second portion directly under the deep well region. An integrated circuit device is directly over the depletion region.

Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.

Abstract: A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to the semiconductor substrate is provided in the epitaxial layer with the low concentration impurity. And the semiconductor device further includes a high concentration impurity region of the first type conductivity having the same type conductivity as the type of the semiconductor substrate formed in at least the epitaxial layer with the low concentration impurity along an inner wall of the trench and coupled to the semiconductor substrate with the high concentration impurity of a first type conductivity, and contacts formed on the high concentration impurity region of the first type conductivity.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.

Abstract: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.

Abstract: Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential.

Abstract: A semiconductor photodetector 10 has a first semiconductor substrate 1 that is of a first conductive type and a low resistivity and has a (111) front surface, and a second semiconductor substrate 2 that is of the first conductive type and a high resistivity, has a (100) front surface, and is adhered onto first semiconductor substrate 1. A semiconductor region 3 of a second conductive type is formed on the front surface side of second semiconductor substrate 2. A region of a periphery of semiconductor region 3 is etched until first semiconductor substrate 1 is exposed. A first electrode 1e and a second electrode 2e are electrically connected to the exposed front surface of first semiconductor substrate 1 and to semiconductor region 3, respectively.

Abstract: A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to the semiconductor substrate is provided in the epitaxial layer with the low concentration impurity. And the semiconductor device further includes a high concentration impurity region of the first type conductivity having the same type conductivity as the type of the semiconductor substrate formed in at least the epitaxial layer with the low concentration impurity along an inner wall of the trench and coupled to the semiconductor substrate with the high concentration impurity of a first type conductivity, and contacts formed on the high concentration impurity region of the first type conductivity.

Abstract: An apparatus that reduces parasitic capacitance in a MEMS device includes a dielectric layer on the surface of a silicon-on-insulator (SOI) substrate, a conductor embedded in the substrate and disposed between the dielectric layer and a buried oxide layer, and surface conductors on the dielectric layer and coupled to ends of the embedded conductor. A boundary region surrounds the embedded conductor and separates an inner region and an outer region of substrate, providing a p-n junction between the boundary region and the outer region of SOI substrate which is reverse biased to electrically isolate the inner region from the outer region of SOI substrate. An amplifier has an input connected to one end of the embedded conductor and an output connected to the inner region of the substrate. The amplifier senses a voltage at the input and produces a voltage that approximates the voltage at the output.

Abstract: In a semiconductor device of the present invention, an N type epitaxial layer is formed on a P type single crystal silicon substrate. The substrate and the epitaxial layer are partitioned into a plurality of element formation regions by isolation regions. Each of the isolation regions is formed of a P type buried diffusion layer and a P type diffusion layer coupled thereto. The P type buried diffusion layer is joined to N type buried diffusion layers on both sides thereof to form PN junction regions. On the other hand, the P type diffusion layer is joined to N type diffusion layers on both sides thereof to form PN junction regions. This structure suppresses extension of widthwise diffusion of the P type buried diffusion layer and the P type diffusion layer, thus making it possible to reduce the device size.

Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.

Abstract: A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.

Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

Abstract: A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor device, without occupying an extra layout area.

Abstract: An island-shaped floating conducting region is provided in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, or peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer. The floating conducting region has floating potential and blocks a depletion layer extending from the wire on the nitride film to the substrate. It is therefore possible to prevent leakage of a high frequency signal to the other side through the depletion layer extending from the wire on the substrate to the substrate in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, peripheral impurity region), or between the adjacent wire on the nitride film and gate metal layer.

Abstract: A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type region forming a channel therein. A floating gate is disposed above and insulated from the channel. A control gate is disposed above and insulated from the floating gate. An isolation trench disposed in the p-type region and surrounding the source and drain regions, the isolation trench extending down into the n-type region. The substrate, the n-type region and the p-type region each biased such that the p-type region is fully depleted.

Abstract: A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped region is limited to a predetermined value. When the ratio exceeds the predetermined value, a dummy doped region is added to prevent the device from being damaged during a plasma process.

Abstract: A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopant of the second conductivity type; and performing an anneal step so that regions of the second conductivity type diffused from neighboring recesses join. A first series of recesses is formed from the upper surface and a second series of recesses is formed from the lower surface. The recesses have a substantially rectangular section, the large dimension of which is perpendicular to the alignment of the recesses and a depth smaller than or equal to the half-thickness of the substrate.

Abstract: A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p-type deep guard ring and a heavily doped p-type shallow impurity region are formed in said lightly doped semiconductor layer in such a manner that a diode has a major p-n junction between the heavily doped n-type impurity region and the heavily doped p-type shallow impurity region and other p-n junction between the lightly doped n-type semiconductor layer and the lightly doped p-type guard ring, wherein the other p-n junction is wider in area than the major p-n junction so that the breakdown voltage is adjustable without increase of parasitic capacitance dominated by the other p-n junction.

Abstract: A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a portion of the gate electrode after the gate electrode has been formed on the surface of a semiconductor substrate. In a preferred embodiment, the channel region is formed by the angled ion implantation of dopant atoms using an edge of the gate electrode as a doping mask. The high-voltage transistor of the invention further includes a drain region that is spaced apart from the channel region by a portion of a well region and by an isolation region residing in the semiconductor substrate. By utilizing the process of the invention to fabricate the high-voltage transistor, the transistor can be integrated into an existing CMOS device with minimal allocation of additional substrate surface area.

Abstract: A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type having a surface. A plurality of separate wells of a second conductivity type with a more highly doped edge layer of the second conductivity type are disposed at the surface of the substrate and are isolated from one another by pn junctions. At least one of the wells is completely surrounded by an insulating well of the first conductivity type. The doping of the insulating well is higher than that of the substrate. A method for fabricating a semiconductor component is also provided.

Abstract: A semiconductor device comprises:a semiconductor substrate; a plurality of active regions for forming semiconductor elements, the active regions being formed on the semiconductor substrate; a device isolation region for separating the plural active regions from each other, the device isolation region including a trench region filled with an insulating film and a pseudo active region formed adjacent to the trench region; a wiring layer formed above the semiconductor substrate; and a pseudo conductive film formed on the device isolation region, wherein, if the pseudo conductive film is partially or entirely located under the wiring layer, the pseudo conductive film is formed only on the trench region.

Abstract: A protection circuit in a semiconductor integrated circuit having a master slice I/O circuit comprises an internal circuit, a pad, and a desired number of protection elements connected in parallel between the internal circuit and the pad. Each protection element includes a P-channel MOS transistor which outputs a first power supply voltage level signal on the basis of an output signal of the internal circuit, a N-channel MOS transistor which outputs a second power supply voltage level signal on the basis of the output signal of the internal circuit, a resistor connected between a signal line connected to the pad and an output terminal of the P-channel MOS transistor, and a resistor connected between the signal line and an output terminal of the N-channel MOS transistor.

Abstract: A low junction capacitance semiconductor structure and an I/O buffer are disclosed. The semiconductor structure includes a MOS transistor and a lightly doped region. The MOS transistor is formed in a semiconductor substrate and has a gate and source and drain region formed aside the gate. The lightly doped region has a conductivity the same as the source and drain regions, and is formed in the drain region and has a depth larger than the source and drain regions. Further, the lightly doped region can be achieved by CMOS-compatible processes, and the formed devices in the well can be isolated from the semiconductor substrate using deeply doped regions which are usually adopted in advanced technologies.

Abstract: A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or “offset” towards a shallower part.

Abstract: The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film.

Abstract: A protection circuit in a semiconductor integrated circuit having a master slice I/O circuit comprises an internal circuit, a pad, and a desired number of protection elements connected in parallel between the internal circuit and the pad. Each protection element includes a P-channel MOS transistor which outputs a first power supply voltage level signal on the basis of an output signal of the internal circuit, a N-channel MOS transistor which outputs a second power supply voltage level signal on the basis of the output signal of the internal circuit, a resistor connected between a signal line connected to the pad and an output terminal of the P-channel MOS transistor, and a resistor connected between the signal line and an output terminal of the N-channel MOS transistor.

Abstract: A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.

Abstract: A high breakdown-voltage diode is provided, which has a decreased chip area and a low electric resistance between anode and cathode regions after the breakdown phenomenon takes place. A semiconductor layer of a first conductivity type is vertically isolated by a first isolation dielectric and laterally isolated by a second isolation dielectric from outside. A first diffusion region of a second conductivity type is formed in a surface area of the semiconductor layer, thereby forming a first p-n junction. A second diffusion region of the first conductivity type is formed in the surface area to be apart from the first diffusion region. A third diffusion region of the second conductivity type is formed in the surface area between the first and second diffusion regions, thereby forming a second p-n junction. The third diffusion region is electrically connected to the first diffusion region.

Abstract: Ba--Sr--Ti-oxide dielectric material, with at least 60 atomic percent of the total content of the oxide being Ti, can have relatively high dielectric constant K (>40 at 20.degree. C.) and relatively low second order voltage coefficient a.sub.2 of the dielectric constant (a.sub.2 <100 PPM V.sup.2 at 20.degree. C.). In preferred embodiments the dielectric material has nominal composition (BA.sub.x Sr.sub.y Ti.sub.1--x--y)-oxide, with 1--x--y in the range 0.65-0.90, with both x and y greater than or equal to 0.05. Ba, Sr and Ti together typically comprise at least 99 atomic percent of the total metal content of the dielectric material.

Abstract: A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36).

Abstract: Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated along a lower semiconductor interface between a semiconductive substrate and an overlying lower semiconductive layer. An upper buried region of a selected conductivity type is situated along an upper semiconductor interface between the lower semiconductive layer and an overlying upper semiconductive layer. Another upper buried region of opposite conductivity type to the first-mentioned upper buried region is preferably situated along the upper semiconductor interface. The upper semiconductive layer contains P-type and N-type device regions in which transistor zones are situated. The semiconductor structure is configured so that at least one of each of the P-type and N-type device regions is electrically isolated from the substrate.

Abstract: A bipolar semiconductor integrated circuit has a pnp transistor through which a DC power is supplied from an external DC power to various elements of the bipolar IC and a constant current circuit for turning the pnp transistor on and regulating the base current of the pnp transistor to a constant level causing operation in the saturation range of the pnp transistor.

Abstract: A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N type impurities are introduced into the substrate through the first masking layer, so as to form N+ doped regions. A second masking layer is then selectively formed on the first masking layer, such that the second masking layer masks the first aperture, but exposes a second portion of the first masking layer that both includes and surrounds the second aperture. Boron impurities are then introduced through the exposed second aperture of the first masking layer, to a P+ doping concentration.

Abstract: A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration impurity region 8 of the second conductivity type and the low concentration impurity layer 2 of a first conductivity type can be made moderate to relax the electric field, which leads to provision of higher breakdown voltage of the semiconductor device. Further, the depth of impurity diffusion of the low concentration impurity region 6 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type is made at least three times the depth of impurity diffusion of the high concentration impurity region 8 of the second conductivity type from the main surface of the low concentration impurity layer 2 of the first conductivity type.

Abstract: A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42).

Abstract: A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resistance semiconductor layer, an element region formed in the high resistance semiconductor layer isolated by the isolation region in a lateral direction, a first low resistance region of a first conductivity type formed in a central surface portion of the element region, and a second low resistance region of a second conductivity type formed in a peripheral surface portion of the element region. Dose of impurities in the element region is set such that a portion of the element region between the first low resistance region and the second low resistance region is completely depleted when voltage is applied between the first and second low resistance regions.

Abstract: A method of fabrication of an semiconductor device comprises applying an impurity of a predetermined polarity to a silicon substrate; forming a well by applying an impurity of an opposite polarity to a region in the silicon substrate; forming a first masking layer on the surface of the substrate; providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first regions selected in the substrate and the well forming a second masking layer on the surface of the substrate; implanting dopant ions of a second polarity through a second mask in other regions selected in the well and the substrate; removal of the second masking layer; formation of field oxide structures over the first and second regions; forming gate oxide layers above the exposed portions of the first and second central regions; and formation of conductive gate structures over the gate oxide layers.

Abstract: A bias structure for an integrated circuit including first and second transistors having emitter terminals coupled respectively to the supply and to a terminal of a resistor whose potential, under certain operating conditions of the circuit, exceeds the supply voltage; base terminals connected to each other and to a current source; and collector terminals connected electrically (12) to an epitaxial tub housing the resistor. A resistor is preferably provided between the two collectors, so that, when the potential of the terminal of the resistor exceeds the supply voltage, the second transistor saturates and maintains the epitaxial tub of the resistor at a potential close to that of the resistor terminal, thus preventing the parasitic diode formed between the resistor and the epitaxial tub from being switched on.

Abstract: A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor region and selectively formed on a surface portion of the first semiconductor region, a third semiconductor region having an impurity concentration lower than that of the second semiconductor region and formed on the surface portion of the first semiconductor region so as to be adjacent to or near the second semiconductor region and a fourth semiconductor region of a second conductivity type having an impurity concentration higher than that of the first semiconductor region and formed on the surface portion of the first semiconductor region so as to be outside the third semiconductor region.