Abstract: A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a silicon-on-insulator (SOI) substrate having an insulator layer between an active layer and a base layer. A semiconductor device and a shallow trench isolation (SIT) structure are disposed on a frontside of the SOI substrate. A semiconductor core structure continuously surrounds the semiconductor device and extends through the STI structure and towards a backside of the SOI substrate. A first insulator liner portion and a second insulator liner portion surround a first outermost sidewall and a second outermost sidewall of the semiconductor core structure. The first and second insulator liner portions respectively have a first protrusion and a second protrusion. The first and second protrusions are arranged between the STI structure and the insulator layer of the SOI substrate.

Abstract: A vertical transient voltage suppression device includes a semiconductor substrate having a first conductivity type, a first doped well having a second conductivity type, a first heavily-doped area having the first conductivity type, a second heavily-doped area having the first conductivity type, and a diode. The first doped well is arranged in the semiconductor substrate and spaced from the bottom of the semiconductor substrate, and the first doped well is floating. The first heavily-doped area is arranged in the first doped well. The second heavily-doped area is arranged in the semiconductor substrate. The diode is arranged in the semiconductor substrate and electrically connected to the second heavily-doped area through a conductive trace.

Abstract: An active matrix substrate 1 includes a plurality of detection circuitry. The detection circuitry includes a photoelectric conversion layer 15, a pair of a first electrode 14a and a second electrode 14b, a protection film 106, and a bias line 16. The protection film 106 covers a side end part of the photoelectric conversion layer 15, and overlaps with at least a part of the second electrode 14b. The bias line 16 is provided on an outer side of the photoelectric conversion layer 15. An electrode portion of the second electrode 14b that overlaps with the bias line 16 has at least one electrode opening 141h. The bias line 16 is in contact with the electrode portion of the second electrode 14b on an outer side of the photoelectric conversion layer 15, and is in contact with the protection film 106 in the electrode opening 141h.

Abstract: A semiconductor structure includes a semiconductor substrate, a buried layer, a pair of first well regions, a second well region, a body doped region, and a first heavily doped region. The semiconductor substrate has a first conductivity type. The buried layer is disposed on the semiconductor substrate. The first well regions having the second conductivity type are disposed on the buried layer. The second well region having the first conductivity type is disposed between the first well regions. The body doped region having the first conductivity type is disposed in the second well region. The first heavily doped region having the first conductivity type is disposed in the body doped region. From a top view, the first heavily doped region and the first well regions extend in a first direction, and the first heavily doped region extends beyond the opposite edges of the first well regions.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node. An emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor. A gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor. Other embodiments are also described.

Abstract: An active matrix substrate includes a substrate 31; gate lines arranged on the substrate 31 and extend in a first direction; source lines Si arranged on the substrate 31 and extend in a second direction that is different from the first direction; transistors 2 arranged in correspondence to points of intersection between the gate lines and the source lines, respectively, and are connected with the gate lines and the source lines; and an insulating layer. At least either the gate lines and the source lines are connected with electrodes of the transistors via contact holes in the insulating layer, and are formed to satisfy at least either i) having a greater film thickness or ii) being formed with a material having a smaller specific resistance, as compared with the electrodes of the transistors to which the lines are connected via the contact holes in the insulating layer.

Abstract: A TFT substrate and a manufacturing method thereof are provided. The TFT substrate includes a plurality of vias formed in a second insulation layer that is formed on a second metal layer that forms peripheral signal wiring traces of the TFT substrate so as to line up in an extension direction of each of the peripheral signal wiring traces and a third metal layer that is formed on the second insulation layer at a location corresponding to each of the peripheral signal wiring traces such that the third metal layer is connected, through the vias, with each of the peripheral signal wiring traces to thereby reduce the electrical resistance of each of the peripheral signal wiring traces and thus lowering down power consumption of control ICs and improving capability of the TFT substrate for resisting electrostatic discharge.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, and first and second electrodes on the layer. A first region of the first type is between the layer and the first electrode and contacting the first electrode. A second region of a second conductivity type is between the layer and the second electrode. A third region of the second type is connected to the second electrode, between the first and second regions, and between the layer and the second electrode. A fourth region of the first type is between the second region and the second electrode and contacting the second electrode. A fifth region of the second type is between the layer and the second region and has an impurity concentration greater than the second region and the third region. A sixth region of the first type is between the second region and the third region.

Abstract: According to one embodiment, a display element includes a plurality of scanning lines and a plurality of signal lines orthogonal to the plurality of scanning lines. A pixel of the display element includes sub-pixels of a plurality of colors to be respectively formed in the regions surrounded by the scanning lines and the signal lines. The size of a sub-pixel of a predetermined color among the plurality of colors is larger than the sizes of the sub-pixels of the other colors. Switching elements of the display element are connected to the scanning lines and the signal lines and drive the sub-pixels, respectively, and are formed into different shapes corresponding to the sub-pixels with different sizes.

Abstract: According to one embodiment, a display element includes a plurality of scanning lines and a plurality of signal lines orthogonal to the plurality of scanning lines. A pixel of the display element includes sub-pixels of a plurality of colors to be respectively formed in the regions surrounded by the scanning lines and the signal lines. The size of a sub-pixel of a predetermined color among the plurality of colors is larger than the sizes of the sub-pixels of the other colors. Switching elements of the display element are connected to the scanning lines and the signal lines and drive the sub-pixels, respectively, and are formed into different shapes corresponding to the sub-pixels with different sizes.

Abstract: The present examples relate to a semiconductor chip having a level shifter with an electrostatic discharge (ESD) protection circuit and a device applying to multiple power supply lines with high and low power inputs to protect the level shifter from the static ESD stress. More particularly, the present examples relate to using a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device itself.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.

Abstract: A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via a first blade in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a second blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor.

Abstract: A semiconductor component includes an auxiliary semiconductor device configured to emit radiation. The semiconductor component further includes a semiconductor device. An electrical coupling and an optical coupling between the auxiliary semiconductor device and the semiconductor device are configured to trigger emission of radiation by the auxiliary semiconductor device and to trigger avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device. The semiconductor device includes a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer.

Abstract: A semiconductor structure includes a P well formed on a P type substrate; a first N type electrode area formed on a central region of the P well; a first insulating area formed on the P well and surrounding the first N type electrode area; a second N type electrode area formed on the P well and surrounding the first insulating area; a second insulating area formed on the P well and surrounding the second N type electrode area; and a P type electrode area formed on the P well and surrounding the second insulating area; wherein periphery outlines of the first N type electrode area and the second N type electrode area are both 8K sided polygons or circles, and K is a positive integer.

Abstract: According to one embodiment, a semiconductor device includes a switching element and a diode provided on a substrate. The switching element includes a first semiconductor layer, a drain region, a source region, a channel region, a gate insulating film, and a gate electrode. The diode includes a second semiconductor layer, an anode region, and a cathode region.

Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a semiconductor substrate, at least one deep n-well in the semiconductor substrate, at least one p-channel metal-oxide-semiconductor transistor in the deep n-well, at least one n-channel metal-oxide-semiconductor transistor outside of the deep n-well, an first interconnect structure, and a protection component. Both of the p-channel metal-oxide-semiconductor transistor and the n-channel metal-oxide-semiconductor transistor are disposed in the semiconductor substrate, and are electrically coupled by the first interconnect structure. The protection component is disposed in the semiconductor substrate, wherein the protection component is electrically coupled to the deep n-well.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer and a buried insulator layer disposed between the bulk substrate layer and the active semiconductor layer. A trench is formed through the SOI substrate to expose the bulk substrate layer. A doped well is formed in an upper region of the bulk substrate layer adjacent trench. The semiconductor device further includes a first doped region different from the doped well that is formed in the trench.

Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.

Abstract: An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp.

Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.

Abstract: A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

Abstract: A semiconductor device includes a control section, a first arm, and a second arm; and has an H-bridge circuit to supply an input current supplied from a power source to an output terminal as a reversible electric current on the basis of a control signal outputted from the control section and a reverse-connection-time backflow prevention circuit to prevent an electric current in a direction opposite to the direction of the input current from being supplied to the H-bridge circuit. The first arm is formed over a first island. The second arm is formed over a second island. The control section and the reverse-connection-time backflow prevention circuit are formed over a third island.

Abstract: An electrostatic discharge (ESD) protection structure comprises a high voltage P type implanted region disposed underneath an N+ region. The high voltage P type implanted region and the N+ region form a reverse diode or a Zener diode depending on different doping densities. The ESD protection structure further comprises a plurality of P+ and N+ regions. The high voltage P type implanted region and the P+ and N+ regions form a semiconductor device having a breakdown characteristic. In one embodiment, the semiconductor device may be a bipolar PNP transistor. The bipolar PNP transistor and a Zener diode in series connection form an ESD protection circuit. In another embodiment, the semiconductor device may be a Silicon-Controlled Rectifier (SCR), which is series-connected with a reverse diode. Both embodiments provide a reliable ESD protection.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material.

Abstract: A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.

Abstract: A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.

Abstract: A diode includes a first region having a first conductive type impurity and formed in a first well having the first conductive type impurity, a second region formed in the first well and having a second conductive type impurity, and a semiconductor pattern disposed above the first well and including a first portion having the first conductive type impurity and a second portion having the second conductive type impurity. The first region and the first portion are coupled with an anode, and the second region and the second portion are coupled with a cathode.

Abstract: Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.

Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

Abstract: A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.

Abstract: A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage.

Abstract: A semiconductor device includes an n-type first doped region for receiving an external voltage, an n-type second doped region and a p-type third doped regions all formed in a p-type substrate, and is configured to have a first threshold voltage for forward conduction between the first and second doped regions, and a second threshold voltage for forward conduction between the first and third doped regions. A current is drained by flowing through the first doped region, the substrate and the second doped region if the external voltage is greater than the first threshold voltage or by flowing through the third doped region, the substrate and the first doped region if the external voltage is less than the second threshold voltage.

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Abstract: A protective structure may include: a semiconductor substrate having a doping of a first conductivity type; a semiconductor layer having a doping of a second conductivity type arranged at a surface of the semiconductor substrate; a buried layer having a doping of the second conductivity type arranged in a first region of the semiconductor layer and at the junction between the semiconductor layer and the semiconductor substrate; a first dopant zone having a doping of the first conductivity type arranged in the first region of the semiconductor layer above the buried layer; a second dopant zone having a doping of the second conductivity type arranged in a second region of the semiconductor layer; an electrical insulation arranged between the first region and the second region of the semiconductor layer; and a common connection device for the first dopant zone and the second dopant zone.

Abstract: A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract: A semiconductor device has a semiconductor chip, an internal circuit region arranged on an inner side of the semiconductor chip, and a bonding pad region arranged adjacently to the internal circuit region. A diode-type ESD protection circuit is formed of a junction between a first conductivity type diffusion layer for fixing a substrate potential of the semiconductor chip and a pair of second conductivity type diffusion layers arranged on an inner side of the first conductivity type diffusion layer. The first conductivity type diffusion layer is arranged on an entire peripheral region or a part of the peripheral region of the semiconductor chip with the peripheral region being outside of the internal circuit region and the bonding pad region. One of the pair of second conductivity type diffusion layers comprising a diffusion layer for breakdown adjustment at a junction portion with the first conductivity type diffusion layer.

Abstract: A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an isolation region when impurities are thermally diffused in a semiconductor substrate to form the isolation region. Boron ions (B+) are implanted into an epitaxial layer through a third opening K3 to form a P-type impurity region, using a third photoresist as a mask. Then a fourth photoresist is formed on a silicon oxide film to have fourth openings K4 (phosphorus ion implantation regions) that partially overlap the P-type impurity region. Phosphorus ions (P+) are implanted into the surface of the epitaxial layer in etched-off regions using the fourth photoresist as a mask to form N-type impurity regions that are adjacent the P-type impurity region. After that, a P-type upper isolation region is formed in the epitaxial layer by thermal diffusion so that the upper isolation region and a lower isolation region are combined together to make an isolation region.

Abstract: Provided is a metal oxide semiconductor device, including a substrate, a gate, a first-type first heavily doped region, a first-type drift region, a second-type first heavily doped region, a contact, a first electrode, and a second electrode. The gate is disposed on the substrate. The first-type first heavily doped region is disposed in the substrate at a side of the gate. The first-type drift region is disposed in the substrate at another side of the gate. The second-type first heavily doped region is disposed in the first-type drift region. The contact is electrically connected to the second-type first heavily doped region. The contact is the closest contact to the gate on the first-type drift region. The first electrode is electrically connected to the contact, and the second electrode is electrically connected to the first-type first heavily doped region and the gate.

Abstract: In a method for producing an electronic component, a substrate is doped by introducing doping atoms. In the doped substrate, at least one connection region of the electronic component is formed by doping with doping atoms. Furthermore, at least one additional doped region is formed at least below the at least one connection region by doping with doping atoms. Furthermore, at least one well region is formed in the substrate by doping with doping atoms in such a way that the well region doping is blocked at least below the at least one additional doped region.

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract: A high voltage isolation protection device for low voltage communication interface systems in mixed-signal high voltage electronic circuit is disclosed. According to one aspect, the protection device includes a semiconductor structure configured to provide isolation between low voltage terminals and protection from transient events. The protection device includes a thyristor having an anode, a cathode, and a gate, and a thyristor cathode-gate control region that is built into the protection device. The protection device is configured to provide multiple built-in path-up to power-high terminals and path-down to power-low terminals at different voltage levels. The protection device also includes independently built-in discharge paths to the common substrate that is connected to a different power-low voltage reference. The conduction paths may be built into a single structure with dual isolation regions.

Abstract: Devices and methods are provided, wherein a diode string is provided in a well and the well is biased with an intermediate voltage between voltages applied to terminals of the diode string.

Abstract: A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided.

Abstract: A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling.

Abstract: A first protection circuit includes a first diode and a first transistor. The anode of the first diode is connected to a terminal to be protected. The first transistor is configured as an N-channel MOSFET, and arranged such that the first terminal of the conduction channel thereof is connected to the cathode of the first diode, and the second terminal of the conduction channel thereof, and the gate and the back gate thereof are connected to a fixed voltage terminal. The first transistor is configured as a floating MOSFET formed within an N-type well formed in a P-type semiconductor substrate. The first diode is formed in the shared N-type well in which the first transistor is formed. The cathode of the first diode and the first terminal of the conduction channel of the first transistor are connected to the N-type well.

Abstract: A FinFET diode and method of fabrication are disclosed. In one embodiment, the diode comprises, a semiconductor substrate, an insulator layer disposed on the semiconductor substrate, a first silicon layer disposed on the insulator layer, a plurality of fins formed in a diode portion of the first silicon layer. A region of the first silicon layer is disposed adjacent to each of the plurality of fins. A second silicon layer is disposed on the plurality of fins formed in the diode portion of the first silicon layer. A gate ring is disposed on the first silicon layer. The gate ring is arranged in a closed shape, and encloses a portion of the plurality of fins formed in the diode portion of the first silicon layer.