Abstract: Techniques for wafer level integration of embedded cooling structures for integrated circuit devices are provided. In one embodiment, a method includes forming channel structures on a first surface of a silicon first wafer, wherein the channel structures respectively include radial channels that extend from central fluid distribution areas, and wherein integrated circuits are formed on a second surface of the silicon first wafer that opposes the first surface. The method can further include bonding a manifold wafer to the first surface of the silicon wafer such that inlet openings formed through the manifold wafer respectively connect to the central fluid distribution areas, thereby enclosing the radial channels and forming a bonded structure.

Abstract: An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided.

Abstract: A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of semiconductor substrate, the via opening exposing a surface of a metal landing structure. A conductive layer is deposited over the backside of semiconductor substrate, sidewalls of the via opening, and exposed surface of the metal landing structure. The conductive layer is coated with a polymer material, filling the via opening. The polymer material is developed to remove the polymer material from the backside of semiconductor substrate, leaving the via opening filled with undeveloped polymer material. A planar backside surface of semiconductor substrate is formed by removing the conductive layer.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first integrated circuit die, a second integrated circuit die coupled to the first integrated circuit die, and a through-via coupled between a first conductive feature of the first integrated circuit die and second conductive feature of the second integrated circuit die. A conductive shield is disposed around a portion of the through-via.

Abstract: A semiconductor device having a protection layer wrapping around a conductive structure is provided. The semiconductor device comprises an image sensor device layer, an interconnect layer over the image sensor device layer, a first bonding layer over the interconnect layer, a second bonding layer bonded with the first bonding layer, a substrate over the second bonding layer, and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer. The conductive via comprises a protection layer and a conductive material. The protection layer is peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer. The protection layer covers a sidewall cut formed at an interface of the second bonding layer and the first bonding layer. The conductive material is peripherally enclosed by the protection layer.

Abstract: A liquid crystal display base includes a liquid crystal module, both a power circuit and a integration circuit, a electric device mounted on the power circuit. The liquid crystal module includes a TFT array substrate and a color filter substrate mounted on the TFT array substrate. The power circuit board mounted on the TFT array substrate. The TFT array substrate has a first surface and a second surface opposite to the first surface, a plurality of through holes extend through the first surface and the second surface, each through hole has equal inner diameter from the first surface to the second surface. the TFT array substrate 11 is made of glass, sapphire, ceramic, a plurality of conductive layers are in the plurality of through holes, both the electric device, the integration circuit and the power circuit board are coupled with the liquid crystal module.

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion.

Abstract: A wafer via solder filling device includes a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air outlet for exhausting air from the accommodation space; a fixing unit for fixing the wafer having a via formed in one surface in the accommodation space to seal the accommodation space airtight; and a pressing unit for pressing a bottom of the molten solder arranged in the solder bath and moving the molten solder upward, to fill the molten solder in the via.

Abstract: A microelectromechanical system structure and a method for fabricating the same are provided. A method for fabricating a MEMS structure includes the following steps. A first substrate is provided, wherein a transistor, a first dielectric layer and an interconnection structure are formed thereon. A second substrate is provided, wherein a second dielectric layer and a thermal stability layer are formed on the second substrate. The first substrate is bonded to the second substrate, and the second substrate removed. A conductive layer is formed within the second dielectric layer and electrically connected to the interconnection structure. The thermal stability layer is located between the conductive layer and the interconnection structure. A growth temperature of a material of the thermal stability layer is higher than a growth temperature of a material of the conductive layer and a growth temperature of a material of the interconnection structure.

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract: A semiconductor structure includes a substrate including a first side, a second side opposite to the first side, and a device layer over the second side, and a conductive via extending through the substrate, and including a first portion adjacent to the first side and a second portion adjacent to the device layer, wherein the conductive via includes an interface between the first portion and the second portion, an average grain size of the first portion is substantially different from an average grain size of the second portion.

Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.

Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a second wiring substrate having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring substrate, and a second semiconductor chip mounted on the second wiring substrate. The first wiring substrate includes a first power supply line and a second power supply line supplying a plurality of power supply potentials, whose types are different from each other, to the second semiconductor chip. In a plan view, the second power supply line is arranged to cross over a first substrate side of the second wiring substrate and a first chip side of the second semiconductor chip. In a plan view, the first power supply line is arranged to pass between the second power supply line and a part of the plurality of first semiconductor chips and to extend toward a region overlapping with the second semiconductor chip.

Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.

Abstract: Provided are a through electrode including an organic side-wall insulating film, capable of eliminating a barrier layer and achieving satisfactory mechanical reliability and electrical reliability and a manufacturing method thereof, and a semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a through electrode disposed in a semiconductor substrate is provided, including: a copper layer in the semiconductor substrate; and a side-wall insulating film that is disposed between the copper layer and the semiconductor substrate so as to be in contact with the copper layer and the semiconductor substrate, the side-wall insulating film being represented by the following chemical formula (1).

Abstract: A liquid crystal display structure includes a liquid crystal display panel, a backlight assembly arranged on one side of the liquid crystal display panel, and a polarizer arranged on a side of the liquid crystal display panel opposite from the backlight assembly. The liquid crystal display structure includes a display area and a non-display area surrounding the display area. The polarizer includes a first section and a second section, the first section being located in a central portion of the polarizer and corresponding in position to the display area, and the second section surrounding the first section and corresponding to the non-display area. The second section of the polarizer defines at least one through hole between every two adjacent corners of the second section.

Abstract: A semiconductor memory device and front-end method of fabricating nickel plated caps over bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. In some examples, the method and device include one or more conductive and insulating layers formed over a substrate, and a plurality of memory cells over the conductive and insulating layers.

Abstract: A method for selective etching using a dry film photoresist includes forming an opening through a substrate from a first surface to expose a stop layer at a second surface of the substrate. A material layer is formed over an inner surface of the opening and over the stop layer. The dry film photoresist is applied over the first surface of the substrate and over the opening. A second photoresist is applied on the dry film photoresist. First and second aligned holes are formed in the second photoresist and the dry film photoresist, respectively. The holes are approximately centered over the opening and are smaller in diameter than the opening so that a composite structure of the dry film photoresist and the second photoresist overhangs edges of the opening. The material layer is removed from the stop layer by etching via the first and second holes.

Abstract: An embodiment of a semiconductor die includes a base semiconductor substrate and an electrically conductive through substrate via (TSV) extending between the surfaces of the base semiconductor substrate. The bottom surface of the base semiconductor substrate includes a recessed region proximate to the TSV so that an end of the TSV protrudes from the bottom surface, and so that the TSV sidewall has an exposed portion at the protruding end of the TSV. Back metal, consisting of one or more metallic layers, is deposited on the bottom surface of the base semiconductor substrate and in contact with the TSV. The back metal can include a gold layer, a sintered metallic layer, and/or a plurality of other conductive layers. The die may be attached to a substrate using solder, another sintered metallic layer, or other materials.

Abstract: A material includes a base resin; a solvent; and a foaming agent and a photosensitizer, and/or a substance that serves as a foaming agent and a photosensitizer.

Abstract: A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation unit is configured to generate a chip ID signal. The chip ID transmission unit is configured to output the chip ID signal to a common line on the basis of whether another chip is electrically coupled therewith. The chip stack information generation unit is configured to be electrically coupled with the common line in response to the chip ID signal and generate a stack information signal.

Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

Abstract: A through-silicon-via structure formed within a semiconductor device is provided. The TSV structure may include a trench located within a substrate of the semiconductor device, an insulator layer located on at least one side wall of the trench, an electrically conductive layer located on the insulator layer, a first dielectric layer located on the electrically conductive layer, and a second dielectric layer located on the first dielectric layer and filling the trench. The second dielectric layer includes a higher refractive index relative to the first dielectric layer, such that the first and the second dielectric layer create an optical waveguide.

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

Abstract: A method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor substrate from a surface of the semiconductor substrate. The insulation trench structure laterally surrounds a portion of the semiconductor substrate. The method further comprises modifying the laterally surrounded portion of the semiconductor substrate to form a vertical electrically conductive structure comprising an alloy material. The alloy material is an alloy of the semiconductor substrate material and at least one metal.

Abstract: A semiconductor device includes a first semiconductor substrate having a first wiring layer which includes a first conductive pad, a second semiconductor substrate disposed on the first semiconductor substrate and including a second wiring layer which includes a second conductive pad, a first oxide layer disposed on the second semiconductor substrate and containing a second end of an intermediate connection which extends vertically through the second semiconductor substrate and has a first end electrically connected to the second conductive pad, and a third semiconductor substrate disposed on the first oxide layer and including a third wiring layer which includes a third conductive pad. The second end of the intermediate connection layer is electrically connected to the third conductive pad via a metal bond.

Abstract: A semiconductor structure includes a semiconductor substrate and a conductive element formed in a portion of the semiconductor substrate. The semiconductor structure further includes a plurality of insulating elements formed in portions of the semiconductor substrate at a first region surrounding the conductive element and a semiconductor device formed over a portion of the semiconductor substrate at a second region adjacent to the first region. The first region is formed between the conductive element and the second region.

Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

Abstract: A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface facing each other, an interlayer dielectric layer provided on the top surface of the semiconductor substrate and including an integrated circuit, an inter-metal dielectric layer provided on the interlayer dielectric layer and including at least one metal interconnection electrically connected to the integrated circuit, an upper dielectric layer disposed on the inter-metal dielectric layer, a through-electrode penetrating the inter-metal dielectric layer, the interlayer dielectric layer, and the semiconductor substrate, a via-dielectric layer surrounding the through-electrode and electrically insulating the through-electrode from the semiconductor substrate. The via-dielectric layer includes one or more air-gaps between the upper dielectric layer and the interlayer dielectric layer.

Abstract: A fingerprint sensor chip package structure including a circuit carrier and a fingerprint sensor chip is provided. The fingerprint sensor chip is disposed on the circuit carrier. The fingerprint sensor chip includes a chip body and a plurality of sensing structures. The chip body has an active surface, a fingerprint sensing back surface, a plurality of bond pads disposed on the active surface and a plurality of through holes. The chip body is electrically connected to the circuit carrier with the active surface facing the circuit carrier. The sensing structures are disposed in the through holes respectively. Each of the sensing structures includes a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer. The first dielectric layer is exposed on the fingerprint sensing back surface. The second metal layer extends to the active surface to be electrically connected to the corresponding bond pad.

Abstract: A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold and a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die. A pillar is disposed through the second mold layer and is coupled to a first metal layer disposed above the first dielectric layer. The first metal layer is coupled to the first die, and the pillar is coupled to a second metal layer disposed above the second dielectric layer.

Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.

Abstract: An electronic device may have layers of glass for forming components such as a display. A display cover glass layer may overlap an array of pixels. A touch sensor may be formed under the display cover glass layer. Conductive structures such as transparent conductive electrodes or other conductive layers of material may be formed on the outer surface of the display cover glass layer. The electrodes on the outer surface of the display cover glass layer may be coupled to metal contacts and other circuitry on the inner surface of the display cover glass layer using conductive vias. Vias may be provided with barrier layers, opaque coatings, tapers, and other structures and may be formed using techniques that enhance compatibility with chemical strengthening processes.

Abstract: Integrated circuit (IC) devices are provided including a substrate having a first sidewall defining a first through hole that is a portion of a through-silicon via (TSV) space, an interlayer insulating layer having a second sidewall and a protrusion, wherein the second sidewall defines a second through hole providing another portion of the TSV space and communicating with the first through hole, and the protrusion protrudes toward the inside of the TSV space and defines an undercut region in the first through hole, a TSV structure penetrating the substrate and the interlayer insulating layer and extending through the first through hole and the second through hole, and a via insulating layer surrounding the TSV structure in the first through hole and the second through hole.

Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include a semiconductor die having a first surface, a second surface opposite to the first surface, and side surfaces between the first and second surfaces; an encapsulant encapsulating the side surfaces of the semiconductor die; a contact pad on the first surface of the semiconductor die; and a redistribution layer coupled to the contact pad The redistribution layer may include a linear portion and a circular pad, and a hemispherical conductive bump on the circular pad may include a protruding part extending toward the linear portion and having a radius less than the hemispherical conductive bump. The second surface of the semiconductor die may be coplanar with a surface of the encapsulant. A dielectric layer may cover a portion of the first surface of the semiconductor die and a first surface of the encapsulant.

Abstract: An electronic device can include one or more trenches that include a material that defines one or more voids. In an embodiment, the substrate defines a first trench having a first portion and a second portion laterally adjacent to the first portion, wherein the first portion has with a first width, the second portion has a second width, and the first width is wider than the second width. The material defines a first void at a predetermined location within the first portion of the first trench and has a seam within the second portion of the first trench. In another embodiment, the substrate defining a trench, and the material that defines spaced-apart voids at predetermined locations within the trench. A process of forming the electronic device can include patterning a substrate to define a trench, and depositing a material within the trench, wherein the deposited material defines a void.

Abstract: Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Abstract: Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel.

Abstract: A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate, wherein the substrate has a front side and a back side, forming a first guard ring doped region and a second guard ring doped region in the substrate, wherein the first guard ring doped region and the second guard ring doped region have different conductive types, forming a trench through the substrate from a back side of the substrate, conformally forming an insulating layer lining the back side of the substrate, a bottom surface and sidewalls of the trench, removing a portion of the insulating layer on the back side of the substrate to form a through via, and forming a conductive material in the through via, wherein a through silicon via (TSV) interconnect structure is formed by the insulating layer and the conductive material.

Abstract: A silicon-on-insulator radio frequency device and a silicon-on-insulator substrate are provided. In the silicon-on-insulator radio frequency device, a pit is formed on a surface of a high resistivity silicon plate which is close to a buried oxide layer. The pit may be filled with an insulating material, thereby increasing an equivalent surface resistance of the high resistivity silicon plate; or no insulating material is filled into the pit, that is, the pit remains a vacuum state or is only filled with air, which can increase the equivalent surface resistance of the high resistivity silicon plate as well. In such, an eddy current generated on a surface of the high resistivity silicon plate under the action of a radio frequency signal may be reduced. As a result, loss of the radio frequency signal is reduced and the linearity of the radio frequency signal is improved.

Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and conductive via is removed by a chemical mechanical polishing process. The semiconductor wafer and conductive via are coplanar at first and second surfaces. A first insulating layer and a second insulating layer are formed over the conductive via and semiconductor wafer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. An opening in the first and second insulating layers is formed over the conductive via while a second portion of the conductive via remains covered by the first and second insulating layers. A conductive layer is formed over the conductive via and first insulating layer. An interconnect structure is formed over the conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

Abstract: Electrically conductive barriers for integrated circuits and integrated circuits and methods including the electrically conductive barriers. The integrated circuits include a semiconductor substrate, a semiconductor device supported by a device portion of the substrate, and a plurality of bond pads supported by a bond pad portion of the substrate. The integrated circuits also include an electrically conductive barrier that projects away from an intermediate portion of the substrate and is configured to decrease capacitive coupling between the device portion and the bond pad portion. The methods can include methods of manufacturing an integrated circuit. These methods include forming a semiconductor device, forming a plurality of bond pads, forming a plurality of electrically conductive regions, and forming an electrically conductive barrier. The methods also can include methods of operating an integrated circuit.

Abstract: An OLED display panel includes a substrate, a light emitting structure and a driving structure. The substrate defines an electrical conductive hole. The light emitting structure is located at a side of the substrate. The light emitting structure includes a first electrode, a second electrode and an organic light emitting layer located between the first electrode and the second electrode. The driving structure includes a row drive circuit line and a column drive circuit line. The substrate includes a face opposite to the light emitting structure. The row drive circuit line is coupled to the face of the substrate. The first electrode is electrically coupled to the row drive circuit line via the electrical conductive hole. The column drive circuit line is coupled to the light emitting structure to be electrically coupled to the second electrode. A display device with the OLED display panel is also provided.

Abstract: A method includes forming a molded panel that includes a number of integrated circuits, fan-out components and stiffeners embedded in an encapsulation material. A redistribution layer is formed over the integrated circuits and the fan-out components. The redistribution layer is electrically coupled to contacts of the integrated circuits. The molded panel is singulated to form electronic devices. Each electronic device each an integrated circuit that is separated from a fan-out component by a portion of the encapsulation material and a stiffener separated from the fan-out component by a second portion of the encapsulation material.

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.