Abstract: A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a flexible substrate and a buffer stack overlying the substrate. The buffer stack comprises at least one epitaxial buffer layer. An epitaxial doped layer comprised predominantly of silicon overlies the at least one epitaxial buffer layer. Mobility of the device is greater than 100 cm2/Vs and carrier concentration of the epitaxial doped layer is less than 1016 cm?3.

Abstract: A mask includes a mask body and at least one sub-mask provided on the mask body. The sub-mask includes an evaporation zone and a shield portion. The shield portion is provided with at least one groove in a thickness direction of the sub-mask. The groove has a depth smaller than a thickness of the mask body. Since the shield portion is provided with the groove, and a single groove has a depth smaller than the thickness of the mask body, it not only ensures that there is no pixel evaporated onto a substrate at the shield portion, but also reduces the thickness of the shield portion, thereby reduces weight thereof, lowers the weight difference between the shield portion and the evaporation zone and reduces the stress concentration on the shield portion, resulting in that the mask body is evenly stressed during tensioning.

Abstract: The present disclosure relates to a pixel structure. The pixel structure may include a base substrate; a first insulating island on a side of the base substrate; a first electrode on a side of the first insulating island opposite front the base substrate; a second electrode on the base substrate and at a peripheral area of the first insulating island; an active layer electrically connected to the first electrode and the second electrode; a second insulating layer on a side of the active layer opposite from the base substrate; a gate electrode on a side of the second insulating layer opposite from the base substrate; and a third insulating layer on a side of the gate electrode opposite from the base substrate.

Abstract: A method for fabricating an electronic device including a semiconductor memory includes forming a chalcogenide layer, forming a first conductive layer on the chalcogenide layer, and increasing a density of an interface between the chalcogenide layer and the first conductive layer by injecting or irradiating ions onto the interface.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.

Abstract: Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials.

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

Abstract: The present disclosure relates to a mask sheet. The mask sheet includes a plurality of mask units. Each mask unit includes an evaporation effective area and a plurality of welding areas that are distributed around the evaporation effective area according to a preset rule. The distribution of the welding areas around the evaporation effective areas of the mask units at the edge of the mask sheet is consistent with the distribution of the welding areas around the evaporation effective areas of the mask units located in the inner region of the mask sheet.

Abstract: A method of forming a crystallized semiconductor layer includes forming an insulating crystallization inducing layer on a base substrate; forming a semiconductor material layer on a side of the insulating crystallization inducing layer away from the base substrate by depositing a semiconductor material on the insulating crystallization inducing layer, the semiconductor material being deposited at a deposition temperature that induces crystallization of the semiconductor material; forming an alloy crystallization inducing layer including an alloy on a side of the semiconductor material layer away from the insulating crystallization inducing layer; and annealing the alloy crystallization inducing layer to further induce crystallization of the semiconductor material to form the crystallized semiconductor layer.

Abstract: A semiconductor device includes a first semiconductor layer that is an electrically-conductive polycrystalline semiconductor layer and a second semiconductor layer on the first semiconductor layer. The second semiconductor layer is an electrically-conductive polycrystalline semiconductor layer having a smaller average grain size than the first semiconductor layer. A plurality of electrode layers are stacked on the second semiconductor layer at intervals in a first direction. A third semiconductor layer extends in the first direction through the first semiconductor layer, the second semiconductor layer, and each of the electrode layers and contacts the second semiconductor layer. A charge storage layer is between the plurality of electrode layers and the third semiconductor layer.

Abstract: A semiconductor device and method for fabricating same is disclosed. Embodiments are directed to a semiconductor device and fabrication of same which include a polycrystalline or amorphous substrate. An electrically conductive Ion Beam-Assisted Deposition (IBAD) template layer is positioned above the substrate. At least one electrically conductive hetero-epitaxial buffer layer is positioned above the IBAD template layer. The at least one buffer layer has a resistivity of less than 100 ??cm. The semiconductor device and method foster the use of bottom electrodes thereby avoiding complex and expensive lithography processes.

Abstract: A semiconductor device includes a substrate including a first area and a second area, and first and second transistors formed in the first area and the second area, respectively. The first transistor includes a first gate insulating layer on the substrate, a first TiN layer on the first gate insulating layer contacting the first gate insulating layer, and a first filling layer on the first TiN layer. The second transistor includes a second gate insulating layer on the substrate, a second TiN layer on the second gate insulating layer contacting the second gate insulating layer, and a second filling layer on the second TiN layer. A threshold voltage of the first transistor is less than that of the second transistor, the second gate insulating layer does not comprise lanthanum, and an oxygen content of a portion of the first TiN layer is greater than that of the second TiN layer.

Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction, depositing a phase change material over the p-n junction, and forming a second electrode over the phase change material.

Abstract: A display device includes: a thin-film transistor on a substrate, the thin-film transistor including on the substrate: an active layer; a gate electrode overlapping the active layer; a source electrode and a drain electrode electrically connected to the active layer and including a first metal material; and a first capping layer which covers each of the source electrode and the drain electrode, the first capping layer having a Young's modulus greater than that of the first metal material.

Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.

Abstract: A laser annealing device includes: a CW laser device configured to emit continuous wave laser light caused by continuous oscillation to preheat the amorphous silicon; a pulse laser device configured to emit the pulse laser light toward the preheated amorphous silicon; an optical system configured to guide the continuous wave laser light and the pulse laser light to the amorphous silicon; and a control unit configured to control an irradiation energy density of the continuous wave laser light so as to preheat the amorphous silicon to have a predetermined target temperature less than a melting point thereof, and configured to control at least one of a fluence and a number of pulses of the pulse laser light so as to crystallize the preheated amorphous silicon.

Abstract: Provided is a thermoelectric module including electrodes and P-type and N-type semiconductors formed on a substrate by a printing method. The thermoelectric module includes upper and lower substrates (110 and 120) formed of ceramic or aluminum and forming upper and lower surfaces of the thermoelectric module; electrodes (130) disposed on surfaces of the upper and lower substrates (110 and 120), the electrodes being formed of an electrically conductive material for transmitting electric power; a plurality of P-type and N-type semiconductors (140 and 150) spaced between the electrodes (130), the P-type and N-type semiconductors (140 and 150) being forming by sintering a paste mixture of thermoelectric powder and an organic solvent, wherein the electrodes (130) and the P-type and N-type semiconductors (140 and 150) are formed by a printing method. With this configuration, thin thermoelectric module having various sizes and shapes can be provided.

Abstract: Provided are methods for growing large-size, uniform graphene layers on planarized substrates using Chemical Vapor Deposition (CVD) at atmospheric pressure; graphene produced according to these methods may have a single layer content exceeding 95%. Field effect transistors fabricated by the inventive process have room temperature hole mobilities that are a factor of 2-5 larger than those measured for samples grown on commercially-available copper foil substrates.

Abstract: A new GaN single crystal is provided. A GaN single crystal according to the present embodiment comprises a gallium polar surface which is a main surface on one side and a nitrogen polar surface which is a main surface on the opposite side, wherein on the gallium polar surface is found at least one square area, an outer periphery of which is constituted by four sides each with a length of 2 mm or more, and, when the at least one square are is divided into a plurality of sub-areas each of which is a square of 100 ?m×100 ?m, pit-free areas account for 80% or more of the sub-areas.

Abstract: A quantum rod, a synthesis method of the quantum rod and a quantum rod display device are discussed. The quantum rod according to an embodiment includes a core, a first shell covering the core, and a second shell covering a side of the first shell. In the quantum rod, a first thickness of the first shell is greater than a second thickness of the second shell, and a first length of the first shell is smaller than a second length of the second shell.

Abstract: A monolithically integrated optical device. The device has a gallium and nitrogen containing substrate member having a surface region configured on either a non-polar or semi-polar orientation. The device also has a first waveguide structure configured in a first direction overlying a first portion of the surface region. The device also has a second waveguide structure integrally configured with the first waveguide structure. The first direction is substantially perpendicular to the second direction.

Abstract: Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate surfaces with a vertical substrate sidewall extending therebetween. The vertical substrate sidewall corresponds to an outermost edge of the substrate. A device layer is arranged over the upper substrate surface. A crack stop is arranged over an upper surface of the device layer and has an outer perimeter that is spaced apart laterally from the vertical substrate sidewall. The die exhibits a tapered sidewall extending downward through at least a portion of the device layer to meet the vertical substrate sidewall.

Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.

Abstract: A semiconductor device may include fin active regions extending parallel to each other on a substrate, an isolation region between the fin active regions, gate patterns intersecting the fin active regions and extending parallel to each other, source/drain areas on the fin active regions between the gate patterns and fin active region spacers contacting side surfaces of the fin active regions and formed over a surface of the isolation region between the fin active regions. Uppermost levels of the fin active region spacers may be higher than interfaces between the fin active regions and the source/drain areas. The upper surface of the isolation region may be lower than bottom surfaces of the source/drain areas.

Abstract: A FinFET device includes a substrate and a fin structure having a semiconductor material layer over the substrate and recessed regions on side walls of the fin structure. The recessed regions have openings facing away from the fin structure. The fin structure has a bottom portion below the recessed regions that is wider than a top portion.

Abstract: Systems and methods for fabricating an OLED are provided, which include dispensing a substrate material onto a substrate carrier, the substrate carrier being rotated by one or more drums, curing the substrate material to form a substrate, depositing at least one OLED onto the substrate, and separating the substrate from the substrate carrier.

Abstract: A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.

Abstract: A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.

Abstract: A thin film transistor array substrate includes a substrate, a plurality of poly-silicon islands and a plurality of gates. The substrate has a display region, a gate driver region and a source driver region. Each poly-silicon island disposed on the substrate has a source region, a drain region and a channel region disposed therebetween. The poly-silicon islands include several first poly-silicon islands and several second poly-silicon islands. The first poly-silicon islands having main grain boundaries and sub grain boundaries are only disposed within the display region and the gate driver region. The main grain boundaries of the first poly-silicon islands are only disposed within the source regions and/or the drain regions. The second poly-silicon islands are disposed in the source driver region. Grain sizes of the first poly-silicon islands are substantially different from those of the second poly-silicon islands. Gates corresponding to the channel regions are disposed on the substrate.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.

Abstract: A semiconductor device which is miniaturized and has sufficient electrical characteristics to function as a transistor is provided. In a semiconductor device including a transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are stacked in that order, an oxide semiconductor film which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and in which the percentage of the indium is twice or more as large as each of the percentage of the gallium and the percentage of the zinc when the composition of the four elements is expressed in atomic percentage is used as the semiconductor layer. In the semiconductor device, the oxide semiconductor film is a film to which oxygen is introduced in the manufacturing process and contains a large amount of oxygen, and an insulating layer including an aluminum oxide film is provided to cover the transistor.

Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

Abstract: A method of forming a fin field effect transistor (FinFET) structure including forming a plurality of shallow trench isolation (STI) features in a semiconductor substrate, thereby defining a plurality of bulk-semiconductor areas separated from each other by the STI features. The method then forms a first hard mask layer on the semiconductor substrate, the first hard mask layer being patterned to have a plurality of openings over one of the bulk-semiconductor areas. A second semiconductor material is then grown on the semiconductor substrate within the plurality of openings of the first hard mask layer, thereby forming a multi-fin active region having multiple fin features within the one of the bulk-semiconductor areas.

Abstract: A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.

Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.

Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.

Abstract: In accordance with an embodiment, an evaluation sample includes a substrate and a polycrystalline film on the substrate. The polycrystalline film has crystal grains. A specific orientation plane is exposed on the surface of each crystal grain. The orientation planes exhibit random angles to the surface of the substrate.

Abstract: A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide.

Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.

Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.

Abstract: A display substrate includes a base substrate, a first insulating layer formed on a base substrate, a pixel including a pixel electrode having the first insulating layer, and a circuit including a circuit transistor disposed on a peripheral area to drive the pixel. The pixel includes a first channel formed on the base substrate having the first insulating layer formed thereon. The first channel includes a poly-silicon layer, a first source electrode and a first drain electrode formed on the first channel that are spaced apart from each other, and a first gate electrode formed on the first source electrode and the first drain electrode corresponding to the first channel which is formed of the transparent conductive material. The poly-silicon layer is formed at a front channel portion of the first channel proximal to the first gate electrode through the first gate electrode.

Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.

Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.

Abstract: An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate. The correcting unit corrects a dropping position of the resist on a basis of a position of the underlying pattern. The dropping position control unit causes the resist to be dropped onto a dropping position after correction on the transfer target substrate on the basis of corrected dropping position.

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract: A thin film transistor (TFT) having an active layer pattern, the active layer pattern including a first active layer pattern extending in a first direction; a second active layer pattern extending in the first direction and parallel to the first active layer pattern; and a third active layer pattern connecting a first end of the first active layer pattern to a first end of the second active layer pattern.

Abstract: An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.