Non-single Crystal, Or Recrystallized, Material With Specified Crystal Structure (e.g., Specified Crystal Size Or Orientation) Patents (Class 257/64)
-
Patent number: 7863617Abstract: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion layer, and having projections and depressions on a surface thereof opposing to the first substrate, the projections and depressions having rounded tips and bottoms; active elements provided on the thin glass layer, each active element corresponding to a pixel; a display provided above the thin glass layer, and driven by the active elements to display an image pixel by pixel; and a second substrate provided on the display, and having an opposing electrode formed thereon.Type: GrantFiled: December 16, 2008Date of Patent: January 4, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsuyoshi Hioki, Masahiko Akiyama, Mitsuo Nakajima, Yujiro Hara, Yutaka Onozuka
-
Publication number: 20100327288Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.Type: ApplicationFiled: June 28, 2010Publication date: December 30, 2010Applicant: PFC DEVICE CORPORATIONInventors: Kou-Liang CHAO, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
-
Patent number: 7859055Abstract: To provide: a thin film transistor which can be operated with a low threshold and has a high transistor withstand voltage; a production method of the thin film transistor; and a semiconductor device, an active matrix substrate, and a display device, each including such a thin film transistor. The present invention is a thin film transistor including a semiconductor layer, a gate insulating film, a gate electrode on a substrate in this order, wherein a cross section of the semiconductor layer has a forward tapered shape; the gate insulating film covers a top surface and a side surface of the semiconductor layer; and the gate insulating film has a multilayer structure including a silicon oxide film on a semiconductor layer side and a film made of a material with a dielectric constant higher than a dielectric constant of silicon oxide on a gate electrode side; the gate insulating film satisfies 0.Type: GrantFiled: June 1, 2006Date of Patent: December 28, 2010Assignee: Sharp Kabushiki KaishaInventors: Hiroshi Matsukizono, Tadayoshi Miyamoto
-
Patent number: 7851695Abstract: The present invention makes it possible to provide a stacked-type thin-film photoelectric conversion device having high photostability, at a high yield rate and significantly reduced production costs. In a stacked-type photoelectric conversion device having an amorphous silicon-based photoelectric conversion unit and a crystalline silicon-based photoelectric conversion unit stacked thereon or vice versa, an amorphous photoelectric conversion layer included in the amorphous photoelectric conversion unit has a thickness of at least 0.03 ?m and less than 0.17 ?m, a crystalline photoelectric conversion layer included in the crystalline photoelectric conversion unit has a thickness of at least 0.2 ?m and less than 1.0 ?m, and a silicon oxide layer of a first conductivity type included in the amorphous photoelectric conversion unit and a silicon layer of a second conductivity type included in the crystalline photoelectric conversion unit make a junction.Type: GrantFiled: December 19, 2006Date of Patent: December 14, 2010Assignee: Kaneka CorporationInventors: Toru Sawada, Yuko Tawada, Takashi Suezaki, Kenji Yamamoto
-
Patent number: 7847293Abstract: Lateral epitaxial overgrowth (LEO) of non-polar gallium nitride (GaN) films results in significantly reduced defect density.Type: GrantFiled: February 1, 2007Date of Patent: December 7, 2010Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Benjamin A. Haskell, Michael D. Craven, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamura
-
Patent number: 7838397Abstract: In a laser annealing process: the first to fourth sections of a bandlike area of a nonmonocrystalline semiconductor film are consecutively scanned and irradiated with laser light so as to produce a fused region in the bandlike area, where the fourth section contains a portion required to have higher crystallinity than other portions of the bandlike area. In the first section, the width of the fused region is substantially uniform. In the second section, the width of the fused region is stepwise or continuously decreased from the width of the fused region in the first section. In the third section, the width of the fused region is stepwise or continuously increased from the width of the fused region at the boundary between the second and third sections. In the fourth section, the width of the fused region at the boundary between the third and fourth sections is substantially uniformly maintained.Type: GrantFiled: January 30, 2007Date of Patent: November 23, 2010Assignee: FUJIFILM CorporationInventor: Atsushi Tanaka
-
Patent number: 7834425Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.Type: GrantFiled: May 5, 2008Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Meikei Ieong, Xinlin Wang, Min Yang
-
Patent number: 7816680Abstract: Provided are oxide semiconductors and thin film transistors of the same. An oxide semiconductor includes Zn, In and Hf. The amount of Hf is in the range of about 2-16 at %, inclusive, based on the total amount of Zn, In, and Hf. A thin film transistor includes a gate and a gate insulating layer arranged on the gate. A channel corresponding to the gate is formed on the gate insulating layer. The channel includes an oxide semiconductor. The semiconductor oxide includes Zn, In and Hf. The amount of Hf is in the range of about 2-16 at %, inclusive, based on the total amount of Zn, In, and Hf. A source and a drain contact respective sides of the channel.Type: GrantFiled: June 19, 2008Date of Patent: October 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-jung Kim, Sang-wook Kim, Sun-il Kim
-
Patent number: 7800081Abstract: The present invention generally describes apparatuses and methods used to perform an annealing process on desired regions of a substrate. In one embodiment, pulses of electromagnetic energy are delivered to a substrate using a flash lamp or laser apparatus. The pulses may be from about 1 nsec to about 10 msec long, and each pulse has less energy than that required to melt the substrate material. The interval between pulses is generally long enough to allow the energy imparted by each pulse to dissipate completely. Thus, each pulse completes a micro-anneal cycle. The pulses may be delivered to the entire substrate at once, or to portions of the substrate at a time. Further embodiments provide an apparatus for powering a radiation assembly, and apparatuses for detecting the effect of pulses on a substrate.Type: GrantFiled: July 16, 2008Date of Patent: September 21, 2010Assignee: Applied Materials, Inc.Inventors: Stephen Moffatt, Joseph M. Ranish
-
Patent number: 7795734Abstract: To provide a semiconductor device composed of a semiconductor element or a group of semiconductor elements, in which a crystalline semiconductor film having as few grain boundaries as possible in a channel formation region is formed on an insulating surface, which can operate at high speed, which have high current drive performance, and which are less fluctuated between elements.Type: GrantFiled: December 11, 2006Date of Patent: September 14, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki, Chiho Kokubo, Koichiro Tanaka, Akihisa Shimomura, Tatsuya Arao, Hidekazu Miyairi
-
Patent number: 7786503Abstract: A crystal comprising gallium nitride is disclosed. The crystal has at least one grain having at least one dimension greater than 2.75 mm, a dislocation density less than about 104 cm?2, and is substantially free of tilt boundaries.Type: GrantFiled: November 13, 2006Date of Patent: August 31, 2010Assignee: Momentive Performance Materials Inc.Inventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven Francis LeBoeuf, Larry Burton Rowland, Kristi Jean Narang, Huicong Hong, Stephen Daley Arthur, Peter Micah Sandvik
-
Publication number: 20100213465Abstract: A semiconductor component is provided having a substrate and at least one semiconductor layer realized to be polycrystalline on one side of the substrate. The polycrystalline semiconductor layer contains the crystal nuclei.Type: ApplicationFiled: July 29, 2008Publication date: August 26, 2010Applicant: Dritte Patentportifolio Beteiligungsgesellschaft mbH & Co. KGInventors: Otto Hauser, Hartmut Frey
-
Patent number: 7777226Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film comprising adjacent primary grain boundaries that are not parallel to each other and do not contact each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.Type: GrantFiled: August 11, 2005Date of Patent: August 17, 2010Assignee: Samsung Mobile Display Co., Ltd.Inventors: Ji Yong Park, Hye Hyang Park
-
Publication number: 20100200834Abstract: Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.Type: ApplicationFiled: March 22, 2010Publication date: August 12, 2010Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
-
Patent number: 7772592Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.Type: GrantFiled: November 19, 2007Date of Patent: August 10, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
-
Patent number: 7772486Abstract: The present invention provides a photovoltaic device capable of keeping reduction of the yield in modularization in check. This photovoltaic device comprises a transparent conductive film, and a collector which is formed on the surface of the transparent conductive film so as to be in partial contact with a semiconductor layer.Type: GrantFiled: December 3, 2004Date of Patent: August 10, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Takeshi Nakashima, Eiji Maruyama
-
Publication number: 20100193795Abstract: Methods for forming semiconductor devices include providing a crystalline template having an initial grain size, annealing the crystalline template, the annealed template having a final grain size larger than the initial grain size, forming a buffer layer over the annealed template, and forming a semiconductor layer over the buffer layer.Type: ApplicationFiled: January 28, 2010Publication date: August 5, 2010Inventors: Leslie G. Fritzemeier, Christopher J. Vineis
-
Patent number: 7759175Abstract: The fabrication method of a mixed substrate comprising a tensile strained silicon-on-insulator portion and a compressive strained germanium-on-insulator portion comprises a first step of producing a strained silicon-on-insulator base substrate comprising first and second tensile strained silicon zones. After the base substrate has been produced, the method comprises the successive steps of masking the first tensile strained silicon zone forming the tensile strained silicon-on-insulator portion of the substrate, of performing germanium enrichment treatment of the second tensile strained silicon zone of the base substrate until a compressive strained germanium layer is obtained forming said compressive strained germanium-on-insulator portion of the substrate, and of removing the masking.Type: GrantFiled: February 27, 2008Date of Patent: July 20, 2010Assignee: Commissariat a l'Energie AtomiqueInventors: Laurent Clavelier, Cyrille Le Royer, Jean-François Damlencourt
-
Patent number: 7759749Abstract: When metallic material is employed for various metallic films, it is possible to improve at least one of the mechanical strength, the durability against abrasion, and the uniformess as a film while keeping unchanged the chemical property and the electric property of the metallic material. Due to the gel three-dimensional mesh structure 406, the dislocations 407 of the tangle in the mesh form are introduced in the crystal of the metal 401 at high density; therefore, when the tensile stress 403 is applied thereto, these dislocations slightly shift. As a result, the metal 401 deforms by uniformly dispersing distortion in the order of crystal grains, and hence there does not occur concentration of stress, which leads to the breakage or the severance at the grain interface 402. Therefore, the metallic material of the present invention improves the mechanical strength and the durability against abrasion.Type: GrantFiled: February 7, 2006Date of Patent: July 20, 2010Assignee: NEC CorporationInventor: Akio Tanikawa
-
Patent number: 7755172Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.Type: GrantFiled: June 20, 2007Date of Patent: July 13, 2010Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Tadao Hashimoto, Hitoshi Sato, Shuji Nakamura
-
Patent number: 7745826Abstract: A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided.Type: GrantFiled: October 13, 2008Date of Patent: June 29, 2010Assignee: Au Optronics CorporationInventors: Ming-Wei Sun, Chih-Wei Chao
-
Patent number: 7723167Abstract: In a laser annealing process: a bandlike area of a nonmonocrystalline semiconductor film is scanned and irradiated with continuous-wave laser light so as to produced fused regions in the first to third sections of the bandlike area as follows, where the third section contains a portion required to have higher crystallinity than other portions of the bandlike area. First, a first fused region having a substantially uniform width is formed in the first section. Then, at least a portion of the first fused region which is last fused is solidified, and thereafter at least a subportion of the solidified portion having a smaller width than the first fused region is re-fused. Subsequently, a second fused region having a stepwise or continuously increasing width is produced in the second section, and then a third fused region substantially uniformly having the increased width is produced in the third section.Type: GrantFiled: January 30, 2007Date of Patent: May 25, 2010Assignee: FUJIFILM CorporationInventor: Atsushi Tanaka
-
Patent number: 7714330Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.Type: GrantFiled: August 14, 2007Date of Patent: May 11, 2010Assignee: Samsung Electronics Co., LtdInventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
-
Patent number: 7709288Abstract: The present invention provides a method for manufacturing a multi-junction solar cell which makes it possible to implement a 4-junction solar cell and to increase the area of a device. A nucleus generation site is disposed on a substrate 2 made of a first semiconductor. A first material gas is fed to the nucleus generation site to form a wire-like semiconductor 3 in the nucleus generation site. A third material gas and a fourth material gas are fed to form a wire-like semiconductor 4 on the semiconductor 3 and a wire-like semiconductor 5 on the semiconductor 4. A nucleus generation site is disposed on a substrate 6. The first material gas is fed to the nucleus generation site to form a wire-like semiconductor 2a in the nucleus generation site. A second material gas to the fourth material gas are fed to form the wire-like semiconductor 3 on the semiconductor 2a, the wire-like semiconductor 4 on the semiconductor 3, and the wire-like semiconductor 5 on the semiconductor 4.Type: GrantFiled: July 17, 2007Date of Patent: May 4, 2010Assignee: Honda Motor Co., Ltd.Inventor: Hajime Goto
-
Publication number: 20100102323Abstract: A method is provided for forming a directionally crystallized (100)-normal crystallographic orientation silicon (Si) film. The method provides a substrate including Si. An amorphous Si (a-Si) layer is formed overlying the substrate, and a silicon oxide cap layer is formed overlying the a-Si layer. In response to scanning a laser in a first direction along a top surface of the silicon oxide cap layer, the a-Si layer is transformed into a crystalline Si film having a (100)-normal crystallographic orientation, with crystal grains elongated in the first direction. That is, the crystalline Si film has grain boundaries between crystal grains, aligned in parallel with the first direction.Type: ApplicationFiled: October 24, 2008Publication date: April 29, 2010Inventors: Robert S. Sposili, Apostolos T. Voutsas
-
Patent number: 7705357Abstract: A semiconductor element with high current drive capability, capable of high-speed operation, and having little variation in pluralities of semiconductor elements is provided. It is characterized by the fact that semiconductor elements have a first crystalline semiconductor region including pluralities of crystal orientations, and the first crystalline semiconductor region being connected to a second crystalline semiconductor region which is conductive, wherein the first crystalline semiconductor region is extended in the direction parallel to the insulating film which extends in linear-shaped stripe pattern on the insulating surface, and the second crystalline semiconductor region is provided ranging over the insulating film which extends in linear-shaped stripe pattern.Type: GrantFiled: March 4, 2003Date of Patent: April 27, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kiyoshi Kato, Atsuo Isobe, Hidekazu Miyairi, Hideomi Suzawa
-
Patent number: 7700165Abstract: Provided is a deposited film containing microcrystalline silicon by plasma CVD, which includes changing at least one of conditions selected from a high frequency power density, a bias voltage with respect to an interelectrode distance, a bias current with respect to an electrode area, a high frequency power with respect to a source gas flow rate, a ratio of a diluting gas flow rate to a source gas flow rate, a substrate temperature, a pressure, and an interelectrode distance, between conditions for forming a deposited film of a microcrystalline region and conditions for forming a deposited film of an amorphous region; and forming a deposited film under conditions within a predetermined range in the vicinity of boundary conditions under which the crystal system of the deposited film substantially changes between a amorphous state and a microcrystalline state.Type: GrantFiled: January 25, 2007Date of Patent: April 20, 2010Assignee: Canon Kabushiki KaishaInventors: Yasuyoshi Takai, Masafumi Sano, Keishi Saito
-
Patent number: 7679087Abstract: There is disclosed a method of fabricating a thin-film transistor having excellent characteristics. Nickel element is held in contact with selected regions of an amorphous silicon film. Then, thermal processing is performed to crystallize the amorphous film. Subsequently, thermal processing is carried out in an oxidizing ambient containing a halogen element to form a thermal oxide film. At this time, the crystallinity is improved. Also, gettering of the nickel element proceeds. This crystalline silicon film consists of crystals grown radially from a number of points. Consequently, the thin-film transistor having excellent characteristics can be obtained.Type: GrantFiled: August 9, 2002Date of Patent: March 16, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
-
Patent number: 7674667Abstract: A CMOS structure includes a first device located using a first active region within a semiconductor substrate, where the first active region is planar and has a first crystallographic orientation. The CMOS structure also includes a second device that is located using a second active region within the semiconductor substrate, where the second active region is topographic and has a second crystallographic orientation absent the first crystallographic orientation. The first crystallographic orientation and the second crystallographic orientation allow for performance optimizations of the first device and the second device, typically with respect to charge carrier mobility. The topographic second active region may also have a single thickness. The CMOS structure may be fabricated using a crystallographically specific etchant for forming the topographic second active region.Type: GrantFiled: November 21, 2006Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventor: Huilong Zhu
-
Patent number: 7671370Abstract: Improvement in characteristics of a SELAX-TFT and throughput of ELA crystallization is achieved. When a thin film transistor using pseudo single crystal semiconductor and a thin film transistor using particulate polysilicon semiconductor are formed on a single substrate, the film thickness of an amorphous semiconductor film before crystallization in the pseudo single crystal semiconductor portion is greater than that in the polysilicon semiconductor portion.Type: GrantFiled: September 18, 2007Date of Patent: March 2, 2010Assignee: Hitachi Displays, Ltd.Inventors: Hidekazu Miyake, Toshihiko Itoga, Eiji Oue, Takeshi Noda
-
Patent number: 7671421Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: GrantFiled: May 31, 2006Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
-
Patent number: 7659542Abstract: A polycrystalline silicon plate has grain boundary lines on a surface thereof, and at least one of the grain boundary lines is a quasi-linear grain boundary line (1). The silicon plate is used to produce a solar cell. The silicon plate is formed using a base substrate having an irregular surface provided with dotted or linear protrusions, which makes it possible to control the grain boundary lines. As such, an inexpensive and high-quality silicon plate can be provided. Further, by employing this silicon plate to produce a solar cell, an inexpensive and high-quality solar cell can be provided as well.Type: GrantFiled: April 28, 2006Date of Patent: February 9, 2010Assignee: Sharp Kabushiki KaishaInventor: Yoshihiro Tsukuda
-
Patent number: 7655511Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.Type: GrantFiled: November 3, 2005Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventor: Dureseti Chidambarrao
-
Patent number: 7655950Abstract: The present invention provides a manufacturing method of a high performance active matrix substrate at a high throughput with a less expensive apparatus, and an image display device using the active matrix substrate. On a stage moving in the short axis direction X and long axis direction Y on a rail, a glass substrate is carried, which has an amorphous silicon semiconductor film formed. Polycrystallized and large grain silicon film may be obtained by intensity modulating the pulsed laser beam in a line beam shape by means of a phase shift mask with a periodicity in the long axis direction Y of the laser beam, moving the laser beam randomly in the modulation direction of the amorphous silicon semiconductor film formed on the glass substrate to expose to crystallize the film. The image display device may incorporate an active matrix substrate having active elements such as thin film transistors formed by this silicon film.Type: GrantFiled: January 30, 2006Date of Patent: February 2, 2010Assignee: Hitachi Displays, Ltd.Inventors: Takeshi Sato, Kazuo Takeda, Masakazu Saito, Jun Goto, Makoto Ohkura
-
Patent number: 7649243Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.Type: GrantFiled: November 6, 2006Date of Patent: January 19, 2010Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
-
Patent number: 7619251Abstract: A method of irradiating at least a part of a semiconductor film on the substrate with a CW or pseudo-CW laser beam so as to grow crystals laterally. A region over the semiconductor film having Si as a chief component is provided with a pixel region, a gate line driving circuit region and a signal line driving circuit region for driving pixels, and a terminal region where connection terminals will be formed. The region not irradiated with the CW laser beam is provided in a peripheral portion of each semiconductor device corresponding to the position where the glass substrate will be cut. Due to this means, it is possible to suppress occurrence of a failure caused by propagation of cracks when the substrate is cut.Type: GrantFiled: May 25, 2006Date of Patent: November 17, 2009Assignee: Hitachi Displays, Ltd.Inventors: Takeshi Sato, Takahiro Kamo, Takeshi Noda
-
Patent number: 7619250Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.Type: GrantFiled: August 11, 2006Date of Patent: November 17, 2009Assignee: Sharp Kabushiki KaishaInventors: Yutaka Takafuji, Takashi Itoga
-
Patent number: 7615424Abstract: An object of the present invention is to provide a laser irradiation method being able to control the irradiation position of the laser beam accurately compared with the conventional irradiation method. Another object of the present invention is to provide a method for manufacturing a semiconductor device with the use of the laser irradiation method being able to irradiate a large substrate accurately with the laser beam. The irradiation position of the laser beam is controlled by using a laser oscillator emitting a laser beam, an optical system for shaping the laser beam into rectangular on the irradiation object, means for moving the irradiation object relative to the laser beam in the long-side direction and the short-side direction of the beam spot, means for moving the irradiation object more slowly in the long-side direction than in the short-side direction, and a laser positioning mechanism.Type: GrantFiled: March 24, 2005Date of Patent: November 10, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koichiro Tanaka, Yoshiaki Yamamoto, Nami Kosaka
-
Patent number: 7608530Abstract: A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.Type: GrantFiled: March 1, 2007Date of Patent: October 27, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Nobuhiko Kobayashi, Shih Yuan Wang
-
Patent number: 7608857Abstract: A TFT having a large mobility of carriers that are conducted through a channel as compared with a conventional organic TFT, and a method of manufacturing the TFT inexpensively and easily are provided. The channel is formed of a semiconductor organic molecular crystal thin film which is highly oriented, and a TFT that is large in the mobility of the carriers that are conducted through the channel, and a lyophilic TFT pattern that is surrounded by a lyophobic region on a substrate are formed, and the configuration of the pattern is featured, whereby a solution of the semiconductor organic molecules which is supplied to an appropriate region of a substrate surface including the channel is spontaneously dried in an anisotropic fashion, and highly oriented crystal is grown in the drying process.Type: GrantFiled: November 21, 2006Date of Patent: October 27, 2009Assignee: Hitachi, Ltd.Inventors: Masaaki Fujimori, Tomihiro Hashizume, Masahiko Ando
-
Patent number: 7601983Abstract: A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.Type: GrantFiled: August 19, 2005Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Tetsuji Ueno, Hwa-Sung Rhee, Ho Lee, Dong-Suk Shin, Seung-Hwan Lee
-
Patent number: 7569462Abstract: The present invention provides a method of recrystallizing a silicon sheet, and in particular recrystallizing a small grained silicon sheet to improve material properties such as grain size and orientation. According to one aspect, the method includes using rapid thermal processing (RTP) to melt and recrystallize one or more entire silicon sheet(s) in one heating sequence. According to another aspect, the method includes directionally controlling a temperature drop across the thickness of the sheet so as to facilitate the production of a small number of nuclei in the melted material and their growth into large grains. According to a further aspect, the invention includes a re-crystallization chamber in an overall process flow that enables high-throughput processing of silicon sheets having desired properties for applications such as photovoltaic modules.Type: GrantFiled: December 13, 2006Date of Patent: August 4, 2009Assignee: Applied Materials, Inc.Inventors: Virendra V. Rana, Robert Z. Bachrach
-
Patent number: 7557374Abstract: An embodiment of the invention provides a substrate. The substrate comprises a single crystal substrate. An epitaxial buffer film is on the single crystal substrate. An epitaxial ZnGa2O4 is on the epitaxial buffer film.Type: GrantFiled: January 25, 2007Date of Patent: July 7, 2009Assignee: Industrial Technology Research InstituteInventors: Yan-Ru Lin, Song-Yeu Tsai
-
Patent number: 7547914Abstract: The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline first layer of the first material and on one part of the second material that is around said aperture. Finally, the process includes recrystallization annealing of the first material. Thus, it is possible to produce, within one and the same wafer, either transistors on a germanium-on-insulator substrate with transistors on a silicon-on-insulator substrate, or transistors on a germanium-on-insulator substrate with transistors on a silicon substrate.Type: GrantFiled: January 16, 2007Date of Patent: June 16, 2009Assignee: STMicroelectronics (Crolles 2) SASInventors: Olivier Kermarec, Yves Campidelli, Guillaume Pin
-
Publication number: 20090140255Abstract: An island of a crystalline semiconductor according to the present invention has an upper surface and a sloped side surface, which are joined together with a curved surface. Crystal grains in a body portion of the island, including the upper surface, and crystal grains in an edge portion of the island, including the sloped side surface, both have average grain sizes that are greater than 0.2 ?m.Type: ApplicationFiled: June 21, 2005Publication date: June 4, 2009Applicant: SHARP KABUSHIKI KAISHAInventors: Tomohiro Kimura, Takuto Yasumatsu
-
Publication number: 20090121231Abstract: Aspects of the invention relate to thin film transistors, a method of fabricating the same, and an organic light-emitting diode device using the same. A thin film transistor according to an aspect of the invention includes a semiconductor layer formed from polysilicon in which a grain size deviation is within a range of substantially ±10%. Accordingly, aspects of the invention can improve non-uniformity of image characteristics due to a non-uniform grain size in polysilicon produced by a sequential lateral solidification (SLS) crystallization process.Type: ApplicationFiled: November 13, 2008Publication date: May 14, 2009Applicant: Samsung SDI Co., Ltd.Inventors: Kyoung-Bo KIM, Yong-Woo Park, Chang-Young Jeong, Sung-Won Doh, Dae-Woo Lee, Jong-Mo Yeo
-
Patent number: 7528408Abstract: To improve the laser annealing process for polycrystallizing amorphous silicon to form silicon thin films having large crystal particle diameters at a high throughput, the present invention is directed to a process of crystallization by irradiation of a semiconductor thin film formed on a substrate with pulsed laser light. The process comprises having a means to shape laser light into a linear beam and a means to periodically and spatially modulate the intensity of pulsed laser in the direction of the long axis of the linear beam by passing through a phase-shifting stripy pattern perpendicular to the long axis, and collectively forming for each shot a polycrystalline film composed of crystals which have grown in a certain direction over the entire region irradiated with the linear beam.Type: GrantFiled: January 31, 2006Date of Patent: May 5, 2009Assignee: Hitachi, Ltd.Inventors: Kazuo Takeda, Jun Gotou, Masakazu Saito, Makoto Ohkura, Takeshi Satou, Hiroshi Fukuda, Takeo Shiba
-
Patent number: 7521712Abstract: A thin film semiconductor device is provided that includes a semiconductor thin film and a gate electrode. The semiconductor thin film has an active region turned into a polycrystalline region through irradiation with an energy beam. The gate electrode is provided to traverse the active region. In a channel part that is the active region overlapping with the gate electrode, a crystalline state is changed cyclically in a channel length direction, and areas each having a substantially same crystalline state traverse the channel part.Type: GrantFiled: March 13, 2007Date of Patent: April 21, 2009Assignee: Sony CorporationInventors: Akio Machida, Toshio Fujino, Tadahiro Kono
-
Publication number: 20090078940Abstract: A structure with location-controlled crystallization of an active semiconductor film using a crystal seed has been provided, along with an associated fabrication method. The method forms a first semiconductor film overlying a substrate having a crystallographic orientation. Typically, the structure is polycrystalline or single-crystal. The first semiconductor film is selectively etched, forming a seed region. An insulator is formed with an opening, exposing the seed region. An amorphous second semiconductor film is formed over the insulator layer. The second semiconductor film is laser annealed, partially melting the seed region. Crystal grains are laterally grown in the second semiconductor film having the same crystallographic orientation as the seed region. In TFT fabrication an etching is typically performed to remove the second semiconductor film overlying the seed region, and a transistor active region is formed in the remaining second semiconductor film.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Themistokles Afentakis, Robert S. Sposili, Apostolos T. Voutsas
-
Publication number: 20090057677Abstract: A method for fabricating a ferroelectric device includes Step S1 of forming a polycrystalline electrode on or above a substrate in which a MOS transistor is formed, Step S2 of performing metal organic chemical vapor deposition to form an amorphous film of bismuth titanate on the polycrystalline electrode, and Step S3 of performing annealing at a temperature in a predetermined range to make the amorphous film be a polycrystalline ferroelectric film made up of a large number of bismuth titanate having a layered perovskite structure. Step S3 includes a sub-step of increasing a temperature of the amorphous film to a lower limit of the predetermined temperature range at a temperature increase rate at which crystal nuclei are not grown.Type: ApplicationFiled: August 18, 2008Publication date: March 5, 2009Inventors: Kazunori ISOGAI, Akihiro KAMADA