Abstract: A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.

Abstract: A charge or carrier injection transistor including a substrate, a gate electrode and an electric potential barrier layer forming an electric potential barrier against charges (either holes or electrons) injected by the gate electrode towards the substrate. A source and a drain are formed in the substrate on opposite sides of the gate electrode. A conduction channel, between the source and the drain, is formed on the substrate by charges passing through the electric potential barrier by a voltage applied to the gate electrode. When the applied voltage is removed, this channel disappears. That is, the transistor is ON when the charges from the gate electrode pass through the electric potential barrier and is OFF when no charges pass through it, thereby the charges perform a transistor switching function.

Abstract: A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer.

Abstract: An insulated gate field-effect transistor or similar semiconductor-insulator-semiconductor structure has an increased time-dependent dielectric failure lifetime due to a reduction in the field across the gate insulator. The electric field in the gate insulator is reduced without degrading device performance by limiting the field only when the gate voltage exceeds its nominal range. The field is limited by lowering the impurity concentration in a polysilicon gate electrode so that the voltage drop across the gate insulator is reduced. In order to avoid degrading the device performance when the device is operating with nominal voltage levels, a fixed charge is imposed at the interface between the gate electrode and the gate insulator, so at a gate voltage of about the supply voltage level the response changes to exhibit less increase in the drop across the gate insulator for higher voltages.

Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.

Abstract: A layer of dopant is implanted in the passivation of a semiconductor die to facilitate testing of the die by a scanning electron microscope voltage contrast system. The layer of dopant is capacitively coupled to circuits under the passivation and is coupled to ground to allow charge to bleed to ground through a high resistivity path. The resistivity is low enough to allow E-beam charge bleed off, but not bleed off of higher frequency capacitive coupled signals. The disclosure is also applicable to photo generated electron voltage contrast.

Abstract: A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.