Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: A semiconductor device includes a lead terminal that has an island at one end, a semiconductor element whose bottom surface is connected to the island, one or more wires that connect a top surface of the semiconductor element to the island, and a resin seal that seals in the semiconductor device and the wires. In the island, a cut is formed between a section on which one semiconductor element is mounted and a section on which the wires are bonded.

Abstract: A silicon substrate material based on silicon has a semi-insulating interior layer isolating the bulk of the substrate material from the top layers, where integrated circuits are to be built. The semi-insulating layer is created by producing submicron particles having Schottky barriers or pn-hetero-barriers and distributing the particles so that the depletion regions then produced around neighbouring particles overlap. Such particles will then deplete the silicon material from electric charge carriers. The substrate material can then be processed using the standard silicon processing methods and allows integrated circuits to be manufactured which are suitable for high frequency applications. A silicon substrate is made by sputtering a metal such as Co in a silicon wafer and then silicidizing the sputtered Co atoms by means of an annealing treatment. A top silicon wafer having a silicon dioxide layer at its bottom surface is then bonded to the sputtered layer.

Abstract: An interlevel dielectric stack for use in semiconductor devices is provided. The interlevel stack includes a bottom adhesion layer, a middle layer composed of a fluorinated amorphous carbon film, and a top adhesion layer. The bottom and top adhesion layers are composed of a silicon carbide material containing hydrogen. The dielectric stack is subjected to rigorous adhesion and thermal testing. A single continuous process for depositing the dielectric stack in a high density plasma reactor is also provided.

Abstract: A semiconductor device having at least a first and second type of devices formed in the substrate of the semiconductor device and having a hydrogen free barrier layer formed by implanting nitrogen into a layer of amorphous silicon or polysilicon formed on the surface of the semiconductor device. A hydrogen getter layer is formed on the semiconductor device under the barrier layer. The hydrogen getter layer is removed from portions of the semiconductor device on which salicide layers are to be formed.

Abstract: A method for making a highly reliable non-single-crystal silicon thin film transistor, in which an underlying SiO.sub.2 film 15 is formed on a glass substrate 14 and then a polycrystalline silicon layer 17 is formed thereon. After patterning the polycrystalline silicon layer 17, a gate SiO.sub.2 film 18 is formed by an ECR-PECVD process or a TEOS-PECVD process. A gate electrode 19 is formed and source and drain regions 20, 20 are formed by an ion doping process. After forming a SiO.sub.2 insulating interlevel film 21 and providing a contact hole 22, an electrode 23 composed of an Al--Si--Cu film is formed. Finally, it is subjected to wet annealing at a temperature of 350.degree. C. for 3 hours.

Abstract: A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material selected from the group consisting of silicon-rich nitride, silicon-rich oxide, carbon-rich nitride, silicon carbide, boron nitride, organic spin-on-glass, graphite, diamond, carbon-rich oxide, nitrided oxide, and organic polymer. The stopping layer (110) promotes better semiconductor device (100) performance by contributing to greater selectivity with respect to an etch process used to remove an insulating layer (112) formed overlying the stopping layer (110).

Abstract: The present invention, in one embodiment provides for use in a semiconductor device having a metal or dielectric layer located over a substrate material, a method of forming an anti-reflective layer on the metal layer and a semiconductor device produced by that method. The method comprises the steps of forming a dielectric layer, such as an amorphous silicon, of a predetermined thickness on the metal layer or dielectric and forming a gradient of refractive indices through at least a portion of the predetermined thickness of the dielectric layer by an oxidation process to transform the dielectric layer into an anti-reflective layer having a radiation absorption region and a radiation transmission region. In advantageous embodiments, the dielectric layer may be a substantially amorphous, non-stacked silicon layer. Additionally, the thickness of the dielectric layer may range from about 4.5 nm to about 150 nm.

Abstract: A metal film with high melting point containing such nitrogen as titanium nitride is disposed on the interface between an amorphous carbon fluoride film and a metal. A structure is obtained from the function of a nitrogen-containing metal film with high melting point which prevents fluorine dispersion, to prevent such problems as the reaction of a metal and fluorine at heating process and the following falling or swelling of the metal film can be solved. In addition, the heating process possible to introduce in the manufacturing steps allow to complete the LSI making process of a practical multilayer wiring structure on the basis of a low dielectric constant of amorphous carbon.

Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described and include a layer of amorphous silicon for passivating and terminating the device junctions. The layer of amorphous silicon is deposited atop the metal contact and atop and overlying insulation layer and expose the source pad. A layer of silicon nitride may be deposited atop the layer of amorphous silicon. The layer of amorphous silicon minimizes gate leakage.

Abstract: A semiconductor device in which inner leads among a plurality of leads are arranged on a circuit formation face of a semiconductor chip encapsulated by a resin encapsulating body and bonding pads formed on the circuit formation face of the chip and the inner leads are electrically connected. An adhesive is selectively applied only to the inner leads on the outermost sides arranged on both ends of the chip among the plurality of inner leads. The circuit formation face of the chip and the inner leads of the selected leads are joined with the adhesive Each of the selected leads has a step on the main face of the semiconductor chip and the leads except for the selected leads have almost straight shapes without being processed to have steps.

Abstract: A plastic-encapsulated semiconductor device is provided, which makes it possible to reinforce the power/ground line by a bus-bar without using the over-lead bonding technique.

Abstract: A semiconductor device which is greatly reliable and is also advantageous in high-density mounting, as well as the method for producing the semiconductor device, includes a filmy material placed along the peripheral sides of the semiconductor chip and along one surface of the semiconductor chip. The conductor pattern is provided on the filmy material such that one end of the pattern is connected to the corresponding electrode which has been provided on the other surface of the semiconductor chip and the other end is opposed to the back of the semiconductor chip. Hereby a semiconductor device can be realized which is greatly reliable and is also advantageous for high-density mounting. Besides, the semiconductor device is produced in such a way that a cutting and bending process of each lead and the film tape is performed toward the tape carrier package, so that the other end of each lead is opposed to the back of the semiconductor chip, holding the film tape between them.

Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (V.sub.th) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si--H chemical bonds at the interface.

Abstract: A multi-layer structure inserted onto an interface between a compound semiconductor region and a highly resistive material region includes an epitaxial silicon layer up to 1.5 nm thick in contact with the compound semiconductor region and an amorphous silicon layer from 1 to 10 nm thick in contact with the highly resistive material region and laminated on the epitaxial silicon layer.

Abstract: A process for forming a structure including an epitaxial layer of a oxide material such as yttria-stabilized zirconia on a thick layer of amorphous silicon dioxide having a thickness of at least about 500 Angstroms on a single crystal silicon substrate and the resultant structures derived therefrom are provided.

Abstract: The present invention provides a composite passivation film deposited at low temperatures (<150.degree. C.). A hydrogenated amorphous silicon nitride (a-SiN.sub.x :H) film is formed over a semiconductor device. Then a very thin layer (>6.4 nm) of an amorphous silicon hydrogen (a-Si:H) film is formed over the a-SiN.sub.x :H film. Such a composite passivation film can prevent semiconductor devices from oxidation due to percolation of moisture, and maintain the electric properties and stability of the semiconductor devices.

Abstract: A protective insulating film in a semiconductor device is formed in a multi-layer structure. A lower layer portion is constituted by an organic-silane-based silicon oxide film formed by a P-CVD process using organic silane and oxygen to improve step coverage. An upper layer portion is constituted by a silane-based silicon oxide film containing excess silicon in an amount greater than that in the stoichiometric composition and formed by a P-CVD process to improve moisture resistance.

Abstract: A semiconductor device, in which wiring layers are electrically isolated from each other by an insulating film which includes an amorphous carbon fluoride film insulating film containing carbon and fluorine as main components and the wiring layers are electrically connected to each other by a conductive material buried in a hole penetrating through the insulating film, is manufactured by selectively etching the amorphous carbon fluoride film. Moreover, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on both of the amorphous carbon fluoride film and a side surface of said hole, or one of the amorphous carbon fluoride film and the side surface thereof.

Abstract: A semiconductor device in which dry etching properties are rendered compatible with satisfactory anti-reflection characteristics in far-infrared lithography the semiconductor device has a semiconductor substrate and an electrode and wire pattern on the substrate. The semiconductor device also has an anti-reflective layer on the substrate which presents a variation in the composition of a constituent element along the film thickness over the semiconductor substrate. The anti-reflective layer is selected from the group consisting of SiO.sub.x, SiN.sub.x and Si.sub.x O.sub.y N.sub.z.

Abstract: A barrier layer impedes hydrogen diffusion into polysilicon resistors in circuits in which the resistor resistivity is sensitive to hydrogen diffusion into the resistors. The barrier layer extends laterally throughout the whole integrated circuit except for contact areas in which circuit elements overlying the barrier layer contact conductive elements underlying the barrier layer. The barrier layer includes a layer of polysilicon or amorphous silicon. In some embodiments, the barrier layer includes multiple layers of polysilicon or amorphous silicon that are separated by thin layers of silicon dioxide. In some embodiments, the barrier layer is formed between the polysilicon resistor and PECVD silicon nitride passivation which contains atomic hydrogen.

Abstract: A resin or amorphous carbon layer is coated on a substrate and then fluorinated by exposing it in a F.sub.2 gas atmosphere. The thus fluorinated resin or amorphous carbon layer can be excellent in dielectric constant and thermal resistance. The resin may be photo-sensitive so that the resin can be patterned before the fluorination. Alternatively, the resin can be fluorinated before patterning.

Abstract: The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.

Abstract: A semiconductor device comprising at least one SiC semiconductor layer; and passivation layers applied on at least a portion of a surface of the SiC semiconductor layer for passivation thereof; the passivation layers comprising at least a substantially insulating layer comprising crystalline AlN and placed next to the SiC semiconductor layer and a semi-insulating layer allowing a weak current to flow therein in a blocking state of the device; wherein the semi-insulating layer comprises at least one first sub-layer and at least one second sub-layer, the at least one first sub-layer having a smaller gap between a conduction band and a valence band thereof than the at least one second sub-layer and the at least one second sub-layer having dopants for auto-ionization thereof by transport of charge carriers thereof to a deeper energy state in the semi-insulating sub-layer.

Abstract: A method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises formation of a polysilicon 1 layer on said semiconductor substrate. The polysilicon 1 layer is patterned and etched. An interpolysilicon layer is formed over the polysilicon 1 layer, patterned and etched forming an opening through the interpolysilicon layer exposing a contact area on the surface of the polysilicon 1 layer. A SIPOS layer forms a resistor material over the interpolysilicon layer in contact with the polysilicon 1 layer through the opening. A load resistor mask is formed over a load resistor region to be formed in the SIPOS layer, and ions are implanted in the remainder of the SIPOS layer not covered by the load resistor mask to convert the remainder of the SIPOS layer from a resistor into an interconnect structure integral with a load resistor in the load resistor region.

Abstract: In a semiconductor device having a passivation layer, the passivation layer is made of benzocyclobutene polymer and silicon power.

Abstract: The invention provides a semiconductor device in which interlayer insulative layers are composed of amorphous carbon film. The amorphous carbon film may include fluorine (F) therein. The invention further provides a method of fabricating a semiconductor device including an interlayer insulative layer composed of amorphous carbon film including fluorine (F), the method having the step of carrying out plasma-enhanced chemical vapor deposition (PCVD) using a mixture gas including (a) at least one of CF.sub.4, C.sub.2 F.sub.6, C.sub.3 F.sub.8, C.sub.4 F.sub.8 and CHF.sub.3, and (b) at least one of N.sub.2, NO, NO.sub.2, NH.sub.3 and NF.sub.3. The method provides amorphous carbon film having superior heat resistance and etching characteristics. By composing interlayer insulative layers of a semiconductor device of the amorphous carbon film, the semiconductor device can operate at higher speed.

Abstract: An improved inter-metal dielectric structure having a low dielectric constant for reduced capacitive coupling between adjacent metal conductor strips is disclosed. The structure employs silicate glass that is heavily doped with fluorine atoms as the primary dielectric material. The primary dielectric material is encased in an insulative barrier film which has a high degree of impermeability to both fluorine atoms and water molecules. Although the preferred barrier material, silicon nitride, possesses a dielectric constant that is higher than undoped silicate glass, the thickness of the silicon nitride film is relatively insignificant compared to the thickness of the fluorine-doped silicate glass portion of the structure.

Abstract: A semiconductor device comprises at least one semiconductor layer (1-3) of SiC and a layer (6) applied on at least a portion of an edge surface (19) of said SiC-layer so as to passivate this edge surface portion. At least the portion of said passivation layer closest to said edge surface portion of the SiC-layer is made of a first crystalline material, and the passivation layer comprises a portion made of a second material having AIN as only component or as a major component of a crystalline alloy constituting said second material.

Abstract: A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.

Abstract: A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer.

Abstract: The present invention relates to semiconductor devices comprising as one of their structural components diamond-like carbon as an insulator for spacing apart one or more levels of a conductor on an integrated circuit chip. The present invention also relates to a method for forming an integrated structure and to the integrated structure produced therefrom. The present invention further provides a method for selectively ion etching a diamond-like carbon layer from a substrate containing such a layer.

Abstract: A semiconductor device has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type contacted by respective first and second electrodes. A semi-insulating layer extends between the first and second electrodes and there is a first insulating layer between the semi-insulating layer and the first semiconductor region. The sheet resistivity of the semi-insulating layer varies, and this improves the high breakdown voltage of the p-n junction of the semiconductor device between the first and second semiconductor layers, by acting as a shield for charges included on a passivation insulation layer covering the semi-insulating layer and the first and second electrodes. Third semiconductor regions, with corresponding third electrodes, extend around, and are spaced from, the second semiconductor region.

Abstract: A layered dielectric structure is provided, which separates a first layer of metal interconnects from each other in semiconductor devices and also separates the first layer from a second, overlying layer of metal interconnects for making electrical contact to the first layer of metal interconnects. The layered dielectric structure comprises: (a) a layer of an organic spin-on-glass material filling gaps between metal interconnects in the first layer of metal interconnects; (b) a layer of an inorganic spin-on-glass material to provide planarization to support the second layer of metal interconnects; and (c) a layer of a chemically vapor deposited oxide separating the organic spin-on-glass layer and the inorganic spin-on-glass layer. The layered dielectric structure provides capacitances on the order of 3.36 to 3.46 in the vertical direction and is about 3.2 in the horizontal direction. This is a reduction of 10 to 15% over the prior art single dielectric layer, using existing commercially available materials.

Abstract: A layer of amorphous silicon covers the top surface of a semiconductor wafer to act as a moisture and contaminant barrier and to prevent the formation of aluminum hillocks on the aluminum bonding pads for the source and gate electrodes of a power MOSFET or other power semiconductor device. The amorphous silicon is easily penetrated by wire bonding apparatus used to make wire bonds to the conductor pads beneath the amorphous silicon.

Abstract: This invention discloses a semiconductor device comprising a semiconductor substrate, a first conducting layer formed on the surface of the semiconductor substrate, an insulating layer formed above the semiconductor substrate, the insulating layer having a contact hole reaching the first conducting layer to expose it, a second conducting layer formed on the insulating layer, the sidewall of the contact hole, and the first conducting layer, and an anti-oxidation layer formed on at least part of the surface of the second conducting layer.

Abstract: A flash memory cell includes the usual thermal oxide layer deposited above the substrate including the source and the drain. On the thermal oxide layer, a silicon rich oxide layer is formed. Above the silicon rich oxide layer a gate structure is formed of layer of polysilicon separated by an intermediate dielectric layer. The lower polysilicon layer commences as an initial portion of the layer of small grain size followed by either amorphous or large grain size material.

Abstract: The invention is a semiconductor device having a metal-semiconductor contact structure. The device includes a metal region having such a high conductivity as to serve as a contact plug. The device also includes a first semiconductor region having a first band gap and being so doped with one conductive type dopant as to exhibit a high conductivity. The device also includes a semiconductor film having a second band gap wider than the first band gap. The semiconductor film is in contact at its opposite surfaces with a part of the metal region and a part of the first semiconductor region respectively. The semiconductor film is doped with the one conductive type dopant so heavily as to suppress electrical current flow between the part of the metal region and the part of the first semiconductor region through the semiconductor film. The semiconductor film comprises amorphous silicon or poly-crystalline silicon.

Abstract: There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer.

Abstract: A power semiconductor component having integrated protection against electrostatic destruction is published. Such a semiconductor component (1) comprises a semiconductor substrate (10) having at least one MOS structure whose gate (7) is arranged insulated from the semiconductor substrate (10). Such structures are susceptible to destruction by a dielectric breakdown of the insulation layer, caused by electrostatic charging. According to the invention, this insulating layer between-the gate electrode (3) and the main electrode (2) is now replaced by a semi-insulating layer (9) so that a limited current flow becomes possible between the gate (7) and the main electrode (2) and it is no longer possible for any potential difference to build up.

Abstract: The adhesion between a metallic silicide film and a dielectric layer of a semiconductor device is improved. Formed on a silicon substrate is a gate dielectric layer formed on which is a metallic silicide film. A silicon dielectric layer of a rich-in-silicon-content type, which have a silicon content higher than a silicon content according to the stoichiometric composition formula, is deposited on the metallic silicide film. Because of this arrangement, a semiconductor device which is free from film peeling and which has an electrode wire with a low electrical resistance is achievable without decreasing the concentration of impurity at an electrode. If a passivation silicon oxide layer whose composition is close to a composition according to the stoichiometric composition formula is formed on the silicon oxide layer of a rich-in-silicon-content type, the degradation of the inside of an electrode, and the degradation of a gate oxide layer both caused by unwanted impurities from the outside can be prevented.

Abstract: The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.

Abstract: A polyemitter structure having a thin interfacial layer deposited between the polysilicon emitter contact and the crystalline silicon emitter, as opposed to a regrown SiO.sub.x layer, has improved reproducibility and performance characteristics. A n-doped hydrogenated microcrystalline silicon film can be used as the deposited interfacial film between a crystalline silicon emitter and a polycrystalline silicon contact.

Abstract: A method of fabricating a semiconductor device, in particular of forming a polysilicon film on a step portion of an insulation film made by a trench or a contact hole is disclosed which includes the steps of depositing an amorphous silicon film on the step portion while doping impurities into the amorphous silicon film and carrying out heat treatment to convert the amorphous silicon film into a polycrystalline silicon film, thereby the polysilicon film on a step portion being formed.

Abstract: A thin film transistor is used as a load transistor in a memory cell in a SRAM. A load thin film transistor is arranged on an interlayer insulating layer on the surface of a silicon substrate. A silicon layer in which source/drain regions of the thin film transistor are formed is covered with an oxidation preventing film. An interlayer insulating layer which is to be subject to high temperature reflow processing is formed on the surface of the oxidation preventing film. The oxidation preventing film is formed of polycrystalline silicon, amorphous silicon, silicon nitride, or the like and formed on the silicon layer in the thin film transistor directly or through an insulating layer to cover the surface of the silicon layer.

Abstract: A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.

Abstract: A thin-film electroluminescence device has transparent electrodes formed on a transparent substrate, a lower dielectric layer formed on the substrate having the transparent electrodes, a luminescent layer formed on the lower dielectric layer, an upper dielectric layer formed on the luminescent layer, and back electrodes formed on the upper dielectric layer. At least one of the upper and lower dielectric layers includes a SiN:H film formed in contact with the luminescent layer by a plasma chemical vapor deposition method. The SiN:H film contains N--H bonds of 1.2.times.10.sup.22 /cm.sup.3 or less to control an amount of change in emission-start voltage to 30 V or less.

Abstract: An integrated circuit structure is presented that includes a substrate in which integrated circuit elements are constructed, a first interconnection metalization over the substrate interconnecting selected ones of the integrated circuit elements, and an oxide layer over the substrate and the first metal interconnection pattern. A glass layer over the oxide layer is substantially planar between portions that overlie the metalization and portions that do not over lie the metalization.

Abstract: A semiconductor device (10), comprising a semiconductor substrate (12) having a layer of semiconductor material (14) deposited, coated or grown epitaxially as a single crystal or polysilicon on the surface of the substrate. The layer of material is also a semiconductor material, having a higher resistivity than the substrate it is deposited on. A dielectric layer (16) of a metal oxide is formed on the high resistivity layer (14), which is then covered with an amorphous layer (18) of a metal oxide dielectric. Zirconium titanate may be used as a metal oxide dielectric layer. A metal electrode (20) is formed on the amorphous layer (18) to form a Metal Insulator Semiconductor device. In an alternative configuration, the amorphous layer (18) may instead be placed between the high resistivity layer (14) and the dielectric layer (16), or a second amorphous layer (22) may be added between the high resistivity layer and the dielectric layer.

Abstract: This invention discloses a semiconductor device comprising a semiconductor substrate, a first conducting layer formed on the surface of the semiconductor substrate, an insulating layer formed above the semiconductor substrate, the insulating layer having a contact hole reaching the first conducting layer to expose it, a second conducting layer formed on the insulating layer, the sidewall of the contact hole, and the first conducting layer, and an anti-oxidation layer formed on at least part of the surface of the second conducting layer.