Abstract: There is provided a method of performing a surface processing on a substrate having a metal layer formed on a bottom portion of a recess formed in an insulating film, the method including: supplying a halogen-containing gas into a processing chamber in which the substrate is loaded; and removing a metal oxide from the bottom portion of the recess using the halogen-containing gas.

Abstract: A microfluidic device for use with a microfluidic delivery system, such as an organic vapor jet printing device, includes a glass layer that is directly bonded to a microfabricated die and a metal plate via a double anodic bond. The double anodic bond is formed by forming a first anodic bond at an interface of the microfabricated die and the glass layer, and forming a second anodic bond at an interface of the metal plate and the glass layer, where the second anodic bond is formed using a voltage that is lower than the voltage used to form the first anodic bond. The second anodic bond is formed with the polarity of the voltage reversed with respect to the glass layer and the formation of the first anodic bond. The metal plate includes attachment features that allow removal of the microfluidic device from a fixture.

Abstract: The invention relates to an anodic bonding method for bonding two elements with an intermediate layer. The invention especially, but not exclusively, relates to an anodic bonding method for between a metallic element and a heterogeneous element, for example a glass, artificial sapphire or ceramic element. The specificity and aim of the present invention is to produce an assembly that is gas-tight and fluid-tight, solderless, brazing- or welder-free and without organic compound (glue). The present method has multiple industrial applications, including making it possible to attach a watch-glass, typically made of mineral glass, sapphire or transparent or translucent ceramics, to a bezel or case middle of a watch case using the anodic bonding technique.

Abstract: A microelectronic device includes a chip housing a functional part and carrying first electrical contact regions in electrical connection with the functional part through first protected connections extending over or in the chip. A substrate has a first contact area and a second contact area, which is remote from the first contact area. The first contact area carries second electrical contact regions, and the second contact area carries external connection regions. The second contact regions and the external connection regions are in mutual electrical connection through second protected connections extending over or in the substrate. A protection-ring structure surrounds the first and second electrical contact regions and delimits a first chamber closed with respect to the outside. The first electrical contact regions and the second electrical contact regions are in mutual electrical contact.

Abstract: A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the insulating layer to form trenches for receiving a metal, depositing one or more sacrificial layers, and etching portions of the one or more sacrificial layers to expose a top surface of the metal of one or more of the trenches. The method further includes selectively depositing an electrode over the top surface of the exposed metal and nitridizing the electrode to form a diffusion barrier between chip components and the metal.

Abstract: According to an embodiment, a method of manufacturing a group III-V semiconductor device includes forming a gate contact that includes an electrode stack including a first titanium layer, an aluminum layer over the first titanium layer, and a second titanium layer over the aluminum layer, and forming a biased reactive capping layer over the second titanium layer. The biased reactive capping layer includes biased reactive titanium nitride. The gate contact is a gate electrode that makes Schottky contact with the group III-V semiconductor device.

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.

Abstract: A resin-sealed semiconductor device 10 of the present invention includes: a mesa-type semiconductor element 100 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin 40 which seals the mesa-type semiconductor element 100, wherein the mesa-type semiconductor element 100 includes a glass layer which substantially contains no Pb as the glass layer. The resin-sealed semiconductor device of the present invention can acquire higher resistance to a reverse bias at a high temperature than a conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device of the present invention has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device.

Abstract: A glass composition for protecting a semiconductor junction contains at least SiO2, B2O3, Al2O3, ZnO, and at least two oxides of alkaline earth metal selected from the group consisting of CaO, MgO and BaO, and substantially contains none of Pb, P, As, Sb, Li, Na and K.

Abstract: Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device.

Abstract: [Problem] To provide a composite substrate which includes a silicon substrate having few lattice defects. [Solution] A composite substrate (50) that comprises a first substrate (10), which is constituted of a semiconductor material, a second substrate (40), which is constituted of an insulating material, and an oxide layer (30) and a semiconducting epitaxial layer (20) which have been disposed between the substrates (10) and (40) in this order from the second substrate (40) side, the oxide layer (30) having oxygen atoms arranged on the side thereof which faces the epitaxial layer (20).

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming semiconductor layers in a plurality of first regions on a semiconductor wafer. The plurality of first regions are separated from each other. The method includes forming elements in the semiconductor layers. The method includes bonding an insulating plate made of an inorganic material in a second region on the semiconductor wafer. The second region excludes the first regions. The method includes performing singulation for each of the semiconductor layers by cutting the semiconductor wafer and the insulating plate along a dicing line configured to pass through only the second region.

Abstract: A light-emitting device includes a substrate, a plurality of light-emitting elements mounted on one surface of the substrate, a first glass film provided to one surface of the substrate and having a plurality of apertures that form a light-reflecting frame surrounding the perimeter of each the light-emitting elements, and a second glass film provided to the other surface of the substrate. A coefficient of thermal expansion of the second glass film is greater than that of the substrate when a coefficient of thermal expansion of the first glass film is greater than that of the substrate, and a coefficient of thermal expansion of the second glass film is less than that of the substrate when a coefficient of thermal expansion of the first glass film is less than that of the substrate.

Abstract: A photosensitive glass paste that can be fired at a low temperature for a short period of time and that can suppress generation of voids and diffusion of Ag in glass layers formed by firing, and a high-performance multilayer wiring chip component manufactured by using the above photosensitive glass paste are provided. As a sintering aid glass which is combined with a ceramic aggregate and a primary glass, a glass having a contact angle to the ceramic aggregate smaller than that of the primary glass to the ceramic aggregate is used, and the content of the sintering aid glass is set to 5 to 10 percent by volume of the inorganic component. As the sintering aid glass, a glass containing SiO2, B2O3, CaO, Li2O, and ZnO at a predetermined ratio is preferably used. As the primary glass, a glass containing 70 to 90 percent by weight of SiO2, 15 to 20 percent by weight of B2O3, and 1 to 5 percent by weight of K2O can be used.

Abstract: A chip package structure for being disposed on a carrier includes a package substrate and a chip. The package substrate includes a laminated layer, a patterned conductive layer, a solder-mask layer, at least one outer pad and a padding pattern. The patterned conductive layer is disposed on a first surface of the laminated layer and has at least one inner pad. The solder resist layer is disposed on the first surface and has at least one opening exposed the inner pad. The outer pad is disposed on the solder resist layer, located within the opening, and is connected with the inner pad. The padding pattern is disposed on the solder resist layer. A height of the padding pattern relative to the first surface is greater than that of the outer pad. The chip is located on a second surface of the laminated layer and electrically connected to the package substrate.

Abstract: A glass composition for protecting a semiconductor junction contains at least SiO2, Al2O3, MO, and nickel oxide, and substantially contains none of Pb, P, As, Sb, Li, Na and K (M in MO indicates one of alkali earth metals).

Abstract: A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

Abstract: Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.

Abstract: Embodiments are directed to an apparatus and fabrication method to form pad arrays on the edge of a substrate wafer substrate. Embodiments of the invention make it possible for surface mount devices to be bonded vertically (i.e. on their side) using standard semiconductor assembly processes.

Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: A glass to be used in a scattering layer of an organic LED element, and an organic LED element using the scattering layer are provided. The organic LED element of the present invention includes, a transparent substrate, a first electrode provided on the transparent electrode, an organic layer provided on the first electrode, and a second electrode provided on the organic layer, and further includes a scattering layer including, in terms of mol % on the basis of oxides, 15 to 30% of P2O5, 5 to 25% of Bi2O3, 5 to 27% of Nb2O5, and 10 to 35% of ZnO and having a total content of alkali metal oxides including Li2O, Na2O and K2O of 5% by mass or less.

Abstract: New photoresists are provided that comprise a multi-keto component and that are particularly useful for ion implant lithography applications. Preferred photoresists of the invention can exhibit good adhesion to underlying inorganic surfaces such as SiON, silicon oxide, silicon nitride, hafnium silicate, zirconium silicate and other inorganic surfaces.

Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.

Abstract: A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6—Si—O—Si—R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12—Si—O—Si—R13R14—O—Si—R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.

Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P?N junction diode. The P?N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

Abstract: A component for an information display device has a transparent substrate having a surface that has a first refractive index. The surface is selectively coated in a pattern comprising a transparent electrically conductive layer disposed at least at a first region of the surface and at a second region of the surface. The first region of the surface is separated from the second region by a third region that is devoid of the transparent conductive layer. The transparent conductive layer has a second refractive index that is higher than the first refractive index. The first, second and third regions are commonly overcoated with a transparent layer comprising non-conductive nanoparticles, the overcoating layer being disposed over the transparent conductive layer at the first and second regions and also disposed over the third region that is devoid of the transparent conductive layer. The refractive index of the layer comprising nanoparticles is higher than the first refractive index.

Abstract: A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed.

Abstract: A semiconductor device having improved adhesiveness between films composing an interlayer insulating film is presented by providing multilayered films in the interlayer insulating films having film density distribution, in which the film density is gradually changes. A SiOC film is deposited to a thickness of 300 nm via a plasma CVD process, in which a flow rate of trimethylsilane gas is stepwise increased. In this case, the film density of the deposited SiOC film is gradually decreased by stepwise increasing the flow rate of trimethylsilane gas. Since trimethylsilane contains methyl group, trimethylsilane has more bulky molecular structure in comparison with monosilane or the like. Thus, the film density is decreased by increasing the amount of trimethylsilane in the reactant gas.

Abstract: A material for passivating a dielectric layer in a semiconductor device has a molecular structure permitting or at least promoting liquid phase metal deposition thereon in a subsequent process step. The contemplated material may be constituted by multiple organic components. A semiconductor device including a layer of the passivating coupling material, and a method of manufacturing such a semiconductor device are also contemplated.

Abstract: A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stacking of the components is determined to establish interfaces between the adjacent components. A hydrogen-free amorphous film is applied to one of the component surfaces at each interface comprising an adjacent: glass component; and conductive or semiconductive component. A sol gel with or without alkaline ions film is applied to one of the component surfaces at each interface comprising an adjacent: conductive or semiconductive component; and conductive or semiconductive component. The components are simultaneously anodically bonded in the determined order of stacking.

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract: A semiconductor structure is provided. The semiconductor structure is disposed on the scribe line of a wafer and is around the chip area of the wafer. The semiconductor structure includes a plurality of dielectric layers sequentially disposed on the scribe line and a plurality of metal patterns disposed in each dielectric layer. The metal patterns disposed in each dielectric layer extend to the next underlying dielectric layer.

Abstract: A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a first insulating material layer over the first conductive layer; d) etching through the first insulating layer and the first conductive layer to the substrate to both form a plurality of first conductive lines from the first conductive layer and provide a plurality of grooves between the first lines, the first lines being capped by first insulating layer material, the first lines having respective sidewalls; e) electrically insulating the first line sidewalls; and f) after insulating the sidewalls, providing the grooves with a second conductive material to form a plurality of second lines within the grooves which alternate with the first lines. Integrated circuitry formed according to the method, and other methods, is also disclosed.

Abstract: A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (c) flowing a second carrier gas at a second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, and (d) flowing a silicon source material at a silicon source flow rate. The second carrier gas flow rate is greater than the first carrier gas flow rate.

Abstract: A low relative permittivity SiOx film excellent in heat resistance without using an alkali metal, fluorine, etc., a method for modifying an SiOx film to accomplish a further reduction of the relative permittivity of the low relative permittivity SiOx film and further to increase the insulating property, a highly reliable semiconductor device free from crack or peeling of the film by employing the low relative permittivity SiOx film as an interlayer insulating film for metal wirings, are provided. The low relative permittivity film is characterized in that it is made of a porous material, the major constituent of which is SiOx (where 1.8?X?1.0), and the relative permittivity at 1 MHz is at most 2.3.

Abstract: There is disclosed a coating material formulation for layering a plurality of electrodes to provide a substrate for the electrochemical synthesis of organic oligomers. Specifically, there is disclosed a coating layer of from about 0.5 to about 100 microns thick and is composed of a mixture of controlled porosity glass (CPG) particles having an average particle size of from about 0.25 to about 25 microns, and a thickening agent.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.

Abstract: Support matrices for semiconductors are often encapsulated in a region of the bonding leads, the so-called bonding channel. The encapsulation is effected using a dispensable material that can flow onto the support matrix and causes contamination there. In order to prevent this flow, the support matrix for integrated semiconductors has a frame, conductor track structures and at least one bonding channel. In the bonding channel bonding leads or wires for connecting the conductor track structures to the integrated semiconductor are disposed. Disposed along the edge of the bonding channel a barrier for preventing the flow of flowable material from the bonding channel onto the frame and/or the conductor track structures. A method for producing such support matrices is likewise disclosed.

Abstract: A marked wafer includes a front-side surface and a back-side surface. A vertical scribe line and a horizontal scribe line are on the front-side surface of the wafer. A back-side alignment mark is located at an intersection of the vertical scribe line and the horizontal scribe line. The back-side alignment mark extends from the front-side surface to the back-side surface of the wafer. The back-side alignment mark is used to aligning a saw, which singulates the wafer from the back-side surface.

Abstract: A semiconductor device capable of inhibiting a conductive plug from increase of resistance or disconnection resulting from moisture discharged from a first insulator film while reducing the capacitance between adjacent first interconnection layers is obtained. This semiconductor device comprises a plurality of first interconnection layers formed on a semiconductor substrate at a prescribed interval, a first insulator film, formed to fill up the clearance between the plurality of first interconnection layers, having an opening reaching the first interconnection layers and a conductive plug charged in the opening of the first insulator film and formed to be in contact with the first interconnection layers. An impurity is selectively introduced into a first region of the first insulator film in the vicinity of contact surfaces between the first interconnection layers and the conductive plug, thereby selectively modifying the first region of the first insulator film.

Abstract: This invention relates to a method of fabricating a light modulation system having a semiconductor substrate. In one exemplary method, an optical layer is applied over a semiconductor substrate which includes a plurality of integrated circuits. Each of these integrated circuits is capable of creating a separate display device. A protective layer is then applied over the optical layer. The plurality of integrated circuits is then singulated. Various other embodiments of apparatuses and methods are disclosed.

Abstract: Low-k dielectric materials have desirable insulating characteristics for use in insulating sub micron conductors in semiconductor devices. However, certain physical and material characteristics of the low-k dielectric materials make them difficult to work with. More particularly, the soft, porous, leakage-prone characteristics of low-k materials makes it difficult to accommodate electrical contacts for electrical probing to conductors covered by such materials. The present invention provides methods and structures for facilitating the electrical probing of semiconductor device conductors insulated by overlying low-k layers of dielectric material.

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract: A method for creating a refractory metal and refractory metal nitride cap effective for reducing copper electromigration and copper diffusion is described. The method includes depositing a refractory metal nucleation layer and nitriding at least the upper portion of the refractory metal layer to form a refractory metal nitride. Methods to reduce and clean the copper lines before refractory metal deposition are also described. Methods to form a thicker refractory metal layer using bulk deposition are also described.

Abstract: A fluorine-doped silica glass (FSG) dielectric layer includes a number of sublayers. Each sublayer is doped with fluorine in such a way that the doping concentration of fluorine in the sublayer decreases as one moves from an interior region of the sublayer towards one or both of the interfaces between the sublayer and adjacent sublayers. This structure reduces the generation of HF when the layer is exposed to moisture and thereby improves the stability and adhesion properties of the layer. The principles of this invention can also be applied to dielectric layers doped with such other dopants as boron, phosphorus or carbon.

Abstract: A MOSFET and the method for fabricating them are disclosed to make the inkjet head chips. The MOSFET has the scaled-down junction formation for the source and drain. Using a lower temperature process and interlayer dielectric, the source and drain dopants can not be diffused deeply due to high-temperature driver-in. The contact holes of the drain are provided with plugs of refractory material to avoid spiking between the metal and silicon. This achieves the requirement of high-density devices on the print head chip.

Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

Abstract: An optical semiconductor device includes a laminated layer structure, an intermediate film formed on an end surface of the laminated layer structure, and a passivation film formed on the intermediate film. The passivation film has a quantity of ion projection than that of the intermediate film.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).