With Dam Or Vent For Encapsulant Patents (Class 257/667)
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Publication number: 20120248589Abstract: A lead frame used in semiconductor packaging has an outer dam bar and inner leads that extend away from the dam bar. The inner leads have distal ends and tips at the distal ends. Each inner lead has a coined area on a first major surface at the distal end and spaced from the tip. The coined area and the spacing of the coined area from the tip form a shoulder structure. The coined area is configured to receive one end of a bond wire that interconnects the inner lead with a wire bond pad of a semiconductor die. The shoulder structure creates a molding compound locking mechanism to reduce shear stress and delamination in the lead bonding area.Type: ApplicationFiled: February 16, 2012Publication date: October 4, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Jinquan WANG, Yuan YUAN
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Publication number: 20120235286Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.Type: ApplicationFiled: May 31, 2012Publication date: September 20, 2012Applicant: MICRON TECHNOLOGY, INC.Inventor: Stephen L. James
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Publication number: 20120228753Abstract: A method of manufacturing of an integrated circuit packaging system includes: providing a bottom package in a cavity in a central region of the bottom package having inter-package interconnects in the cavity; forming a vent on an inter-package connection side of the bottom package from an exterior of the bottom package to the cavity; mounting a top package on the inter-package interconnects; and applying an underfill through the vent and into the cavity.Type: ApplicationFiled: March 10, 2011Publication date: September 13, 2012Inventors: Chan Hoon Ko, SeungYun Ahn
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Patent number: 8258612Abstract: A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.Type: GrantFiled: November 9, 2010Date of Patent: September 4, 2012Assignee: STATS ChipPAC Ltd.Inventors: Heap Hoe Kuan, Rui Huang, Yaojian Lin, Seng Guan Chow
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Patent number: 8258019Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 30, 2008Date of Patent: September 4, 2012Assignee: Intel CorporationInventors: Weng Khoon Mong, A. Vethanayagam Rudge, Bok Sim Lim, Mun Leong Loke, Kang Eu Ong, Sih Fei Lim, Tean Wee Ong
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Patent number: 8252683Abstract: Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove.Type: GrantFiled: September 9, 2010Date of Patent: August 28, 2012Assignee: Electronics and Telecommunications Research InstituteInventor: Kwon-Seob Lim
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Patent number: 8252615Abstract: An integrated circuit package system that includes: providing a support structure including an integrated circuit and an electrical contact adjacent thereto; providing a first mold having a first cavity with a projection and a recess for collecting flash; engaging the first mold on the support structure with the first cavity over at least a portion of the integrated circuit and the projection and the recess between the at least a portion of the integrated circuit and the electrical contact; and injecting encapsulation material into the first cavity.Type: GrantFiled: December 22, 2006Date of Patent: August 28, 2012Assignee: Stats Chippac Ltd.Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
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Method and apparatus for directing molding compound flow and resulting semiconductor device packages
Patent number: 8207599Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.Type: GrantFiled: March 15, 2011Date of Patent: June 26, 2012Assignee: Micron Technology, Inc.Inventor: Stephen L. James -
Patent number: 8203199Abstract: A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.Type: GrantFiled: December 10, 2009Date of Patent: June 19, 2012Assignee: National Semiconductor CorporationInventors: Lee Han Meng Eugene Lee, Kuan Yee Woo
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Patent number: 8183088Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: June 25, 2010Date of Patent: May 22, 2012Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Byoung-Ok Lee
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Patent number: 8178955Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.Type: GrantFiled: April 4, 2011Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventors: Kenichi Itou, Noboru Takeuchi, Shigetoyo Kawakami, Toshiyuki Fukuda
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Patent number: 8174096Abstract: A stamped leadframe for a leadless package and a method of manufacturing the same are provided wherein the leadframe has at least a die pad, a frame, tie bars connecting the die pad to the frame and a plurality of leads. Each lead comprises a first portion and a second portion, and the second portion is connected substantially parallel to and displaced relative to the first portion by a distance that is less than the thickness of the first portion. Portions of the tie-bars and/or die pad may be similarly displaced.Type: GrantFiled: August 25, 2006Date of Patent: May 8, 2012Assignee: ASM Assembly Materials Ltd.Inventors: Tat Chi Chan, Man Shing Cheng
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Patent number: 8143707Abstract: A semiconductor device includes a circuit base including an inner lead portion and an outer lead portion. The inner lead portion has a plurality of inner leads. At least part of the inner leads is routed inside a chip mounting area. On both upper and lower surfaces of the circuit base, a first and a second semiconductor chip are mounted. At least part of electrode pads of the first semiconductor chip are electrically connected to electrode pads of the second semiconductor chip via the inner leads.Type: GrantFiled: December 18, 2009Date of Patent: March 27, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Yoshiaki Goto
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Patent number: 8120150Abstract: An integrated circuit package system includes: forming a die-attach paddle, a terminal pad, and an external interconnect with the external interconnect below the terminal pad; connecting an integrated circuit die with the terminal pad and the external interconnect; and forming an encapsulation, having a first side and a second side at an opposing side to the first side, surrounding the integrated circuit die with the terminal pad exposed at the first side and the external interconnect extending below the second side.Type: GrantFiled: September 18, 2007Date of Patent: February 21, 2012Assignee: Stats Chippac Ltd.Inventors: Guruprasad Badakere Govindaiah, Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Henry Descalzo Bathan, Lionel Chien Hui Tay
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Patent number: 8097934Abstract: A lead frame and package construction configured to attain a thin profile and low moisture sensitivity. Lead frames of this invention may include a die attach pad having a die attachment site and an elongate ground lead that extends from the die attach pad. The lead frame includes a plurality of elongate I/O leads arranged about the die attach pad and extending away from the die attach pad in at least two directions. An inventive lead frame features “up-set” bonding pads electrically connected with the die attach pad and arranged with a bonding surface for supporting a plurality of wire bonds. The bonding surfaces also constructed to define at least one mold flow aperture for each up-set bonding pad. A package incorporating the lead frame is further disclosed such that the package includes an encapsulant that surrounds the bonding support and flows through the mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity.Type: GrantFiled: August 13, 2008Date of Patent: January 17, 2012Assignee: National Semiconductor CorporationInventors: Felix C. Li, Yee Kim Lee, Peng Soon Lim, Terh Kuen Yii, Lee Han Meng@Eugene Lee
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Patent number: 8076761Abstract: The present invention is directed a novel method and apparatus for reducing crosstalk in a lead frame based electrical device package. One cause of the crosstalk in the lead frame package is the mutual inductance between adjacent lead fingers. A conductive sheet or mesh is introduced into the lead frame package such that one edge of the conductive sheet is below the die attach pad and electrically connected to the die and another edge is below the lead fingers and electrically connected to the ground lead of the package. Such arrangement significantly reduces the inductive coupling between adjacent lead fingers by coupling the lead fingers with the conductive sheet. The conductive sheet includes an array of through holes allowing the encapsulant material from the two sides of the sheet to flow smoothly together into one body.Type: GrantFiled: January 13, 2004Date of Patent: December 13, 2011Assignee: Altera CorporationInventor: Jon M. Long
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Patent number: 8067821Abstract: In accordance with the present invention, there are provided multiple embodiments of a semiconductor package, each embodiment including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, each embodiment of the semiconductor package of the present invention includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads, the exposed portions of the bottom surfaces of which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of both rows thereof being exposed in a common exterior surface of the package body.Type: GrantFiled: April 10, 2008Date of Patent: November 29, 2011Assignee: Amkor Technology, Inc.Inventors: YeonHo Choi, Timothy L. Olson
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Publication number: 20110284999Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.Type: ApplicationFiled: August 3, 2011Publication date: November 24, 2011Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jose Alvin Caparas
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Patent number: 8058107Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).Type: GrantFiled: September 17, 2007Date of Patent: November 15, 2011Inventors: Erwin Victor R. Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
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Patent number: 8058725Abstract: A package structure and a package substrate thereof are provided. The package structure includes a package substrate, a chip and a molding compound. The package substrate has an upper surface and a lower surface. The lower surface has a molding area and a pad area. The molding area has at least one window opening penetrating the upper surface and the lower surface. The pad area is used for disposing at least one solder ball or at least one connecting pin. The package substrate includes a solder mask. The solder mask covers the lower surface of the package substrate. The solder mask has at least one groove. The groove is disposed between the molding area and the pad area. The chip disposed on the package substrate has an active surface. The active surface contacts with the upper surface of the package substrate. The molding area is covered by the molding compound.Type: GrantFiled: October 10, 2007Date of Patent: November 15, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kuang-Hsiung Chen, Chen-Ming Cheng, Hung-Ju Chung
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Patent number: 8053875Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.Type: GrantFiled: November 23, 2009Date of Patent: November 8, 2011Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
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Patent number: 8048718Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.Type: GrantFiled: August 1, 2007Date of Patent: November 1, 2011Assignee: Renesas Electronics CorporationInventors: Toshinori Kiyohara, Yoshiharu Kaneda, Yoshikazu Takada
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Patent number: 8039938Abstract: A package includes a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, an assembly material between the pad chip and the spring chip arranged to form a gap between the pad chip and the spring chip, and an underfill material in a portion of the gap to form a mold from the pad chip and the spring chip. A package includes a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, an assembly material between the pad chip and the spring chip arranged to form a gap between the pad chip and the spring chip, an underfill material in the gap to form a mold from the pad chip and the spring chip, and at least one wall between the underfill material and the interconnect area.Type: GrantFiled: May 22, 2009Date of Patent: October 18, 2011Assignee: Palo Alto Research Center IncorporatedInventors: Christopher L. Chua, Bowen Cheng, Eugene M. Chow, Dirk De Bruyker
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Patent number: 8039947Abstract: An integrated circuit package system is provided including forming a first inner lead having a first inner bottom side and a first outer lead, forming a first side lock of the first inner lead above the first inner bottom side, connecting an integrated circuit die with the first inner lead and the first outer lead, and encapsulating the integrated circuit die and the first side lock.Type: GrantFiled: May 16, 2007Date of Patent: October 18, 2011Assignee: Stats Chippac Ltd.Inventors: Jeffrey D. Punzalan, Henry Descalzo Bathan, Zigmund Ramirez Camacho
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Patent number: 8035205Abstract: A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.Type: GrantFiled: January 5, 2007Date of Patent: October 11, 2011Assignee: Stats Chippac, Inc.Inventors: Seong Won Park, Cheng Yu Hsia, Yong Suk Kim
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Patent number: 8026591Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.Type: GrantFiled: March 19, 2010Date of Patent: September 27, 2011Assignee: Rohm Co., Ltd.Inventor: Kazutaka Shibata
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Patent number: 8018072Abstract: A semiconductor device has a substrate. A die is attached to a first surface of the substrate. A heat sink is provided having an approximately planer member and support members extending from the planer member. The support members are attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die. An encapsulant is provided for encapsulating the device, wherein an exterior surface of the planer member is exposed. A non-tapered opening is formed in the planer member. The encapsulant is injected through the opening to encapsulate the cavity and the encapsulant will partially fill the non-tapered opening.Type: GrantFiled: December 23, 2008Date of Patent: September 13, 2011Assignee: Amkor Technology, Inc.Inventors: Jeffrey A. Miks, Jui Min Lim
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Patent number: 8008132Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package.Type: GrantFiled: December 28, 2007Date of Patent: August 30, 2011Assignee: SanDisk Technologies Inc.Inventors: Suresh Upadhyayula, Bonnie Ming-Yan Chan, Shih-Ping Fan-chiang, Hem Takiar
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Patent number: 8008128Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.Type: GrantFiled: March 22, 2010Date of Patent: August 30, 2011Assignee: Shanghai Kaihong Technology Co., Ltd.Inventors: Xiaochun Tan, Zhining Li, Xaiolan Jiang
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Patent number: 8008756Abstract: A heat dissipating wiring board includes a metal wiring plate with a circuit pattern formed therein, a filler containing resin layer embedded with the metal wiring plate such that a top surface of the metal wiring plate is exposed, and a heat dissipating plate arranged on an under surface of the filler containing resin layer. The circuit pattern is formed of a through groove provided in the metal wiring plate. The through groove includes a fine groove that opens at the top surface of the metal wiring plate and an expanded groove that expands from a lower end of the fine groove toward the under surface of the metal wiring plate. The heat dissipating wiring board is capable of improving reliability against electric insulation due to dust or the like in a space of the through groove.Type: GrantFiled: June 13, 2007Date of Patent: August 30, 2011Assignee: Panasonic CorporationInventors: Tetsuya Tsumura, Hiroharu Nishiyama, Etsuo Tsujimoto
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Publication number: 20110198739Abstract: A semiconductor device manufacturing method prevents the occurrence of a short-circuit between leads caused by peeling-off of residual resin formed on lead side faces or lead lower portions. A laser beam is radiated a plurality of times from a main surface side of leads and also a plurality of times from a back surface side of the leads to intra-dam resin formed in a dam portion, the dam portion being enclosed with adjacent leads, a dam bar and a sealing body, thereby removing all the intra-dam resin formed on lead side faces and lead lower portions. The laser beam radiation of the intra-dam resin may leave behind a sealing body-side resin portion and a projecting resin portion which projects outwardly from the sealing body.Type: ApplicationFiled: February 10, 2011Publication date: August 18, 2011Applicant: Renesas Electronics CorporationInventors: Tomoji Amanai, Toshiyuki Okabe
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Patent number: 7999374Abstract: A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member.Type: GrantFiled: September 22, 2009Date of Patent: August 16, 2011Assignee: Fujitsu LimitedInventors: Tsuyoshi So, Hideo Kubo, Seiji Ueno, Osamu Igawa
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Patent number: 7999281Abstract: An optical semiconductor device includes: an optical semiconductor element including a light-emitting layer formed on a first principal surface, a first electrode formed on the light-emitting layer and having a smaller size than the first principal surface, and a second electrode formed on a second principal surface different from the first principal surface; a first lead portion including a bonding region to which the first electrode is bonded and which has a smaller size than the first principal surface, and a first groove portion formed on an outer peripheral region adjacent to the bonding region, the first lead portion being electrically connected to the first electrode bonded to the bonding region by use of a bonding member; and a second lead portion electrically connected to the second electrode by use of a connecting member.Type: GrantFiled: October 17, 2007Date of Patent: August 16, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuo Shimokawa, Yasunari Ukita
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Patent number: 7989930Abstract: A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles.Type: GrantFiled: October 25, 2007Date of Patent: August 2, 2011Assignee: Infineon Technologies AGInventors: Edmund Riedl, Joachim Mahler, Johannes Lodermeyer, Mathias Vaupel, Steffen Jordan
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Patent number: 7956386Abstract: A wiring structure in a semiconductor device may include a first insulation layer formed on a substrate, a first contact plug, a capping layer pattern, a second insulation layer and a second contact plug. The first insulation layer has a first opening that exposes a contact region of the substrate. The first contact plug is formed on the contact region to partially fill up the first opening. The capping layer pattern is formed on the first contact plug to fill up the first opening. The second insulation layer is formed on the capping layer pattern and the first insulation layer. The second insulation layer has a second opening passing through the capping layer pattern to expose the first contact plug. The second contact plug is formed on the first contact plug in the second opening. Since the wiring structure includes the capping layer pattern, the wiring structure may prevent a contact failure by preventing chemicals from permeating into the first contact plug.Type: GrantFiled: June 29, 2007Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Soon Bae, Sei-Ryung Choi
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Patent number: 7952198Abstract: A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas. The solder balls are disposed on the ball-placement areas.Type: GrantFiled: May 14, 2008Date of Patent: May 31, 2011Assignees: ChipMos Technologies (Bermuda) Ltd., ChipMos Technologies Inc.Inventor: Hung-Tsun Lin
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Patent number: 7948091Abstract: A mounting structure for a semiconductor element is disclosed. The semiconductor element is bonded to a die pad through an adhesive film, which is formed by applying a predetermined amount of a paste adhesive onto the surface of the die pad and placing the semiconductor element on the die pad so as to press and spread the adhesive between the lower surface of the semiconductor element and the die pad. A wire extends between the semiconductor element and a terminal pad disposed around the die pad. The die pad includes plural grooves in the surface thereof. Each of the grooves extends from the center of the die pad toward a peripheral edge of the die pad and ends at the inner side of the peripheral edge of the die pad.Type: GrantFiled: May 8, 2007Date of Patent: May 24, 2011Assignees: Fujitsu Component Limited, Fujitsu LimitedInventors: Yuko Ohse, Osamu Daikuhara, Hideki Takauchi
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Patent number: 7947534Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.Type: GrantFiled: February 4, 2006Date of Patent: May 24, 2011Assignee: Stats Chippac Ltd.Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Keng Kiat Lau
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Publication number: 20110089519Abstract: The invention discloses a chip lead frame and a photoelectric energy transducing module. The chip lead frame includes an insulator and a plurality of conductors. The insulator includes a first surface, a second surface, a first recess structure formed on the first surface, a through hole passing through the second surface and the first recess structure, and a venting structure. The first recess structure forms an accommodating space. The venting structure communicates with the accommodating space so that when a substrate is being bound to the first recess structure, the air in the accommodating space pressed by the substrate could flow through the venting structure out of the insulator without remaining between the substrate and the first recess structure. A photoelectric energy transducing semiconductor structure could be disposed on the substrate and electrically connected to the conductors, so as to form the photoelectric energy transducing module of the invention.Type: ApplicationFiled: October 6, 2010Publication date: April 21, 2011Applicant: NEOBULB TECHNOLOGIES, INC.Inventors: Jen-Shyan Chen, Chun-Jen Lin, Yun-Lin Peng, Wei-Yeh Wen
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Method and apparatus for directing molding compound flow and resulting semiconductor device packages
Patent number: 7927923Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.Type: GrantFiled: September 25, 2006Date of Patent: April 19, 2011Assignee: Micron Technology, Inc.Inventor: Stephen L. James -
Patent number: 7915717Abstract: A package for an image sensor includes a lead frame having a first surface and a second surface opposite the first surface; an image sensor mounted on the first surface of the lead frame; an optical cover spanning the first surface; and a plastic, optically transparent window in the optical cover and aligned with the image sensor.Type: GrantFiled: August 18, 2008Date of Patent: March 29, 2011Assignee: Eastman Kodak CompanyInventor: Carlos F. Rezende
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Patent number: 7909233Abstract: A method for manufacturing a semiconductor package system includes: providing a die having a plurality of contact pads; forming a leadframe having a plurality of lead fingers with flat tops of predetermined lengths, the plurality of lead fingers having a fine pitch and each having a trapezoidal cross-section; attaching a plurality of bumps to the plurality of lead fingers, the plurality of bumps on the tops, extending beyond the widths of the trapezoidal cross-sections, and clamping down on the two sides of each of the plurality of lead fingers; attaching a plurality of bond wires to the plurality of contact pads; attaching the plurality of bond wires to the plurality of bumps; and forming an encapsulant over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed.Type: GrantFiled: April 26, 2010Date of Patent: March 22, 2011Assignee: Stats Chippac Ltd.Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
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Publication number: 20110057298Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging lead-count, wherein the method lends itself to better automation of the manufacturing line and improved quality and reliability of the packages produced therefrom. A major portion of the manufacturing process steps is performed with a partially patterned strip of metal formed into a web-like lead frame on one side so that the web-like lead frame is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation.Type: ApplicationFiled: September 3, 2010Publication date: March 10, 2011Inventors: Mary Jean Ramos, Anang Subagio, Lynn Simporios Guirit, Romarico Santos San Antonio
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Publication number: 20110049687Abstract: A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.Type: ApplicationFiled: November 9, 2010Publication date: March 3, 2011Inventors: Heap Hoe Kuan, Rui Huang, Yaojian Lin, Seng Guan Chow
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Patent number: 7884453Abstract: The present invention relates to a semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, and an object of the invention is to provide the semiconductor chip and its manufacturing method in which the reduction in size may be attempted. It includes a semiconductor chip 15, an external connection terminal pad 18 electrically connected to the semiconductor chip 15, and an encapsulation resin 16 encapsulating the semiconductor chip 15, wherein a wiring pattern 12 on which the external connection terminal pad 18 is formed is provided between the semiconductor chip 15 and the external connection terminal pad 18, and the semiconductor chip 15 is flip-chip bonded to the wiring pattern 12.Type: GrantFiled: September 17, 2007Date of Patent: February 8, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Takaharu Yamano
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Patent number: 7880276Abstract: A wiring board where an electronic component is mounted on a main surface via a bump and at least a part of the periphery of the electronic component is covered with resin, the wiring board includes a dam provided at least at a part of the periphery of an area where the electronic component is mounted, on the main surface of the wiring board; wherein a surface of the dam contacting the resin has a configuration where a curved line is continuously formed.Type: GrantFiled: January 4, 2008Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Kazuyuki Aiba
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Patent number: 7880313Abstract: A flip chip lead frame package includes a die and a lead frame having a die paddle and leads, and has a spacer to maintain a separation between the die and the die paddle. Also, methods for making the package are disclosed.Type: GrantFiled: November 17, 2005Date of Patent: February 1, 2011Assignee: Chippac, Inc.Inventors: Jae Soo Lee, Geun Sik Kim, Sheila Alvarez, Robinson Quiazon, Hin Hwa Goh, Frederick Dahilig
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Patent number: 7863737Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.Type: GrantFiled: April 1, 2006Date of Patent: January 4, 2011Assignee: Stats Chippac Ltd.Inventors: Byoung Wook Jang, Hun Teak Lee, Kwang Soon Hwang
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Patent number: 7863759Abstract: A package structure and method for preventing gold bonding wires from collapsing are disclosed. The structure is especially useful for those chips whose two n×1 arrays of bonding pads are on the chip center to be packaged on a BGA substrate. According to the first preferred embodiment, two dies having a redistribution layer formed thereon are introduced outer the bonding pad array on the chip so that the gold bonding wires can be divided into two sections each to connect the bonding pads with the redistribution layer and the redistribution layer with the gold fingers on the BGA substrate. According to the second embodiment, the gold bonding wires are fixed by the epoxy strips on the chips after bonding the bonding pads to the gold fingers but before pouring liquid encapsulated epoxy into a mold.Type: GrantFiled: January 9, 2008Date of Patent: January 4, 2011Assignee: Integrated Circuit Solution Inc.Inventor: Ming-Feng Wu
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Patent number: 7847384Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.Type: GrantFiled: August 17, 2006Date of Patent: December 7, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Tsuyoshi Kobayashi, Tetsuya Koyama, Takaharu Yamano