Abstract: A semiconductor package comprising a substrate which includes a leadframe having a plurality of leads which each define opposed top and bottom surfaces and extends in spaced relation to each other such that gaps are defined therebetween. The substrate further comprises a compound layer which is filled within the gaps defined between the leads. The substrate includes a continuous, generally planar top surface collectively defined by the top surfaces of the leads and compound layer, and a continuous, generally planar bottom surface collectively defined by the bottom surfaces of the leads and compound layer. Attached to the top surface is a semiconductor die which is electrically connected to at least some of the leads.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: A power Schottky rectifier device having a plurality of first trenches filled in with an un-doped polycrystalline silicon layer and each first trenches also has a p-region beneath the bottom of said first trenches to block out reverse current while a reverse biased is applied and to reduce minority carrier while forward biased is applied. Thus, the power Schottky rectifier device can provide first fast switch speed. The power Schottky rectifier device is formed with termination region at an outer portion of the substrate. The manufacture method is also provided.

Abstract: A semiconductor device assembly having a lead frame and a semiconductor die configured to be attached to each other is disclosed. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor die is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: The invention is a leadframe/stabilizer (35) for use with semiconductor devices. Stabilizer (35) is for stabilizing the space between of lead frame leads (36–39) and improving the lead to lead spacing and to improve lead tip planarity. Stabilizer (35) extends partially along the length of and on each side of said lead frame leads (36–39) and include a die pad mount (40), integral with and forming a part of said stabilizer 35.

Abstract: A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

Abstract: A leadframe of a conductive material includes a central region to accommodate a chip and a plurality of connecting fingers extending at least from one side in the direction of the central region, a contact region being provided adjacent to the central region on at least some of the connecting fingers. The course of the connecting fingers is such that a sectional face in an arbitrary imaginary cross-section at right angles to the main face of the leadframe has leadframe material. In such a case, it is attempted to keep cross-sections in a component without leadframe material as small as possible.

Abstract: A substrate structure capable of reducing the package singular stress comprises a substrate having a plurality of substrate units. A molding gate is provided at a corner of each substrate unit. A plurality of slots are provided at the periphery of each substrate unit. A connection portion is provided between every two adjacent slots. These connection portions include a first connection portion and two second connection portions. The first connection portion is located at each molding gate. The second connection portions are located between two adjacent corners of each substrate unit, and opposite to each other. Through appropriate position arrangement of the connection portions, the molding gate stress at the corner of each package unit can be reduced. Moreover, the situation of breakage of trace in the substrate and peeling of molding compound from the substrate can be avoided.

Abstract: A semiconductor chip mounting component includes a support structure adapted to engage a semiconductor chip. The support structure has a top surface, a bottom surface, and a gap extending through the support structure for defining first and second portions of the support structure on opposite sides of the gap. The support structure includes at least one elongated bus disposed alongside the gap, on the second portion of the support structure. The support structure includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the first portion of the support structure, and a second end secured to the bus. Each lead includes a frangible section disposed between the first and second ends of the connection section, the frangible section having a cross-sectional area that is smaller than a cross-sectional area of the connection section. The gap is open at the bottom surface of the support structure.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract: In a lead frame which has second tie bars in the vicinity of plastic packages first notches are formed along first edges of the second tie bars (in areas defined on both sides of the inner leads and to come into contact with a punch during the tie bar cutting step). The first notches prevent troubles associated with close arrangement of the second tie bars and the plastic packages. In addition, second notches are provided along second edges of the second tie bars. These second notches are designed to receive the tips of outer leads which extend from neighboring plastic packages of the lead frames.

Abstract: An improved lead frame structure for use in a semiconductor package, including: a plurality of leads; a paddle structure electrically isolated from the leads, the paddle structure including at least one lower paddle section having a first top surface to which a die may be attached, at least one mesa section disposed proximate the paddle section and having a second top surface disposed at a different elevation than the first top surface, the lower paddle section and the mesa section being joined by a wall section; and a plurality of tie bars attached to the paddle structure for supporting the paddle structure; whereby contact pads of a die attached to the first top surface may be electrically connected to the second top surface and to the leads prior to encapsulation thereof. A plurality of tie bars extends from opposite edges of the paddle structure, the tie bars providing for stabilizing the paddle structure during package fabrication.

Abstract: A semiconductor package includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads. Each lead includes an inner end and an opposing distal end. Each inner end is disposed adjacent the peripheral edge in spaced relation thereto and vertically downset with respect to each respective distal end. The package further includes at least one isolated ring structure disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto. The ring structure is electrically connected to the semiconductor chip and an inner end of at least one of the leads.

Abstract: A semiconductor power module in which a power circuit chip and a control circuit chip are integrated in a package, is provided. The semiconductor power module includes a case; a terminal inserted into the case, the terminal including portions protruding upward to the outside of the case, and portions exposed in the case; a first substrate to which the power circuit chip is attached, the first substrate attached to the case for encapsulating the bottom of the package; a second substrate to which the control circuit chip is attached, the second substrate being spaced from the first substrate at a predetermined interval in a perpendicular direction in the case; and a cover for covering the top of the case, and for encapsulating the top of the package.

Abstract: A novel five-layer tape is provided for applications such as bonding, interconnection and insulation of different parts of a semiconductor package at the same time. The five layer tape includes a metal conductive layer that is sandwiched between two insulative layers, that are themselves in turn sandwiched by two adhesive layers. Windows cut into the insulative and adhesive layers on either the top or bottom of the tape permit electrical connection to the metallic conductive layer. The tape may be made from two insulation sheets that have an adhesive layer and a metallic interconnect. In turn, the tape enables the manufacturer to overcome physical limitations in forming conduction paths, including permitting the connection of multiple die where the terminals of the one die are obscured by the other die.

Abstract: The invention concerns a semiconductor component and a method for identifying a semiconductor component that comprises at least one semiconductor substrate equipped with electronic/electromechanical components, which said semiconductor substrate—except for its leads—is embedded in a housing part made of plastic. It is proposed to equip the semiconductor substrate located in the housing part with an identifier located directly or indirectly thereon that makes it possible to distinguish the semiconductor component from other similarly-designed semiconductor components, and which can be read out from outside the housing part using ultrasound.

Abstract: A flexible interconnect substrate (1) comprises a tape-shaped base substrate (10) and a plurality of interconnect patterns (20) formed on the base substrate (10). The base substrate (10) bas a plurality of first regions (44) met to be punched out, and second regions (45) between those first regions (44). Each of the second regions (45) has the material that forms the base substrate (10) is present in a central portion in the widthwise direction of the base substrate (10), and a low-bending-resistance portion (40) for ensuring that the second region (45) bends more readily than the adjacent first regions (44) in a direction in which the longitudinal axis of the base substrate (10) bends.

Abstract: An electronic device having a first semiconductor device for powering MOSFET and a second semiconductor device for controlling on a principal surface and sealed by a resin body. The first semiconductor device has a semiconductor chip with a first and a second electrodes formed on a first principal surface and also with a third electrode formed on a second principal surface, and an insulative or dielectric sheet laid out between a first lead and the first principal surface of the semiconductor chip and between a second lead and the semiconductor ship for covering a specified area of the first principal surface of the semiconductor chip other than a region in which a plurality of projected electrodes are disposed. An upper surface of the first and second leads of the first semiconductor device is positioned under an upper surface of the resin body of the second semiconductor device in a thickness direction of a wiring substrate.

Abstract: An improved tape carrier package (TCP) structure is proposed, which is characterized in the provision of dummy pads and dummy leads to help reinforce the package construction. The dummy pads are provided on the corners of the semiconductor chip, while the dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas on the tape carrier. During assembly, since dummy leads are bonded between the dummy pads and corner-situated lead-bonding areas, the corners of the semiconductor chip can be firmly supported as well as the four sides of the semiconductor chip which are supported by the I/O leads. As a result the package construction is reinforced. During inner-lead bonding (ILB) process, such reinforcement can help prevent the cracking of the I/O leads.

Abstract: A frame for semiconductor packages has die-pads supported with suspending leads of individual lead frames. Semiconductor devices are mounted on the respective die-pads. These semiconductor devices are collectively molded with molding compound, and then the collectively molded semiconductor packages are cut into individual packages by means of a dicing saw. In the frame, thin parts are formed in areas corresponding to the roots of individual terminals, the thin parts being formed by half-etching metal of the areas from the front or back thereof. Alternatively, hollows are formed in areas corresponding to the roots of individual terminals.

Abstract: The optical communication module comprises a laminated lead frame composed of a plurality of lead frames that are laminated and held by a tie bar made of an insulating material, and an optical communication functional unit that is disposed on at least one layer of the lead frame. The optical communication functional unit comprises at least one of a light emitting element (LD) and a light receiving element and an optical transmission medium (optical fiber).

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.

Abstract: Attaining improvement of the reliability and standardization of the lead frame. A semiconductor device comprises a plurality of inner leads extending around a semiconductor chip, a tape substrate supporting the semiconductor chip and joined to respective end portions of the inner leads, wires connecting the inner leads and pads formed on a main surface of the semiconductor chip, a seal portion formed by resin-sealing the semiconductor chip and the wires, and a plurality of outer leads linking in a line with line with the inner leads and protruded from the seal portion to the exterior of four directions. A relationship between a length (a) of a shorter side of the semiconductor chip and a clearance (b) from the semiconductor chip, to a tip of the inner leads arranged at the farthest location from the semiconductor chip is a≦2b. It is possible to attain a narrow pad pitch, and mount the semiconductor chip formed in a small size, and standardize the lead frame.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: A novel five-layer tape is provided for applications such as bonding, interconnection and insulation of different parts of a semiconductor package at the same time. The five layer tape includes a metal conductive layer that is sandwiched between two insulative layers, that are themselves in turn sandwiched by two adhesive layers. Windows cut into the insulative and adhesive layers on either the top or bottom of the tape permit electrical connection to the metallic conductive layer. The tape may be made from two insulation sheets that have an adhesive layer and a metallic interconnect. In turn, the tape enables the manufacturer to overcome physical limitations in forming conduction paths, including permitting the connection of multiple die where the terminals of the one die are obscured by the other die.

Abstract: An LOC die assembly including a die dielectrically adhered to the under of lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant is maximized, and the point stresses on the active surface caused by the filler particles are reduced by the lead flexure.

Abstract: A BGA package and a method for fabricating the package are provided. The package includes a semiconductor die, internal conductors wire bonded to bond pads on the die, external ball contacts attached to ball bonding pads formed on the conductors in a dense grid pattern, and an encapsulating resin encapsulating the die and conductors. The package is fabricated using a lead frame having lead fingers that form the conductors. The die is back bonded to a polymer tape placed across the lead fingers, and then wire bonded to bonding pads on the conductors. In addition, the encapsulating resin is molded to include openings for the ball contacts which are aligned with the ball bonding pads. An alternate embodiment BGA package includes a polymer substrate adhesively bonded to a face of the die. The polymer substrate includes conductors having beam leads aligned with an opening through the polymer substrate. The opening provides access for a bonding tool for bonding bumps on the beam leads to bond pads on the die.

Abstract: A lead frame of a plastic integrated circuit package is fabricated in two steps. First, from a rectangular sheet of metal, lead fingers of the lead frame are formed. Second, the die pad of the lead frame is clamped and is simultaneously separated and downset from the lead fingers of the lead frame by shearing the lead frame with a mated punch die pair. Performing the separation and downset of the die pad from the lead fingers results in essentially no horizontal gap between the lead fingers and the die pad. The downset of the die pad with respect to the lead fingers results in a vertical separation between the die pad and the lead fingers.

Abstract: An apparatus for routing signals to and from at least one circuit component that has a plurality of input/output leads includes a support structure having a first side and a second side. The first side is adapted to have the input/output leads of the circuit component attached thereto. A signal routing strip having a first end and a second end is also included. The first end of the routing strip is configured and adapted to be electrically connected to the input/output leads of the circuit component for transmitting signals to and from the circuit component.

Abstract: A system substrate for a semiconductor chip has a conductor frame (1); many small-area signal flat conductors (4) extend from webs (2, 3) of the conductor frame and on their free ends have contact terminal faces (5). Remaining faces (6) between the webs (2, 3) and the many signal flat conductors (4) are occupied by large-area flat conductors (7). Between the large-area flat conductors (7) and the webs (2, 3), there are connecting webs (9) with bent areas (8) at various spacings from the webs (2, 3).

Abstract: A multilayer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

Abstract: The flexible interconnecting substrate (1) has a tape-shaped base substrate (10), a plurality of interconnecting patterns (20) formed on a base substrate (10), and a plurality of reinforcing sections (40) formed on the base substrate 10. The plurality of reinforcing sections (40) is formed along the longitudinal direction of the base substrate (10), and at least part of each of the interconnecting patterns (20) is formed at a position away from each of the reinforcing sections (40) in the widthwise direction of the base substrate (10).

Abstract: An ultra-thin semiconductor package device comprises a heat-resistant film-type adhesive support tape which connects a semiconductor chip to a plurality of individual lead frames, wherein each lead frame is connected to an associated one of a plurality of electrode pads of the semiconductor chip by a plurality of bonding wires. An encapsulating molding material provides environmental protection for the completed package. Within the encapsulating molding, the semiconductor chip is mounted on a same underside of the support tape as the plurality of lead frames, such that the bottom of the semiconductor chip is aligned with the bottom of an encapsulating molding, and the height of a loop in each bonding wire is minimized.

Abstract: An ultra-thin semiconductor package device comprises a heat-resistant film-type adhesive support tape which connects a semiconductor chip to a plurality of individual lead frames, wherein each lead frame is connected to an associated one of a plurality of electrode pads of the semiconductor chip by a plurality of bonding wires. An encapsulating molding material provides environmental protection for the completed package. Within the encapsulating molding, the semiconductor chip is mounted on a same underside of the support tape as the plurality of lead frames, such that the bottom of the semiconductor chip is aligned with the bottom of an encapsulating molding, and the height of a loop in each bonding wire is minimized.

Abstract: Microelectronic-device assemblies and methods are provided that enhance operation of microelectronic devices because they exclude extraneous elements from sensitive device areas. They are especially suited for devices that carry a plurality of bonding pads on a circuit face that has a sensitive area. A lead frame defines a paddle that has an area less than that of the device face. The paddle is spaced from the face and positioned to cover the sensitive area and expose the pads. A plastic ring is arranged to surround the sensitive area and abut the face and the paddle. Encapsulation in an overmold thus forms a void within the ring and between the device face and the paddle and extraneous elements are excluded from this void.

Abstract: A die mounting apparatus that includes: 1) a die including a bottom surface having an active region is located among the bottom surface and a first and second bond pads provided on the bottom surface outside of the active region; 2) a substrate including a top surface and protruding electrical contacts that are electrically coupled to the first and second bond pads; and 3) a first encapsulant circumscribing a periphery of the die, where the first encapsulant, the bottom surface of the die, and the top surface of the substrate define a free space. The first encapsulant extends inwards from the periphery of the die towards the active region but does not contact the active region. Advantageously, the first encapsulant forms a seal around the die to protect its active region from the environment. A further advantage is that the first encapsulant provides added security that bond pads of the die will remain in contact with contacts formed among the substrate even after distortion of the shape of the die.

Abstract: Apparatus and methods for coupling conductive leads of semiconductor assemblies are disclosed. In one embodiment, a semiconductor assembly includes a semiconductor device having at least two bond pads with a conductive member extending between the bond pads, external to the device. In one embodiment, the conductive member can be connected directly to the bond pads and can extend between the bond pads at or above the surface of the semiconductor device. In another embodiment, the conductive member can be connected on top of another conductive member previously attached to one of the bond pads. The conductive members can be attached to each other or to the bond pads with either ball bonds or wedge bonds to provide electrical signals to selected bond pads of the semiconductor device.

Abstract: This invention prevents deterioration in characteristics of a semiconductor device having a lead frame that is thin and uniform in thickness. More specifically, this invention relieves resin distortion caused by a difference in thermal expansion coefficients between the lead frame and the sealing resin in order to prevent the characteristic deterioration caused by some factors such as moisture invasion from outside and mechanical pressure. A lead frame for a resin-sealed semiconductor device of this invention is composed of an element-mount part, a horizontal part for fixing the lead frame for resin sealing, and a central lead having side leads formed in parallel on both sides thereof. The element-mount part, the horizontal part and the central lead are formed integrally. In the lead frame, at least one pair of resin-anchoring parts are formed on two opposing sides on the periphery of the element-mount part.

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Abstract: The present invention relates to a packaged semiconductor that includes a semiconductor having a plurality of leads extending therefrom. The leads are formed by mounting the semiconductor device in a lead frame and punching and sealing the leads in the semiconductor device using a resin, wherein the leads have been bent to a predetermined configuration. A connector is further provided to connect leads to the frame, and the connector is bent at substantially the same time as when the leads are bent to the predetermined configuration. According to the packaged semiconductor, a lead is not cut off from a lead frame, and the connection between the two can be maintained even after a bending process is finished.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A leadframe including offsets extending from a major plane thereof. The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high Temperatures or changes in temperature.

Abstract: There is provided a lead frame including first and second rows of inner leads each of which is electrically connected to an associated electrode of a semiconductor chip and which are situated at opposite sides about the semiconductor chip, first and second rows of outer leads each of which is electrically connected to an associated inner lead in the first and second rows of inner leads, respectively, a tie bar connecting a first outermost inner lead in the first row of inner leads to a second outermost inner lead in the second row of inner leads, and a control plate comprised of first branches extending from the first outermost inner lead towards the second outermost inner lead and second branches extending from the second outermost inner lead towards the first outermost inner lead, the control plate being connected to the tie bar.

Abstract: A multi-layer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Abstract: In a lead frame, L-shaped support tapes are applied to inner leads and suspension leads. Ends of the support tapes are overlapped with each other at the suspension leads to form, together, a rectangular ring shape. Since the support tapes are L-shaped, when the overlapped portions are positioned at the suspension leads, there are only two overlapped portions of the support tapes at the suspension leads. Thus, the number of overlapped portions requiring accurate alignment is reduced. Moreover, the L-shaped support tapes can be cut from the material for the support tape with higher efficiency.