Of Insulating Material Patents (Class 257/671)
-
Patent number: 6268645Abstract: A semiconductor device having a semiconductor chip on a TAB (Tape Automated Bonding) tape with high reliability is provided. The semiconductor device of the present invention includes a TAB tape which has a base film provided with a device hole in a position where a semiconductor chip is mounted, a wiring pattern whose end portions constitute inner leads connected to the semiconductor chip and terminal connecting portions provided with solder balls, and a photo-solder resist which protects the wiring pattern. Chamfered portions which relieves internal residual stress caused in the photo-solder resist due to the difference in thermal expansion coefficient between the base film and the photo-solder resist are formed at locations on the photo-solder resist facing the corners of the device hole.Type: GrantFiled: March 22, 2000Date of Patent: July 31, 2001Assignee: Fujitsu LimitedInventors: Masashi Takenaka, Shiro Yoda, Junichiro Hiyoshi, Hiroshi Takahashi, Hideo Sato
-
Publication number: 20010008303Abstract: A semiconductor apparatus includes a thin film belt-like insulating tape having a plurality of predetermined wire patterns thereon, and a plurality of IC chips that are provided on a surface of the insulating tape at uniform spaces in a lengthwise direction and electrically connected with the wire patterns, and further includes thick film reinforcing tapes with sprocket holes for transport use provided at uniform spaces, the reinforcing tapes being provided on both side portions of the insulating tape, in the lengthwise direction.Type: ApplicationFiled: March 7, 2001Publication date: July 19, 2001Applicant: Sharp Kabushiki KaishaInventor: Nakae Nakamura
-
Patent number: 6246110Abstract: A semiconductor lead frame, and a semiconductor package fabricated using the lead frame, are provided. The lead frame includes side rails; patterns of lead fingers; and multiple die mounting paddles. Each die mounting paddle is configured to mount a semiconductor die for wire bonding to an associated pattern of lead fingers. In addition, each die mounting paddle includes support members on opposing sides, each having at least two downset segments. The downset segments of the support members offset the die mounting paddles from the lead fingers. In a first lead frame embodiment, the support members include downset segments oriented at opposing angles with respect to a longitudinal axes of the mounting paddles. In a second embodiment, the support members include two or more downset segments oriented along axes that are generally parallel to the die mounting paddles.Type: GrantFiled: October 12, 1999Date of Patent: June 12, 2001Assignee: Micron Technology, Inc.Inventors: Larry D. Kinsman, Mark Wolfe
-
Patent number: 6225685Abstract: Wire sweep/crossing during resin molding is significantly reduced or prevented by reducing the gap spacing between corner lead pins and the tie bars of a die-attach pad. Embodiments of the present invention include spacing the tie bars from the corner lead pins by a distance no greater than about 18 mils, e.g., about 4 to 12 mils. Embodiments of the present invention also comprise a lead frame wherein the inner ends of the lead pins are arranged in a substantially planar array to define a substantially circular region surrounding the die-attach pad.Type: GrantFiled: April 5, 2000Date of Patent: May 1, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Robert Newman, Chu-Chung Stephen Lee, Melissa Siow-Lui Lee
-
Patent number: 6211563Abstract: The leadframe of the present invention comprises a supporting bar having the first terminals and the second terminals, wherein the first terminals are coupled to the separating portion of the leadframe and the second terminals are used to support the chip. A plurality of inner leads connected to the supporting bar. A plurality of external leads connected to the inner leads; Adhesive material, formed on the leadframe and used to attach the chip to the inner leads, wherein the area of adhesive material is smaller than that of said chip. A plurality of bonding wires is used to couple the chip to the leadframe. Finally, the chip is encapsulated with the molding compound to protect the chip and the bonding wires.Type: GrantFiled: June 30, 1999Date of Patent: April 3, 2001Assignee: Sampo Semiconductor CooperationInventor: Chung-Hsing Tzu
-
Patent number: 6191490Abstract: This invention relates to a semiconductor package having a separated die pad, which is comprised of an integrated circuit chip having a plurality or bonding pads mounted on its surface; a die pad providing its upper surface for the chip to be attached to, which comprises the first plate and second plates disposed a space apart, and an adhesive film attached to the under surface of the first and second plates; a plurality of leads, the near end portions of the leads which can be electrically connected to the bonding pads of the chip, wherein the far end portions are exposed to the exterior surface of the semiconductor package; and a package body made of insulating material, wherein the chip, the die pad and the leads including parts of their near end portions are encapsulated.Type: GrantFiled: January 20, 1998Date of Patent: February 20, 2001Assignee: Siliconware Precision Industries, Co., Ltd.Inventor: Chien-Ping Huang
-
Patent number: 6172413Abstract: The present invention relates to a chip package and to methods of testing a chip package wherein contact to chip leads is made by a configuration of testing probes in such a manner so as to allow for shorter, tighter-pitch, and more robust chip leads that will not short out into neighboring adjacent chip leads. The present invention also relates to a chip package wherein the terminal ends of the chip leads are constrained in a dielectric medium such that package testing may be carried out before final sizing of chip lead lengths.Type: GrantFiled: October 9, 1997Date of Patent: January 9, 2001Assignee: Micron Technology, Inc.Inventor: Warren M. Farnworth
-
Patent number: 6124630Abstract: A multi-layer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.Type: GrantFiled: August 10, 1999Date of Patent: September 26, 2000Assignee: Micron Technology, Inc.Inventor: Eric J. Stave
-
Patent number: 6124642Abstract: A lead structure is provided in a semiconductor device, having a body of a lead having at least a part of which is in contact with an adhesive which bonds with an insulation tape, and a protection layer selectively provided on the body of the lead so that the protection layer coats at least the part of the body in contact with the adhesive to completely isolate the body of the lead from the adhesive, to prevent an ion migration of a material of the body and also to prevent leakage of currents from and into the body of the lead.Type: GrantFiled: November 26, 1997Date of Patent: September 26, 2000Assignee: NEC CorporationInventor: Mitsuhiro Matsutomo
-
Patent number: 6093958Abstract: In a semiconductor device having a lead-on-chip structure, a thin plate is arranged in an outer peripheral area of a semiconductor element and has a thickness substantially the same as that of the semiconductor element.Type: GrantFiled: January 19, 1999Date of Patent: July 25, 2000Assignee: NEC CorporationInventor: Takehito Inaba
-
Patent number: 6091135Abstract: An improved lead frame with a pre-mold paddle for a semiconductor chip package which prevents delamination and cracking between a mold body and the pre-mold paddle on which a semiconductor chip in the semiconductor chip package is placed.Type: GrantFiled: December 23, 1997Date of Patent: July 18, 2000Assignee: LG Semicon Co., Ltd.Inventor: Byeong Duck Lee
-
Patent number: 6066888Abstract: In a tape carrier, one or a plurality of overhang patterns, each being shorter than a length that reaches an edge of a semiconductor chip, is provided in an area where the pitch between adjacent inner leads is relatively large or in a corner area of the device hole where inner leads are not provided, depending upon the size of such area. An average of resin sealing ranges on the rear surface of the tapes is 0.8 mm and the diversification is 0.06 mm.Type: GrantFiled: June 11, 1999Date of Patent: May 23, 2000Assignee: Seiko Epson CorporationInventor: Masahiko Yanagisawa
-
Patent number: 6037652Abstract: A lead frame is provided that prevents breaks in bonding wires caused by thermal stress which is applied when mounting a resin semiconductor. A plating layer is applied to the surfaces of internal leads to which bonding wires are to be connected and an insulating tape is adhered the internal lead 1 tips and bonding balls, so as to prevent peeling between the internal leads 1 and the resin, thereby preventing breaking of a bonding wire cause by stress applied during mounting. Additionally, a semiconductor device which makes use of this lead frame structure is provided.Type: GrantFiled: May 29, 1997Date of Patent: March 14, 2000Assignee: NEC CorporationInventor: Mitsuhiro Matsutomo
-
Patent number: 6031277Abstract: A multi-layered conductive device is constituted of a plurality of conductive elements disposed in at least two layers, and an insulating film disposed between the respective conductive elements. The multi-layered conductive device may be manufactured by forming a single conductive element, adhering an insulating film to at least one surface of the conductive element, cutting the conductive element to form at least two conductive strips, laminating at least two layers of conducting elements to from a single assembly and fixing the assembly with a resin.Type: GrantFiled: January 30, 1998Date of Patent: February 29, 2000Assignee: Tokai Kogyo Kabushiki KaishaInventors: Katsura Sugiura, Sei Utsunomiya
-
Patent number: 6020630Abstract: A semiconductor package (80) is provided that serves to support a semiconductor chip (12). A radial slot (54) is formed in an inner ring (26). Cross-slots (64) and (66) are formed in a corner member (38) of polyimide film (22). The slots (54), (64) and (66) serve to allow independent expansion of various portions of the polyimide film (22) and prevent breakage of contact leads (14), (16), (18) and (20) due to the differences in the thermal coefficient of expansion of the semiconductor material and the polyimide film material.Type: GrantFiled: January 5, 1995Date of Patent: February 1, 2000Assignee: Texas Instruments IncorporatedInventors: William K. Dennis, Masood Murtuza
-
Patent number: 5998857Abstract: Disclosed is a semiconductor package where at least one tie bar is arranged on the leadframe such that the die to be packaged is attached to the tie bar by binding tape. The problem of gap or delamination will not occur due to the disuse of silver epoxy and die paddle. The processing time can be reduced and the applicability to die is enhanced.Type: GrantFiled: August 11, 1998Date of Patent: December 7, 1999Assignee: Sampo Semiconductor CorporationInventor: Chung-Hsing Tzu
-
Patent number: 5969413Abstract: A semiconductor chip is supported on a tape carrier provided with lead wirings. The semiconductor chip is electrically connected to the lead wirings. The semiconductor chip of this quality is bonded in combination with the pe carrier to an aluminum nitride substrate. The lead wirings provided on the carrier combine the two functions as an internal lead and an external lead. The semiconductor package of such a structure as is described above allows multi-terminal connection by the narrowing of pitches between the leads and permits provision of a miniature package excelling in the heat-radiating property. Alternatively, the lead wirings supported on the tape carrier and electrically connected to the semiconductor chip are utilized as internal leads. For the external leads, such lead frames as are bonded to the aluminum nitride substrate are used. The lead frames are electrically connected to the internal leads provided in the tape carrier.Type: GrantFiled: May 14, 1997Date of Patent: October 19, 1999Assignee: Kabushiki Kaishi ToshibaInventors: Keiichi Yano, Kazuo Kimura, Hironori Asai, Jun Monma, Koji Yamakawa, Mitsuyoshi Endo, Hirohisa Osoguchi
-
Patent number: 5965936Abstract: A multi-layer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.Type: GrantFiled: December 31, 1997Date of Patent: October 12, 1999Assignee: Micron Technology, Inc.Inventor: Eric J. Stave
-
Patent number: 5939775Abstract: An improved leadframe structure and an improved IC package and process using such structure are disclosed. The improved leadframe structure eliminates the dambar commonly found on leadframes for use in plastic packages. A polymer structure is formed and employed primarily to act as a barrier to flashing during the epoxy encapsulation process and secondarily to provide support for the leads. The polymer structure remains a permanent part of the IC package following molding. An improved IC packaging process using the improved leadframe design eliminates common debar, dejunk and deflash operations, resulting in reduced capital costs and higher yields.Type: GrantFiled: November 5, 1996Date of Patent: August 17, 1999Assignee: GCB Technologies, LLCInventors: Giuseppe D. Bucci, Paul H. Voisin
-
Patent number: 5917235Abstract: A semiconductor device with a LOC structure having a semiconductor device lead frame, TAB leads, and an insulating TAB tape, wherein the semiconductor device lead frame has a plurality of leads and is formed by fixing a semiconductor element on one surface side of the leads through insulating tapes. The leads are arranged to correspond to electrodes of the semiconductor element, wherein the TAB leads electrically connect the leads of the semiconductor device lead frame and the electrodes on the semiconductor element, and wherein the insulating TAB tape has electrical insulating characteristics and is fixed on the other surface side of the leads of the semiconductor device lead frame to surround a group electrodes of the semiconductor element, the insulating TAB tape serving to hold the TAB leads to be isolated from each other.Type: GrantFiled: August 18, 1997Date of Patent: June 29, 1999Assignee: NEC CorporationInventor: Tomoo Imura
-
Patent number: 5905300Abstract: A method and apparatus for a reinforced leadframe to substrate attachment in a semiconductor assembly. In one embodiment, a printed circuit board having a plurality of electrically coupled electrical contact regions and wire bond areas formed thereon has a leadframe attached thereto such that each of the bonding fingers of the leadframe is coupled to a respective electrical contact region on the printed circuit board. A ribbon of B-staged epoxy is disposed on the leadframe such that the leadframe is disposed between the ribbon of B-staged epoxy and the printed circuit board. An integrated-circuit die is mounted on the printed circuit board with the bonding fingers of the leadframe peripherally surrounding the integrated circuit die. The bonding pads on the integrated-circuit die are electrically coupled to respective wire bond areas on the printed circuit board.Type: GrantFiled: June 30, 1997Date of Patent: May 18, 1999Assignee: VLSI Technology, Inc.Inventor: Louis H. Liang
-
Patent number: 5885852Abstract: For manufacturing a packaged semiconductor device, a lead frame with an electrically insulating strip member and a semiconductor chip is placed in a molding unit having upper and lower dies. The upper and lower dies have recessed areas for determining a size of a cavity of the molding unit different from each other, the size of the cavity being measured in a direction perpendicular to a clamping motion direction of the dies. The lead frame is positioned so that a surface of each lead with the insulating strip member applied thereto is contacted with one of the upper and lower dies having a larger recessed area and a molding line of the molding unit intersects the insulating strip member. The molding unit is closed to clamp the lead frame to depress and thrust into spaces between adjacent leads that part of the strip member which is outside the molding line and to form the cavity of the molding unit.Type: GrantFiled: April 28, 1997Date of Patent: March 23, 1999Assignee: Hitachi, Ltd.Inventors: Norio Kishikawa, Ikuo Yoshida, Tetsuya Hayashida
-
Patent number: 5872394Abstract: In a lead frame, L-shaped support tapes are applied to inner leads and suspension leads. Ends of the support tapes are overlapped with each other at the suspension leads to form, together, a rectangular ring shape. Since the support tapes are L-shaped, when the overlapped portions are positioned at the suspension leads, there are only two overlapped portions of the support tapes at the suspension leads. Thus, the number of overlapped portions requiring accurate alignment is reduced. Moreover, the L-shaped support tapes can be cut from the material for the support tape with higher efficiency.Type: GrantFiled: September 5, 1996Date of Patent: February 16, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Shinohara, Yoshiharu Takahashi
-
Patent number: 5859471Abstract: In a lead frame adapted to be used for a semiconductor device, a plurality of inner leads are made of a thin conductive material for easily forming a fine pattern of the inner leads. A plurality of outer leads are integrally formed with the respective inner leads. The outer leads are coated with metal layers to increase the thickness thereof, so that a desired strength of the outer leads is obtained. A semiconductor chip is electrically connected to the inner leads. The semiconductor chip and a part of the lead frame including the inner leads are hermetically sealed with a resin and, thus, a semiconductor device is obtained.Type: GrantFiled: October 9, 1997Date of Patent: January 12, 1999Assignee: Shinko Electric Industries Co., Ltd.Inventors: Fumio Kuraishi, Kazuhito Yumoto, Mamoru Hayashi
-
Patent number: 5821610Abstract: Resin tie bars are formed between leads of external leads extending out from a resin-sealed region. The external leads are formed such that lead width at portions beyond the portion where the resin tie bars are formed is less than the lead width at portions where the resin tie bars are formed. With this construction, resin extending between the leads from the periphery of the resin-sealed region, including the resin tie bars, can be easily removed after resin-sealing when the resin tie bars are subjected to water sprayed at high pressure.Type: GrantFiled: July 14, 1997Date of Patent: October 13, 1998Assignee: NEC CorporationInventor: Hideyuki Nishikawa
-
Patent number: 5773876Abstract: A lead frame having protection against electrostatic discharge is disclosed. The lead frame having protection against electrostatic discharge includes a multiplicity of leads and an electrostatic discharge protection device. The electrostatic discharge protection device includes a conductive layer and a protection layer. The protection layer is arranged to contact a plurality of leads and is formed from an electrostatic discharge protection material, which insulates the leads from the conductive layer at voltages below a predefined threshold voltage and establishes an electrical connection between the leads and the conductive layer at voltages above the threshold voltage.Type: GrantFiled: November 6, 1996Date of Patent: June 30, 1998Assignee: National Semiconductor CorporationInventors: Boonmi Mekdhanasarn, Randy Hsiao-Yu Lo
-
Patent number: 5751056Abstract: A semiconductor device having metal leads 14 with improved reliability comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and dummy leads 16 proximate the metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16, and the dummy leads 16 are capable of dissipating the heat. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is improved reliability of metal leads for circuits using low-dielectric constant materials.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: Texas Instruments IncorporatedInventor: Ken Numata
-
Patent number: 5710064Abstract: A method for manufacturing a semiconductor package, including providing a lead frame in which die pad and side rail areas of the lead frame are mechanically interconnected to, and electrically isolated from each other so that the exposed bottom surface of the die pad does not become coated with a metal plating film during surface treatment for coating outer leads of the lead frame.Type: GrantFiled: August 10, 1995Date of Patent: January 20, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: Young Jae Song, Jeong Woo Seo, Wan Gyun Choi
-
Patent number: 5704593Abstract: A film carrier tape for a semiconductor package comprises a tape base film having a signal plane with leads disposed thereon and a ground plane on the surface opposite the signal plane. The ground plane has ground plane leads projecting into a device hole and OLB lead holes defined in the tape base film, the ground plane leads confronting the leads on the signal plane. The ground plane leads are electrically connected to selected leads on the signal plane.Type: GrantFiled: January 9, 1997Date of Patent: January 6, 1998Assignee: NEC CorporationInventor: Hirokazu Honda
-
Patent number: 5637914Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.Type: GrantFiled: May 10, 1995Date of Patent: June 10, 1997Assignee: Hitachi, Ltd.Inventors: Naotaka Tanaka, Akihiro Yaguchi, Makoto Kitano, Tatsuya Nagata, Tetsuo Kumazawa, Atsushi Nakamura, Hiromichi Suzuki, Masayoshi Tsugane
-
Patent number: 5559365Abstract: Disclosed herein is a semiconductor device having a terminal bend protecting frame formed in the terminal tip parts by filling the spaces between the lead terminals with a resin of the same quality as that of the sealing resin. In other words, each of lead terminals led from a package has a first end portion extending upward and a second end portion extending downward.Type: GrantFiled: December 28, 1994Date of Patent: September 24, 1996Assignee: NEC CorporationInventor: Shotaro Kobayashi
-
Patent number: 5545850Abstract: There is provided a leadframe having a plurality of coplanar electrically conductive leads. At least one metallic guard is bonded to the leads with a dielectric layer disposed between the metallic guard and the leads. The metallic guard has good adhesion to a polymer molding resin such that when the leadframe structure is encased in a molding resin, delamination is minimized. By restricting delamination, the ingress of water and water soluble contaminants to an integrated circuit device is inhibited.Type: GrantFiled: January 13, 1995Date of Patent: August 13, 1996Assignee: Olin CorporationInventors: Deepak Mahulikar, Paul R. Hoffman
-
Patent number: 5525547Abstract: A molded semiconductor device has a plurality of slender leads formed with a sealing strip connecting them together to prevent the molding material from leaking out between the leads. Specifically, the sealing strip comprising an adhesive and an electrically insulating material is applied to the leads substantially perpendicular to the lengthwise direction of the leads. The strip is place such that an inner edge thereof substantially lies on a boundary line or inside where the molding terminates. The strip is then thrust into spaces formed between the leads. Thereafter the semiconductor chip is connected to the leads, the semiconductor chip and the leads are placed in a molding unit, the strip serving to block the molding material leaking outside the molding unit.Type: GrantFiled: December 2, 1993Date of Patent: June 11, 1996Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Toshihiro Matsunaga, Yuji Shirai, Takayuki Okinaga, Osamu Horiuchi, Takashi Emata, Makoto Omata
-
Patent number: 5512780Abstract: An inorganic chip-to-package interconnection circuit is described. The circuit has a set of electrical conductors that are held together by a set of insulating inorganic tie bars. The circuit constitutes a high-density chip-to-package interconnection circuit that does not absorb vapor or volatile gases. A variety of methods for forming the circuit are described. Advantageously, the methods utilize known processing techniques.Type: GrantFiled: September 9, 1994Date of Patent: April 30, 1996Assignee: Sun Microsystems, Inc.Inventor: Howard L. Davidson
-
Patent number: 5473199Abstract: A semiconductor device includes a semiconductor device body, a ring part, and connecting parts. The semiconductor device body includes a resin package and a plurality of leads extending outwardly from the resin package. The ring part is made of a resin and surrounds the semiconductor device body. The connecting parts are made of a resin and connect the semiconductor device body and the ring part, so that the semiconductor device body is supported by the ring part via the connecting parts.Type: GrantFiled: February 24, 1993Date of Patent: December 5, 1995Assignee: Fujitsu LimitedInventor: Yoji Murakami
-
Patent number: 5473190Abstract: A TAB tape is constituted by a base material consisting of, e.g., a polyimide, in which leads composed of a copper foil are formed on the base material, and a power supply unit and a signal unit formed on a substrate, such as a printed circuit board, are connected to electrodes formed on a chip via the copper foil leads. Power supply leads for supplying power to the chip, ground leads for grounding, and signal leads for exchanging signals with the chip are formed by the copper foil on one surface of the base material. A common power supply lead to be connected to the power supply leads and a common ground lead to be connected to the ground leads are formed by the copper foil on the other surface of the base material.Type: GrantFiled: December 14, 1993Date of Patent: December 5, 1995Assignee: Intel CorporationInventors: Shuji Inoue, Yasuhiko Hiraki, Mutsumi Agawa
-
Patent number: 5471097Abstract: A semiconductor device encapsulated with a synthetic resin portion, includes a semiconductor chip, a plurality of leads each electrically connected at one end thereof to the semiconductor chip and bent to have a gull-wing like shape extending outwardly from the synthetic resin portion, and an insulating support member provided in a flat portion nearer to the resin portion than a bottom soldering face of the leads of the gull-wing like shape. The leads are fixed to each other by means of the insulating support member. The semiconductor device has an improved lead alignment even if the leads are each very thin and aligned with fine pitch. Such a semiconductor device can be assuredly mounted on a printed board or the like with ease together with mounting the semiconductor device on the printed board type components, thereby contributing to acquisition of a highly reliable electronic device.Type: GrantFiled: September 9, 1994Date of Patent: November 28, 1995Assignee: Rohm Co., Ltd.Inventor: Kazutaka Shibata
-
Patent number: 5442229Abstract: A method of assembling a semiconductor chip on a tape carrier has the steps of stacking, on a film carrier having a first group of metal leads, another film carrier having a second group of metal leads and bonding the two film carriers together by adhesive to form a laminated structure. The first and second groups of metal leads are so disposed that they do not contact and do not cross one another. The tips of the metal leads of the two groups are bonded to the electrodes on the semiconductor chip. The metal leads are formed in advance on the corresponding film carriers by etching. By stacking the plurality of film carriers, the connection pitch can be reduced while eliminating a necessity for reducing the thickness of each lead.Type: GrantFiled: September 10, 1993Date of Patent: August 15, 1995Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.Inventors: Takao Mori, Satoshi Yoshida, Tadahiko Nishimukai, Kenji Yamaguchi
-
Patent number: 5399903Abstract: A substrate includes a non-conductive support layer and a plurality "n" of conductive leads disposed on the support layer. The leads are arranged in a generally radial pattern about a central point on the support layer, each of the leads having a width "w" and spaced a distance "d" from one another at their innermost ends, thereby forming a generally square opening of side dimension "s". The substrate accommodates semiconductor dies ranging in size from smaller than the opening, to approximately equal to that of the opening, to substantially larger than the opening, such as four times the size (linear dimension) of the opening. The die is bonded to the substrate. Other elements of a semiconductor device assembly are added to the resulting structure. Method and apparatus are disclosed.Type: GrantFiled: July 30, 1992Date of Patent: March 21, 1995Assignee: LSI Logic CorporationInventors: Michael D. Rostoker, Richard Brossart
-
Patent number: 5359225Abstract: A high leadcount surface mount IC package. The IC package of the present invention includes a plastic molded compound which is localized over the surface of the die, such that it covers the interconnections of the die. The package includes a leadframe having many leads. The leads are supported using a ring support structure.Type: GrantFiled: November 6, 1992Date of Patent: October 25, 1994Assignee: Intel CorporationInventor: Kevin J. Haley
-
Patent number: 5338973Abstract: An opening is formed at the central part of a substrate, and a recessed part for holding a film carrier type IC is formed in the periphery of the opening. Fixing hooks are provided in the recessed part that are mutually opposed with the opening in between. In particular, the projections in the upper part of the fixing hooks are tapered to facilitate the insertion of the fixing hooks to the sprocket holes.Type: GrantFiled: November 1, 1993Date of Patent: August 16, 1994Assignee: NEC CorporationInventor: Akira Yoshigai
-
Patent number: 5336564Abstract: A process for forming a keeper bar upon TAB tape leads for maintaining position of the leads during excise and form operations, integrated circuit placement, and lead bonding, utilizes the steps of immersing TAB tape into a bath of ultraviolet curable resin; directing ultraviolet radiation onto the TAB tape at location(s) where keeper bars are desired, so as to cure the resin to define the keeper bars; washing away uncured resin; and drying the TAB tape.Type: GrantFiled: December 6, 1993Date of Patent: August 9, 1994Assignee: Grumman Aerospace CorporationInventor: Boris Moldavsky
-
Patent number: 5336927Abstract: A semiconductor device includes an element mounting portion, suspending leads, a large number of inner leads, a semiconductor element, and insulating tapes. The element mounting portion is arranged at a central portion of a lead frame. The suspending leads support four corners of the element mounding portion from a peripheral portion of the lead frame. The large number of inner leads are formed toward the element mounting portion. The semiconductor element is mounted on the element mounting portion and has electrode portions connected to distal ends of the inner leads. Each of the insulating tapes has cut portions obtained by partially cutting two corners of both ends of a rectangle of each of the tapes near the element mounting portion and projection portions projected from two corners of the rectangle far from the element mounting portion and each having the same shape of each of the cut portions. The insulating tapes are adhered to the inner leads parallelly to four sides of the semiconductor element.Type: GrantFiled: January 25, 1993Date of Patent: August 9, 1994Assignee: NEC CorporationInventor: Kenji Suetake
-
Patent number: 5293064Abstract: A lead frame for manufacturing a semiconductor device has at least one set of substantially parallel leads having inner ends for connection to a semiconductor chip, outer ends for external connection and central portions therebetween and an outer tiebar interconnecting the outer ends and having an elongated guide hole therein, the longer dimension of the guide hole being parallel to the leads. A lead bending die has a locating pin respectively corresponding to and received in sliding engagement in each guide hole. The die maintains a center portion of them lead frame in a first plane and, with each locating pin remaining in sliding engagement within the respective, elongated guide hole, bends the central portions of the leads thereby to dispose the respective outer ends of the leads in a second plane, displaced from the first plane. The outer tiebar and the sliding engagement of the locating pin in the guide hole serve to prevent undesirable deformation of the leads as a result of the bending operation.Type: GrantFiled: February 3, 1992Date of Patent: March 8, 1994Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Masanori Yoshimoto, Kazuto Tsuji, Masao Sakuma, Kouichi Takeshita
-
Patent number: 5281851Abstract: An integrated circuit package with plastic or glass reinforcement of leads to increase lead rigidity, to improve lead alignment and positional stability, and to prevent bent leads. The invention is particularly applicable to surface mount packages. For plastic packages, plastic between the leads is formed during molding of the plastic package. For metal packages, the plastic is molded as a separate operation. For ceramic packages with lead frames, glass may be formed as a separate operation or may be formed at the same time as a glass seal for the ceramic package. Reinforcement can optionally be thicker than the leads for increased rigidity. Optional extended lead lengths enable plastic or glass to be formed on either side of the soldered foot area of each lead. No changes to test fixtures or to pick and place equipment are required.Type: GrantFiled: October 2, 1992Date of Patent: January 25, 1994Assignee: Hewlett-Packard CompanyInventors: Louis T. Mills, Richard M. Butler, Havyn E. Bradley
-
Patent number: 5268331Abstract: The invention is to a method for plasma spraying a ceramic or plastic material on selected areas of leads to form stabilizer/spacers for the leads.Type: GrantFiled: January 7, 1992Date of Patent: December 7, 1993Assignee: Texas Instruments IncorporatedInventor: Donald C. Abbott
-
Patent number: 5250842Abstract: In a tape automated bonding (TAB) tape used in a semiconductor device, there is provided at each of the corners of a square opening therein a projection inwards the opening instead of the conventional right angle corner. This projection is left when said opening is cut in the base tape or when metal foil on the base tape is selectively etched. According to the present invention, gap between each corner of the opening and each corner of a semiconductor chip can be reduced in virtue of the above-mentioned projection, this permitting to prevent resin to be applied for coating a semiconductor chip and the inner leads to be bonded to it from dripping through the corner.Type: GrantFiled: September 5, 1991Date of Patent: October 5, 1993Assignee: NEC CorporationInventor: Yukihito Ikeda
-
Patent number: 5227661Abstract: A lead over chip packaged device that is less prone to package cracking during surface mounting is disclosed. The lead over chip lead frame overlies the active face of a semiconductor circuit. The backside of the semiconductor circuit is covered with an aminopropyltriethoxysilane coating. The aminopropyltriethoxysilane coating promotes adhesion between the backside of the semiconductor circuit and the mold compound used to encapsulate the device. This reduces package cracking resulting from delamination between the inactive face of the chip and the mold compound during reflow solder.Type: GrantFiled: September 24, 1990Date of Patent: July 13, 1993Assignee: Texas Instruments IncorporatedInventor: Katherine G. Heinen
-
Patent number: 5184207Abstract: A lead pack which includes a frame of polymer insulating material and a plurality of leads imbedded in said frame and extending inwardly and outwardly therefrom for attachment to an associated integrated circuit and for attachment of the leaded integrated circuit to an associated printed wiring board or like circuit. The insulating frame serves as a dam or sealing means in an encapsulating process. The same or an additional frame stabilizes and positions the outwardly extending ends of the leads. A reusable transport and test tape which includes a plurality of insulated conductors adapted to receive and connect to the leads of the lead pack and to position the lead pack for reception of an integrated circuit for bonding of lead pack leads to the contact pads of the integrated circuit and to move the lead pack and integrated circuit into succeeding processing stations where the circuit is packaged and tested and lead formed, and then excised.Type: GrantFiled: October 31, 1990Date of Patent: February 2, 1993Assignee: TribotechInventor: Earl S. Cain